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qmk_firmware

custom branch of QMK firmware git clone https://anongit.hacktivis.me/git/qmk_firmware.git

mcuconf.h (21338B)

    

  1. /*
  2.     ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
  4.     Licensed under the Apache License, Version 2.0 (the "License");
  5.     you may not use this file except in compliance with the License.
  6.     You may obtain a copy of the License at
  8.         http://www.apache.org/licenses/LICENSE-2.0
  10.     Unless required by applicable law or agreed to in writing, software
  11.     distributed under the License is distributed on an "AS IS" BASIS,
  12.     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13.     See the License for the specific language governing permissions and
  14.     limitations under the License.
  15. */
  17. #ifndef MCUCONF_H
  18. #define MCUCONF_H
  20. /*
  21.  * STM32H723/33/25/35 drivers configuration.
  22.  * The following settings override the default settings present in
  23.  * the various device driver implementation headers.
  24.  * Note that the settings for each driver only have effect if the whole
  25.  * driver is enabled in halconf.h.
  26.  *
  27.  * IRQ priorities:
  28.  * 15...0       Lowest...Highest.
  29.  *
  30.  * DMA priorities:
  31.  * 0...3        Lowest...Highest.
  32.  */
  34. #define STM32H7xx_MCUCONF
  35. #define STM32H723_MCUCONF
  36. #define STM32H733_MCUCONF
  37. #define STM32H725_MCUCONF
  38. #define STM32H735_MCUCONF
  40. /*
  41.  * General settings.
  42.  */
  43. #define STM32_NO_INIT                       FALSE
  45. /*
  46.  * Memory attributes settings.
  47.  */
  48. #define STM32_NOCACHE_ENABLE                FALSE
  49. #define STM32_NOCACHE_MPU_REGION            MPU_REGION_6
  50. #define STM32_NOCACHE_RBAR                  0x24000000U
  51. #define STM32_NOCACHE_RASR                  MPU_RASR_SIZE_16K
  53. /*
  54.  * PWR system settings.
  55.  * Reading STM32 Reference Manual is required, settings in PWR_CR3 are
  56.  * very critical.
  57.  * Register constants are taken from the ST header.
  58.  */
  59. #define STM32_VOS                           STM32_VOS_SCALE0
  60. #define STM32_PWR_CR1                       (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
  61. #define STM32_PWR_CR2                       (PWR_CR2_BREN)
  62. #define STM32_PWR_CR3                       (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
  63. #define STM32_PWR_CPUCR                     0
  65. /*
  66.  * Clock tree static settings.
  67.  * Reading STM32 Reference Manual is required.
  68.  */
  69. #define STM32_HSI_ENABLED                   TRUE
  70. #define STM32_LSI_ENABLED                   FALSE
  71. #define STM32_CSI_ENABLED                   FALSE
  72. #define STM32_HSI48_ENABLED                 TRUE
  73. #define STM32_HSE_ENABLED                   TRUE
  74. #define STM32_LSE_ENABLED                   FALSE
  75. #define STM32_HSIDIV                        STM32_HSIDIV_DIV1
  77. /*
  78.  * PLLs static settings.
  79.  * Reading STM32 Reference Manual is required.
  80.  */
  81. #define STM32_PLLSRC                        STM32_PLLSRC_HSE_CK
  82. #define STM32_PLLCFGR_MASK                  ~0
  83. #define STM32_PLL1_ENABLED                  TRUE
  84. #define STM32_PLL1_P_ENABLED                TRUE
  85. #define STM32_PLL1_Q_ENABLED                TRUE
  86. #define STM32_PLL1_R_ENABLED                TRUE
  87. #define STM32_PLL1_DIVM_VALUE               4
  88. #define STM32_PLL1_DIVN_VALUE               275
  89. #define STM32_PLL1_FRACN_VALUE              0
  90. #define STM32_PLL1_DIVP_VALUE               1
  91. #define STM32_PLL1_DIVQ_VALUE               10
  92. #define STM32_PLL1_DIVR_VALUE               4
  93. #define STM32_PLL2_ENABLED                  TRUE
  94. #define STM32_PLL2_P_ENABLED                TRUE
  95. #define STM32_PLL2_Q_ENABLED                TRUE
  96. #define STM32_PLL2_R_ENABLED                TRUE
  97. #define STM32_PLL2_DIVM_VALUE               4
  98. #define STM32_PLL2_DIVN_VALUE               400
  99. #define STM32_PLL2_FRACN_VALUE              0
  100. #define STM32_PLL2_DIVP_VALUE               40
  101. #define STM32_PLL2_DIVQ_VALUE               8
  102. #define STM32_PLL2_DIVR_VALUE               8
  103. #define STM32_PLL3_ENABLED                  TRUE
  104. #define STM32_PLL3_P_ENABLED                TRUE
  105. #define STM32_PLL3_Q_ENABLED                TRUE
  106. #define STM32_PLL3_R_ENABLED                TRUE
  107. #define STM32_PLL3_DIVM_VALUE               4
  108. #define STM32_PLL3_DIVN_VALUE               240
  109. #define STM32_PLL3_FRACN_VALUE              0
  110. #define STM32_PLL3_DIVP_VALUE               10
  111. #define STM32_PLL3_DIVQ_VALUE               10
  112. #define STM32_PLL3_DIVR_VALUE               10
  114. /*
  115.  * Core clocks dynamic settings (can be changed at runtime).
  116.  * Reading STM32 Reference Manual is required.
  117.  */
  118. #define STM32_SW                            STM32_SW_PLL1_P_CK
  119. #define STM32_RTCSEL                        STM32_RTCSEL_LSI_CK
  120. #define STM32_D1CPRE                        STM32_D1CPRE_DIV1
  121. #define STM32_D1HPRE                        STM32_D1HPRE_DIV2
  122. #define STM32_D1PPRE3                       STM32_D1PPRE3_DIV2
  123. #define STM32_D2PPRE1                       STM32_D2PPRE1_DIV2
  124. #define STM32_D2PPRE2                       STM32_D2PPRE2_DIV2
  125. #define STM32_D3PPRE4                       STM32_D3PPRE4_DIV2
  127. /*
  128.  * Peripherals clocks static settings.
  129.  * Reading STM32 Reference Manual is required.
  130.  */
  131. #define STM32_MCO1SEL                       STM32_MCO1SEL_HSI_CK
  132. #define STM32_MCO1PRE_VALUE                 4
  133. #define STM32_MCO2SEL                       STM32_MCO2SEL_SYS_CK
  134. #define STM32_MCO2PRE_VALUE                 4
  135. #define STM32_TIMPRE_ENABLE                 TRUE
  136. #define STM32_HRTIMSEL                      0
  137. #define STM32_STOPKERWUCK                   0
  138. #define STM32_STOPWUCK                      0
  139. #define STM32_RTCPRE_VALUE                  8
  140. #define STM32_CKPERSEL                      STM32_CKPERSEL_HSE_CK
  141. #define STM32_SDMMCSEL                      STM32_SDMMCSEL_PLL1_Q_CK
  142. #define STM32_OCTOSPISEL                    STM32_OCTOSPISEL_HCLK
  143. #define STM32_FMCSEL                        STM32_FMCSEL_HCLK
  144. #define STM32_SWPSEL                        STM32_SWPSEL_PCLK1
  145. #define STM32_FDCANSEL                      STM32_FDCANSEL_HSE_CK
  146. #define STM32_DFSDM1SEL                     STM32_DFSDM1SEL_PCLK2
  147. #define STM32_SPDIFSEL                      STM32_SPDIFSEL_PLL1_Q_CK
  148. #define STM32_SPI45SEL                      STM32_SPI45SEL_PCLK2
  149. #define STM32_SPI123SEL                     STM32_SPI123SEL_PLL1_Q_CK
  150. #define STM32_SAI1SEL                       STM32_SAI1SEL_PLL1_Q_CK
  151. #define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK1
  152. #define STM32_CECSEL                        STM32_CECSEL_LSE_CK
  153. #define STM32_USBSEL                        STM32_USBSEL_PLL3_Q_CK
  154. #define STM32_I2C1235SEL                    STM32_I2C1235SEL_PCLK1
  155. #define STM32_RNGSEL                        STM32_RNGSEL_PLL1_Q_CK
  156. #define STM32_USART16910SEL                 STM32_USART16910SEL_PCLK2
  157. #define STM32_USART234578SEL                STM32_USART234578SEL_PCLK1
  158. #define STM32_SPI6SEL                       STM32_SPI6SEL_PCLK4
  159. #define STM32_SAI4BSEL                      STM32_SAI4BSEL_PLL1_Q_CK
  160. #define STM32_SAI4ASEL                      STM32_SAI4ASEL_PLL1_Q_CK
  161. #define STM32_ADCSEL                        STM32_ADCSEL_PLL2_P_CK
  162. #define STM32_LPTIM345SEL                   STM32_LPTIM345SEL_PCLK4
  163. #define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK4
  164. #define STM32_I2C4SEL                       STM32_I2C4SEL_PCLK4
  165. #define STM32_LPUART1SEL                    STM32_LPUART1SEL_PCLK4
  167. /*
  168.  * IRQ system settings.
  169.  */
  170. #define STM32_IRQ_EXTI0_PRIORITY            6
  171. #define STM32_IRQ_EXTI1_PRIORITY            6
  172. #define STM32_IRQ_EXTI2_PRIORITY            6
  173. #define STM32_IRQ_EXTI3_PRIORITY            6
  174. #define STM32_IRQ_EXTI4_PRIORITY            6
  175. #define STM32_IRQ_EXTI5_9_PRIORITY          6
  176. #define STM32_IRQ_EXTI10_15_PRIORITY        6
  177. #define STM32_IRQ_EXTI16_PRIORITY           6
  178. #define STM32_IRQ_EXTI17_PRIORITY           6
  179. #define STM32_IRQ_EXTI18_PRIORITY           6
  180. #define STM32_IRQ_EXTI19_PRIORITY           6
  181. #define STM32_IRQ_EXTI20_21_PRIORITY        6
  183. #define STM32_IRQ_FDCAN1_PRIORITY           10
  184. #define STM32_IRQ_FDCAN2_PRIORITY           10
  185. #define STM32_IRQ_FDCAN3_PRIORITY           10
  187. #define STM32_IRQ_MDMA_PRIORITY             9
  189. #define STM32_IRQ_OCTOSPI1_PRIORITY         10
  190. #define STM32_IRQ_OCTOSPI2_PRIORITY         10
  192. #define STM32_IRQ_SDMMC1_PRIORITY           9
  193. #define STM32_IRQ_SDMMC2_PRIORITY           9
  195. #define STM32_IRQ_TIM1_UP_PRIORITY          7
  196. #define STM32_IRQ_TIM1_CC_PRIORITY          7
  197. #define STM32_IRQ_TIM2_PRIORITY             7
  198. #define STM32_IRQ_TIM3_PRIORITY             7
  199. #define STM32_IRQ_TIM4_PRIORITY             7
  200. #define STM32_IRQ_TIM5_PRIORITY             7
  201. #define STM32_IRQ_TIM6_PRIORITY             7
  202. #define STM32_IRQ_TIM7_PRIORITY             7
  203. #define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY   7
  204. #define STM32_IRQ_TIM8_UP_TIM13_PRIORITY    7
  205. #define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
  206. #define STM32_IRQ_TIM8_CC_PRIORITY          7
  207. #define STM32_IRQ_TIM15_PRIORITY            7
  208. #define STM32_IRQ_TIM16_PRIORITY            7
  209. #define STM32_IRQ_TIM17_PRIORITY            7
  211. #define STM32_IRQ_USART1_PRIORITY           12
  212. #define STM32_IRQ_USART2_PRIORITY           12
  213. #define STM32_IRQ_USART3_PRIORITY           12
  214. #define STM32_IRQ_UART4_PRIORITY            12
  215. #define STM32_IRQ_UART5_PRIORITY            12
  216. #define STM32_IRQ_USART6_PRIORITY           12
  217. #define STM32_IRQ_UART7_PRIORITY            12
  218. #define STM32_IRQ_UART8_PRIORITY            12
  219. #define STM32_IRQ_UART9_PRIORITY            12
  220. #define STM32_IRQ_USART10_PRIORITY          12
  221. #define STM32_IRQ_LPUART1_PRIORITY          12
  223. /*
  224.  * ADC driver system settings.
  225.  */
  226. #define STM32_ADC_DUAL_MODE                 FALSE
  227. #define STM32_ADC_SAMPLES_SIZE              16
  228. #define STM32_ADC_USE_ADC12                 FALSE
  229. #define STM32_ADC_ADC12_DMA_STREAM          STM32_DMA_STREAM_ID_ANY
  230. #define STM32_ADC_ADC12_DMA_PRIORITY        2
  231. #define STM32_ADC_ADC12_IRQ_PRIORITY        5
  232. #define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV4
  234. /*
  235.  * CAN driver system settings.
  236.  */
  237. #define STM32_CAN_USE_FDCAN1                FALSE
  238. #define STM32_CAN_USE_FDCAN2                FALSE
  239. #define STM32_CAN_USE_FDCAN3                FALSE
  241. /*
  242.  * DAC driver system settings.
  243.  */
  244. #define STM32_DAC_DUAL_MODE                 FALSE
  245. #define STM32_DAC_USE_DAC1_CH1              FALSE
  246. #define STM32_DAC_USE_DAC1_CH2              FALSE
  247. #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     10
  248. #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     10
  249. #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
  250. #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
  251. #define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
  252. #define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
  254. /*
  255.  * GPT driver system settings.
  256.  */
  257. #define STM32_GPT_USE_TIM1                  FALSE
  258. #define STM32_GPT_USE_TIM2                  FALSE
  259. #define STM32_GPT_USE_TIM3                  FALSE
  260. #define STM32_GPT_USE_TIM4                  FALSE
  261. #define STM32_GPT_USE_TIM5                  FALSE
  262. #define STM32_GPT_USE_TIM6                  FALSE
  263. #define STM32_GPT_USE_TIM7                  FALSE
  264. #define STM32_GPT_USE_TIM8                  FALSE
  265. #define STM32_GPT_USE_TIM12                 FALSE
  266. #define STM32_GPT_USE_TIM13                 FALSE
  267. #define STM32_GPT_USE_TIM14                 FALSE
  268. #define STM32_GPT_USE_TIM15                 FALSE
  269. #define STM32_GPT_USE_TIM16                 FALSE
  270. #define STM32_GPT_USE_TIM17                 FALSE
  272. /*
  273.  * I2C driver system settings.
  274.  */
  275. #define STM32_I2C_USE_I2C1                  FALSE
  276. #define STM32_I2C_USE_I2C2                  FALSE
  277. #define STM32_I2C_USE_I2C3                  FALSE
  278. #define STM32_I2C_USE_I2C4                  FALSE
  279. #define STM32_I2C_BUSY_TIMEOUT              50
  280. #define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  281. #define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  282. #define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  283. #define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  284. #define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  285. #define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  286. #define STM32_I2C_I2C4_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY
  287. #define STM32_I2C_I2C4_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY
  288. #define STM32_I2C_I2C1_IRQ_PRIORITY         5
  289. #define STM32_I2C_I2C2_IRQ_PRIORITY         5
  290. #define STM32_I2C_I2C3_IRQ_PRIORITY         5
  291. #define STM32_I2C_I2C4_IRQ_PRIORITY         5
  292. #define STM32_I2C_I2C1_DMA_PRIORITY         3
  293. #define STM32_I2C_I2C2_DMA_PRIORITY         3
  294. #define STM32_I2C_I2C3_DMA_PRIORITY         3
  295. #define STM32_I2C_I2C4_DMA_PRIORITY         3
  296. #define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
  298. /*
  299.  * ICU driver system settings.
  300.  */
  301. #define STM32_ICU_USE_TIM1                  FALSE
  302. #define STM32_ICU_USE_TIM2                  FALSE
  303. #define STM32_ICU_USE_TIM3                  FALSE
  304. #define STM32_ICU_USE_TIM4                  FALSE
  305. #define STM32_ICU_USE_TIM5                  FALSE
  306. #define STM32_ICU_USE_TIM8                  FALSE
  307. #define STM32_ICU_USE_TIM12                 FALSE
  308. #define STM32_ICU_USE_TIM13                 FALSE
  309. #define STM32_ICU_USE_TIM14                 FALSE
  310. #define STM32_ICU_USE_TIM15                 FALSE
  311. #define STM32_ICU_USE_TIM16                 FALSE
  312. #define STM32_ICU_USE_TIM17                 FALSE
  314. /*
  315.  * MAC driver system settings.
  316.  */
  317. #define STM32_MAC_TRANSMIT_BUFFERS          2
  318. #define STM32_MAC_RECEIVE_BUFFERS           4
  319. #define STM32_MAC_BUFFERS_SIZE              1522
  320. #define STM32_MAC_PHY_TIMEOUT               100
  321. #define STM32_MAC_ETH1_CHANGE_PHY_STATE     TRUE
  322. #define STM32_MAC_ETH1_IRQ_PRIORITY         13
  323. #define STM32_MAC_IP_CHECKSUM_OFFLOAD       0
  325. /*
  326.  * PWM driver system settings.
  327.  */
  328. #define STM32_PWM_USE_TIM1                  FALSE
  329. #define STM32_PWM_USE_TIM2                  FALSE
  330. #define STM32_PWM_USE_TIM3                  FALSE
  331. #define STM32_PWM_USE_TIM4                  FALSE
  332. #define STM32_PWM_USE_TIM5                  FALSE
  333. #define STM32_PWM_USE_TIM8                  FALSE
  334. #define STM32_PWM_USE_TIM12                 FALSE
  335. #define STM32_PWM_USE_TIM13                 FALSE
  336. #define STM32_PWM_USE_TIM14                 FALSE
  337. #define STM32_PWM_USE_TIM15                 FALSE
  338. #define STM32_PWM_USE_TIM16                 FALSE
  339. #define STM32_PWM_USE_TIM17                 FALSE
  341. /*
  342.  * RTC driver system settings.
  343.  */
  344. #define STM32_RTC_PRESA_VALUE               32
  345. #define STM32_RTC_PRESS_VALUE               1024
  346. #define STM32_RTC_CR_INIT                   0
  347. #define STM32_RTC_TAMPCR_INIT               0
  349. /*
  350.  * SDC driver system settings.
  351.  */
  352. #define STM32_SDC_USE_SDMMC1                FALSE
  353. #define STM32_SDC_USE_SDMMC2                FALSE
  354. #define STM32_SDC_SDMMC_UNALIGNED_SUPPORT   TRUE
  355. #define STM32_SDC_SDMMC_WRITE_TIMEOUT       10000
  356. #define STM32_SDC_SDMMC_READ_TIMEOUT        10000
  357. #define STM32_SDC_SDMMC_CLOCK_DELAY         10
  358. #define STM32_SDC_SDMMC_PWRSAV              TRUE
  360. /*
  361.  * SERIAL driver system settings.
  362.  */
  363. #define STM32_SERIAL_USE_USART1             FALSE
  364. #define STM32_SERIAL_USE_USART2             FALSE
  365. #define STM32_SERIAL_USE_USART3             FALSE
  366. #define STM32_SERIAL_USE_UART4              FALSE
  367. #define STM32_SERIAL_USE_UART5              FALSE
  368. #define STM32_SERIAL_USE_USART6             FALSE
  369. #define STM32_SERIAL_USE_UART7              FALSE
  370. #define STM32_SERIAL_USE_UART8              FALSE
  371. #define STM32_SERIAL_USE_UART9              FALSE
  372. #define STM32_SERIAL_USE_USART10            FALSE
  373. #define STM32_SERIAL_USE_LPUART1            FALSE
  375. /*
  376.  * SIO driver system settings.
  377.  */
  378. #define STM32_SIO_USE_USART1                FALSE
  379. #define STM32_SIO_USE_USART2                FALSE
  380. #define STM32_SIO_USE_USART3                FALSE
  381. #define STM32_SIO_USE_UART4                 FALSE
  382. #define STM32_SIO_USE_UART5                 FALSE
  383. #define STM32_SIO_USE_USART6                FALSE
  384. #define STM32_SIO_USE_UART7                 FALSE
  385. #define STM32_SIO_USE_UART8                 FALSE
  386. #define STM32_SIO_USE_UART9                 FALSE
  387. #define STM32_SIO_USE_USART10               FALSE
  388. #define STM32_SIO_USE_LPUART1               FALSE
  390. /*
  391.  * SPI driver system settings.
  392.  */
  393. #define STM32_SPI_USE_SPI1                  FALSE
  394. #define STM32_SPI_USE_SPI2                  FALSE
  395. #define STM32_SPI_USE_SPI3                  FALSE
  396. #define STM32_SPI_USE_SPI4                  FALSE
  397. #define STM32_SPI_USE_SPI5                  FALSE
  398. #define STM32_SPI_USE_SPI6                  FALSE
  399. #define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  400. #define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  401. #define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  402. #define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  403. #define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  404. #define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  405. #define STM32_SPI_SPI4_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  406. #define STM32_SPI_SPI4_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  407. #define STM32_SPI_SPI5_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  408. #define STM32_SPI_SPI5_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  409. #define STM32_SPI_SPI6_RX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY
  410. #define STM32_SPI_SPI6_TX_BDMA_STREAM       STM32_BDMA_STREAM_ID_ANY
  411. #define STM32_SPI_SPI1_DMA_PRIORITY         1
  412. #define STM32_SPI_SPI2_DMA_PRIORITY         1
  413. #define STM32_SPI_SPI3_DMA_PRIORITY         1
  414. #define STM32_SPI_SPI4_DMA_PRIORITY         1
  415. #define STM32_SPI_SPI5_DMA_PRIORITY         1
  416. #define STM32_SPI_SPI6_DMA_PRIORITY         1
  417. #define STM32_SPI_SPI1_IRQ_PRIORITY         10
  418. #define STM32_SPI_SPI2_IRQ_PRIORITY         10
  419. #define STM32_SPI_SPI3_IRQ_PRIORITY         10
  420. #define STM32_SPI_SPI4_IRQ_PRIORITY         10
  421. #define STM32_SPI_SPI5_IRQ_PRIORITY         10
  422. #define STM32_SPI_SPI6_IRQ_PRIORITY         10
  423. #define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
  425. /*
  426.  * ST driver system settings.
  427.  */
  428. #define STM32_ST_IRQ_PRIORITY               8
  429. #define STM32_ST_USE_TIMER                  2
  431. /*
  432.  * TRNG driver system settings.
  433.  */
  434. #define STM32_TRNG_USE_RNG1                 FALSE
  436. /*
  437.  * UART driver system settings.
  438.  */
  439. #define STM32_UART_USE_USART1               FALSE
  440. #define STM32_UART_USE_USART2               FALSE
  441. #define STM32_UART_USE_USART3               FALSE
  442. #define STM32_UART_USE_UART4                FALSE
  443. #define STM32_UART_USE_UART5                FALSE
  444. #define STM32_UART_USE_USART6               FALSE
  445. #define STM32_UART_USE_UART7                FALSE
  446. #define STM32_UART_USE_UART8                FALSE
  447. #define STM32_UART_USE_UART9                FALSE
  448. #define STM32_UART_USE_USART10              FALSE
  449. #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  450. #define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  451. #define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  452. #define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  453. #define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  454. #define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  455. #define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  456. #define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  457. #define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  458. #define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  459. #define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  460. #define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  461. #define STM32_UART_UART7_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  462. #define STM32_UART_UART7_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  463. #define STM32_UART_UART8_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  464. #define STM32_UART_UART8_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  465. #define STM32_UART_UART9_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  466. #define STM32_UART_UART9_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  467. #define STM32_UART_USART10_RX_DMA_STREAM    STM32_DMA_STREAM_ID_ANY
  468. #define STM32_UART_USART10_TX_DMA_STREAM    STM32_DMA_STREAM_ID_ANY
  469. #define STM32_UART_USART1_DMA_PRIORITY      0
  470. #define STM32_UART_USART2_DMA_PRIORITY      0
  471. #define STM32_UART_USART3_DMA_PRIORITY      0
  472. #define STM32_UART_UART4_DMA_PRIORITY       0
  473. #define STM32_UART_UART5_DMA_PRIORITY       0
  474. #define STM32_UART_USART6_DMA_PRIORITY      0
  475. #define STM32_UART_UART7_DMA_PRIORITY       0
  476. #define STM32_UART_UART8_DMA_PRIORITY       0
  477. #define STM32_UART_UART9_DMA_PRIORITY       0
  478. #define STM32_UART_USART10_DMA_PRIORITY     0
  479. #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
  481. /*
  482.  * USB driver system settings.
  483.  */
  484. #define STM32_USB_USE_OTG2                  TRUE
  485. #define STM32_USB_OTG2_IRQ_PRIORITY         14
  486. #define STM32_USB_OTG2_RX_FIFO_SIZE         1024
  487. #define STM32_USB_HOST_WAKEUP_DURATION      2
  489. /*
  490.  * WDG driver system settings.
  491.  */
  492. #define STM32_WDG_USE_IWDG                  FALSE
  494. /*
  495.  * WSPI driver system settings.
  496.  */
  497. #define STM32_WSPI_USE_OCTOSPI1             FALSE
  498. #define STM32_WSPI_USE_OCTOSPI2             FALSE
  499. #define STM32_WSPI_OCTOSPI1_PRESCALER_VALUE 1
  500. #define STM32_WSPI_OCTOSPI2_PRESCALER_VALUE 1
  501. #define STM32_WSPI_OCTOSPI1_SSHIFT          FALSE
  502. #define STM32_WSPI_OCTOSPI2_SSHIFT          FALSE
  503. #define STM32_WSPI_OCTOSPI1_DHQC            FALSE
  504. #define STM32_WSPI_OCTOSPI2_DHQC            FALSE
  505. #define STM32_WSPI_OCTOSPI1_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
  506. #define STM32_WSPI_OCTOSPI2_MDMA_CHANNEL    STM32_MDMA_CHANNEL_ID_ANY
  507. #define STM32_WSPI_OCTOSPI1_MDMA_PRIORITY   1
  508. #define STM32_WSPI_OCTOSPI2_MDMA_PRIORITY   1
  509. #define STM32_WSPI_OCTOSPI1_MDMA_IRQ_PRIORITY 10
  510. #define STM32_WSPI_OCTOSPI2_MDMA_IRQ_PRIORITY 10
  511. #define STM32_WSPI_DMA_ERROR_HOOK(wspip)    osalSysHalt("MDMA failure")
  513. #endif /* MCUCONF_H */