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qmk_firmware

custom branch of QMK firmware git clone https://anongit.hacktivis.me/git/qmk_firmware.git

mcuconf.h (12507B)

    

  1. /*
  2.     ChibiOS - Copyright (C) 2006..2020 Giovanni Di Sirio
  4.     Licensed under the Apache License, Version 2.0 (the "License");
  5.     you may not use this file except in compliance with the License.
  6.     You may obtain a copy of the License at
  8.         http://www.apache.org/licenses/LICENSE-2.0
  10.     Unless required by applicable law or agreed to in writing, software
  11.     distributed under the License is distributed on an "AS IS" BASIS,
  12.     WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13.     See the License for the specific language governing permissions and
  14.     limitations under the License.
  15. */
  17. /*
  18.  * STM32G0xx drivers configuration.
  19.  * The following settings override the default settings present in
  20.  * the various device driver implementation headers.
  21.  * Note that the settings for each driver only have effect if the whole
  22.  * driver is enabled in halconf.h.
  23.  *
  24.  * IRQ priorities:
  25.  * 3...0        Lowest...Highest.
  26.  *
  27.  * DMA priorities:
  28.  * 0...3        Lowest...Highest.
  29.  */
  31. #ifndef MCUCONF_H
  32. #define MCUCONF_H
  34. #define STM32G0xx_MCUCONF
  35. #define STM32G0B1_MCUCONF
  36. #define STM32G0C1_MCUCONF
  38. /*
  39.  * HAL driver system settings.
  40.  */
  41. #define STM32_NO_INIT                       FALSE
  42. #define STM32_CLOCK_DYNAMIC                 TRUE
  43. #define STM32_VOS                           STM32_VOS_RANGE1
  44. #define STM32_PWR_CR2                       (STM32_PVDRT_LEV0 | STM32_PVDFT_LEV0 | STM32_PVDE_DISABLED)
  45. #define STM32_PWR_CR3                       (PWR_CR3_EIWUL)
  46. #define STM32_PWR_CR4                       (0U)
  47. #define STM32_PWR_PUCRA                     (0U)
  48. #define STM32_PWR_PDCRA                     (0U)
  49. #define STM32_PWR_PUCRB                     (0U)
  50. #define STM32_PWR_PDCRB                     (0U)
  51. #define STM32_PWR_PUCRC                     (0U)
  52. #define STM32_PWR_PDCRC                     (0U)
  53. #define STM32_PWR_PUCRD                     (0U)
  54. #define STM32_PWR_PDCRD                     (0U)
  55. #define STM32_PWR_PUCRE                     (0U)
  56. #define STM32_PWR_PDCRE                     (0U)
  57. #define STM32_PWR_PUCRF                     (0U)
  58. #define STM32_PWR_PDCRF                     (0U)
  59. #define STM32_HSIDIV_VALUE                  1
  60. #define STM32_HSI16_ENABLED                 TRUE
  61. #define STM32_HSI48_ENABLED                 TRUE
  62. #define STM32_HSE_ENABLED                   FALSE
  63. #define STM32_LSI_ENABLED                   FALSE
  64. #define STM32_LSE_ENABLED                   FALSE
  65. #define STM32_SW                            STM32_SW_PLLRCLK
  66. #define STM32_PLLSRC                        STM32_PLLSRC_HSI16
  67. #define STM32_PLLM_VALUE                    2
  68. #define STM32_PLLN_VALUE                    16
  69. #define STM32_PLLP_VALUE                    2
  70. #define STM32_PLLQ_VALUE                    4
  71. #define STM32_PLLR_VALUE                    2
  72. #define STM32_HPRE                          STM32_HPRE_DIV1
  73. #define STM32_PPRE                          STM32_PPRE_DIV1
  74. #define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
  75. #define STM32_MCOPRE                        STM32_MCOPRE_DIV1
  76. #define STM32_LSCOSEL                       STM32_LSCOSEL_NOCLOCK
  78. /*
  79.  * Peripherals clocks and sources.
  80.  */
  81. #define STM32_FDCANSEL                      STM32_USBSEL_HSI48
  82. #define STM32_USBSEL                        STM32_USBSEL_HSI48
  83. #define STM32_USART1SEL                     STM32_USART1SEL_SYSCLK
  84. #define STM32_USART2SEL                     STM32_USART2SEL_SYSCLK
  85. #define STM32_USART3SEL                     STM32_USART3SEL_SYSCLK
  86. #define STM32_LPUART1SEL                    STM32_LPUART1SEL_SYSCLK
  87. #define STM32_LPUART2SEL                    STM32_LPUART2SEL_SYSCLK
  88. #define STM32_CECSEL                        STM32_CECSEL_HSI16DIV
  89. #define STM32_I2C1SEL                       STM32_I2C1SEL_PCLK
  90. #define STM32_I2C2SEL                       STM32_I2C1SEL_PCLK
  91. #define STM32_I2S1SEL                       STM32_I2S1SEL_SYSCLK
  92. #define STM32_I2S2SEL                       STM32_I2S2SEL_SYSCLK
  93. #define STM32_LPTIM1SEL                     STM32_LPTIM1SEL_PCLK
  94. #define STM32_LPTIM2SEL                     STM32_LPTIM2SEL_PCLK
  95. #define STM32_TIM1SEL                       STM32_TIM1SEL_TIMPCLK
  96. #define STM32_TIM15SEL                      STM32_TIM15SEL_TIMPCLK
  97. #define STM32_RNGSEL                        STM32_RNGSEL_HSI16
  98. #define STM32_RNGDIV_VALUE                  1
  99. #define STM32_ADCSEL                        STM32_ADCSEL_PLLPCLK
  100. #define STM32_RTCSEL                        STM32_RTCSEL_NOCLOCK
  102. /*
  103.  * Shared IRQ settings.
  104.  */
  105. #define STM32_IRQ_EXTI0_1_PRIORITY          3
  106. #define STM32_IRQ_EXTI2_3_PRIORITY          3
  107. #define STM32_IRQ_EXTI4_15_PRIORITY         3
  108. #define STM32_IRQ_EXTI1921_PRIORITY         3
  110. #define STM32_IRQ_USART1_PRIORITY           2
  111. #define STM32_IRQ_USART2_LP2_PRIORITY       2
  112. #define STM32_IRQ_USART3_4_5_6_LP1_PRIORITY 2
  114. #define STM32_IRQ_TIM1_UP_PRIORITY          1
  115. #define STM32_IRQ_TIM1_CC_PRIORITY          1
  116. #define STM32_IRQ_TIM2_PRIORITY             1
  117. #define STM32_IRQ_TIM3_4_PRIORITY           1
  118. #define STM32_IRQ_TIM6_PRIORITY             1
  119. #define STM32_IRQ_TIM7_PRIORITY             1
  120. #define STM32_IRQ_TIM14_PRIORITY            1
  121. #define STM32_IRQ_TIM15_PRIORITY            1
  122. #define STM32_IRQ_TIM16_PRIORITY            1
  123. #define STM32_IRQ_TIM17_PRIORITY            1
  125. /*
  126.  * ADC driver system settings.
  127.  */
  128. #define STM32_ADC_USE_ADC1                  FALSE
  129. #define STM32_ADC_ADC1_CFGR2                ADC_CFGR2_CKMODE_ADCCLK
  130. #define STM32_ADC_ADC1_DMA_PRIORITY         2
  131. #define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     2
  132. #define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID_ANY
  133. #define STM32_ADC_PRESCALER_VALUE           2
  135. /*
  136.  * DAC driver system settings.
  137.  */
  138. #define STM32_DAC_DUAL_MODE                 FALSE
  139. #define STM32_DAC_USE_DAC1_CH1              FALSE
  140. #define STM32_DAC_USE_DAC1_CH2              FALSE
  141. #define STM32_DAC_DAC1_CH1_IRQ_PRIORITY     3
  142. #define STM32_DAC_DAC1_CH2_IRQ_PRIORITY     3
  143. #define STM32_DAC_DAC1_CH1_DMA_PRIORITY     2
  144. #define STM32_DAC_DAC1_CH2_DMA_PRIORITY     2
  145. #define STM32_DAC_DAC1_CH1_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
  146. #define STM32_DAC_DAC1_CH2_DMA_STREAM       STM32_DMA_STREAM_ID_ANY
  148. /*
  149.  * GPT driver system settings.
  150.  */
  151. #define STM32_GPT_USE_TIM1                  FALSE
  152. #define STM32_GPT_USE_TIM2                  FALSE
  153. #define STM32_GPT_USE_TIM3                  FALSE
  154. #define STM32_GPT_USE_TIM4                  FALSE
  155. #define STM32_GPT_USE_TIM6                  FALSE
  156. #define STM32_GPT_USE_TIM7                  FALSE
  157. #define STM32_GPT_USE_TIM14                 FALSE
  158. #define STM32_GPT_USE_TIM15                 FALSE
  159. #define STM32_GPT_USE_TIM16                 FALSE
  160. #define STM32_GPT_USE_TIM17                 FALSE
  162. /*
  163.  * I2C driver system settings.
  164.  */
  165. #define STM32_I2C_USE_I2C1                  FALSE
  166. #define STM32_I2C_USE_I2C2                  FALSE
  167. #define STM32_I2C_USE_I2C3                  FALSE
  168. #define STM32_I2C_BUSY_TIMEOUT              50
  169. #define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  170. #define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  171. #define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  172. #define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  173. #define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  174. #define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  175. #define STM32_I2C_I2C1_IRQ_PRIORITY         3
  176. #define STM32_I2C_I2C2_IRQ_PRIORITY         3
  177. #define STM32_I2C_I2C1_DMA_PRIORITY         3
  178. #define STM32_I2C_I2C2_DMA_PRIORITY         3
  179. #define STM32_I2C_DMA_ERROR_HOOK(i2cp)      osalSysHalt("DMA failure")
  181. /*
  182.  * ICU driver system settings.
  183.  */
  184. #define STM32_ICU_USE_TIM1                  FALSE
  185. #define STM32_ICU_USE_TIM2                  FALSE
  186. #define STM32_ICU_USE_TIM3                  FALSE
  187. #define STM32_ICU_USE_TIM4                  FALSE
  188. #define STM32_ICU_USE_TIM15                 FALSE
  190. /*
  191.  * PWM driver system settings.
  192.  */
  193. #define STM32_PWM_USE_TIM1                  FALSE
  194. #define STM32_PWM_USE_TIM2                  FALSE
  195. #define STM32_PWM_USE_TIM3                  FALSE
  196. #define STM32_PWM_USE_TIM4                  FALSE
  197. #define STM32_PWM_USE_TIM14                 FALSE
  198. #define STM32_PWM_USE_TIM15                 FALSE
  199. #define STM32_PWM_USE_TIM16                 FALSE
  200. #define STM32_PWM_USE_TIM17                 FALSE
  202. /*
  203.  * RTC driver system settings.
  204.  */
  205. #define STM32_RTC_PRESA_VALUE               32
  206. #define STM32_RTC_PRESS_VALUE               1024
  207. #define STM32_RTC_CR_INIT                   0
  208. #define STM32_RTC_TAMPCR_INIT               0
  210. /*
  211.  * SERIAL driver system settings.
  212.  */
  213. #define STM32_SERIAL_USE_USART1             FALSE
  214. #define STM32_SERIAL_USE_USART2             FALSE
  215. #define STM32_SERIAL_USE_USART3             FALSE
  216. #define STM32_SERIAL_USE_UART4              FALSE
  217. #define STM32_SERIAL_USE_UART5              FALSE
  218. #define STM32_SERIAL_USE_USART6             FALSE
  219. #define STM32_SERIAL_USE_LPUART1            FALSE
  220. #define STM32_SERIAL_USE_LPUART2            FALSE
  222. /*
  223.  * SIO driver system settings.
  224.  */
  225. #define STM32_SIO_USE_USART1                FALSE
  226. #define STM32_SIO_USE_USART2                FALSE
  227. #define STM32_SIO_USE_USART3                FALSE
  228. #define STM32_SIO_USE_UART4                 FALSE
  229. #define STM32_SIO_USE_UART5                 FALSE
  230. #define STM32_SIO_USE_USART6                FALSE
  231. #define STM32_SIO_USE_LPUART1               FALSE
  232. #define STM32_SIO_USE_LPUART2               FALSE
  234. /*
  235.  * SPI driver system settings.
  236.  */
  237. #define STM32_SPI_USE_SPI1                  FALSE
  238. #define STM32_SPI_USE_SPI2                  FALSE
  239. #define STM32_SPI_USE_SPI3                  FALSE
  240. #define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  241. #define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  242. #define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  243. #define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  244. #define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  245. #define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID_ANY
  246. #define STM32_SPI_SPI1_DMA_PRIORITY         1
  247. #define STM32_SPI_SPI2_DMA_PRIORITY         1
  248. #define STM32_SPI_SPI3_DMA_PRIORITY         1
  249. #define STM32_SPI_SPI1_IRQ_PRIORITY         2
  250. #define STM32_SPI_SPI2_IRQ_PRIORITY         2
  251. #define STM32_SPI_SPI3_IRQ_PRIORITY         2
  252. #define STM32_SPI_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
  254. /*
  255.  * ST driver system settings.
  256.  */
  257. #define STM32_ST_IRQ_PRIORITY               2
  258. #define STM32_ST_USE_TIMER                  2
  260. /*
  261.  * TRNG driver system settings.
  262.  * NOTE: STM32G0C1 only.
  263.  */
  264. #define STM32_TRNG_USE_RNG1                 FALSE
  266. /*
  267.  * UART driver system settings.
  268.  */
  269. #define STM32_UART_USE_USART1               FALSE
  270. #define STM32_UART_USE_USART2               FALSE
  271. #define STM32_UART_USE_USART3               FALSE
  272. #define STM32_UART_USE_UART4                FALSE
  273. #define STM32_UART_USE_UART5                FALSE
  274. #define STM32_UART_USE_USART6               FALSE
  275. #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  276. #define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  277. #define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  278. #define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  279. #define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  280. #define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  281. #define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  282. #define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  283. #define STM32_UART_UART5_RX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  284. #define STM32_UART_UART5_TX_DMA_STREAM      STM32_DMA_STREAM_ID_ANY
  285. #define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  286. #define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID_ANY
  287. #define STM32_UART_USART1_DMA_PRIORITY      0
  288. #define STM32_UART_USART2_DMA_PRIORITY      0
  289. #define STM32_UART_USART3_DMA_PRIORITY      0
  290. #define STM32_UART_UART4_DMA_PRIORITY       0
  291. #define STM32_UART_UART5_DMA_PRIORITY       0
  292. #define STM32_UART_USART6_DMA_PRIORITY      0
  293. #define STM32_UART_DMA_ERROR_HOOK(uartp)    osalSysHalt("DMA failure")
  295. /*
  296.  * USB driver system settings.
  297.  */
  298. #define STM32_USB_USE_USB1                  TRUE
  299. #define STM32_USB_USB1_LP_IRQ_PRIORITY      3
  300. #define STM32_USB_USE_ISOCHRONOUS           FALSE
  301. #define STM32_USB_USE_FAST_COPY             TRUE
  302. #define STM32_USB_HOST_WAKEUP_DURATION      2
  303. #define STM32_USB_48MHZ_DELTA               0
  305. /*
  306.  * WDG driver system settings.
  307.  */
  308. #define STM32_WDG_USE_IWDG                  FALSE
  310. #endif /* MCUCONF_H */