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qmk_firmware

custom branch of QMK firmware git clone https://anongit.hacktivis.me/git/qmk_firmware.git

config.h (2848B)

    

  1. /*
  2. Copyright 2021 KapCave
  4. This program is free software: you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation, either version 2 of the License, or
  7. (at your option) any later version.
  9. This program is distributed in the hope that it will be useful,
  10. but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12. GNU General Public License for more details.
  14. You should have received a copy of the GNU General Public License
  15. along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16. */
  17. #pragma once
  19. /* Only required if you add in a trackpoint hardware to the pcb */
  20. #ifdef PS2_DRIVER_USART
  21. #define PS2_CLOCK_PIN   D5
  22. #define PS2_DATA_PIN    D2
  24.     /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling
  25.      * edge */
  26.     /* set DDR of CLOCK as input to be slave */
  27.     #define PS2_USART_INIT() do {   \
  28.                     PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT);   \
  29.                     PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT);     \
  30.                     UCSR1C = ((1 << UMSEL10) |  \
  31.                                                   (3 << UPM10)   |  \
  32.                                                   (0 << USBS1)   |  \
  33.                                                   (3 << UCSZ10)  |  \
  34.                                                   (0 << UCPOL1));   \
  35.                     UCSR1A = 0;                 \
  36.                     UBRR1H = 0;                 \
  37.                     UBRR1L = 0;                 \
  38.                 } while (0)
  39.     #define PS2_USART_RX_INT_ON() do {  \
  40.                     UCSR1B = ((1 << RXCIE1) |       \
  41.                                                   (1 << RXEN1));        \
  42.                 } while (0)
  43.     #define PS2_USART_RX_POLL_ON() do { \
  44.                     UCSR1B = (1 << RXEN1);          \
  45.                 } while (0)
  46.     #define PS2_USART_OFF() do {    \
  47.                     UCSR1C = 0;                 \
  48.                     UCSR1B &= ~((1 << RXEN1) |  \
  49.                                                     (1 << TXEN1));  \
  50.                 } while (0)
  51.     #define PS2_USART_RX_READY      (UCSR1A & (1<<RXC1))
  52.     #define PS2_USART_RX_DATA       UDR1
  53.     #define PS2_USART_ERROR         (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
  54.     #define PS2_USART_RX_VECT       USART1_RX_vect
  55. #endif
  57. #ifdef PS2_DRIVER_INTERRUPT
  58. #define PS2_CLOCK_PIN   D2
  59. #define PS2_DATA_PIN    D5
  61.     #define PS2_INT_INIT()  do {    \
  62.         EICRA |= ((1<<ISC21) |      \
  63.                   (0<<ISC20));      \
  64.     } while (0)
  65.     #define PS2_INT_ON()  do {      \
  66.         EIMSK |= (1<<INT2);         \
  67.     } while (0)
  68.     #define PS2_INT_OFF() do {      \
  69.         EIMSK &= ~(1<<INT2);        \
  70.     } while (0)
  71.     #define PS2_INT_VECT   INT2_vect
  73. #endif