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qmk_firmware

custom branch of QMK firmware git clone https://anongit.hacktivis.me/git/qmk_firmware.git

config.h (2940B)

    

  1. /*
  2. Copyright 2012 Jun Wako <wakojun@gmail.com>
  3. Copyright 2016 Priyadi Iman Nurcahyo <priyadi@priyadi.net>
  5. This program is free software: you can redistribute it and/or modify
  6. it under the terms of the GNU General Public License as published by
  7. the Free Software Foundation, either version 2 of the License, or
  8. (at your option) any later version.
  10. This program is distributed in the hope that it will be useful,
  11. but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13. GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License
  16. along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17. */
  19. #pragma once
  21. /* matrix size */
  22. #define MATRIX_ROWS 17  // keycode bit: 3-0
  23. #define MATRIX_COLS 8   // keycode bit: 6-4
  26. /* legacy keymap support */
  27. #define USE_LEGACY_KEYMAP
  30. /* key combination for command */
  31. #define IS_COMMAND() ( \
  32.     get_mods() == (MOD_BIT(KC_LSFT) | MOD_BIT(KC_RSFT) | MOD_BIT(KC_RALT) | MOD_BIT(KC_RCTL)) \
  33. )
  36. /*
  37.  * PS/2 USART configuration for ATMega32U4
  38.  */
  39. #ifdef PS2_DRIVER_USART
  40. /* XCK for clock line */
  41. #define PS2_CLOCK_PIN   D5
  42. #define PS2_DATA_PIN    D2
  44. /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
  45. /* set DDR of CLOCK as input to be slave */
  46. #define PS2_USART_INIT() do {   \
  47.     PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT);   \
  48.     PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT);     \
  49.     UCSR1C = ((1 << UMSEL10) |  \
  50.               (3 << UPM10)   |  \
  51.               (0 << USBS1)   |  \
  52.               (3 << UCSZ10)  |  \
  53.               (0 << UCPOL1));   \
  54.     UCSR1A = 0;                 \
  55.     UBRR1H = 0;                 \
  56.     UBRR1L = 0;                 \
  57. } while (0)
  58. #define PS2_USART_RX_INT_ON() do {  \
  59.     UCSR1B = ((1 << RXCIE1) |       \
  60.               (1 << RXEN1));        \
  61. } while (0)
  62. #define PS2_USART_RX_POLL_ON() do { \
  63.     UCSR1B = (1 << RXEN1);          \
  64. } while (0)
  65. #define PS2_USART_OFF() do {    \
  66.     UCSR1C = 0;                 \
  67.     UCSR1B &= ~((1 << RXEN1) |  \
  68.                 (1 << TXEN1));  \
  69. } while (0)
  70. #define PS2_USART_RX_READY      (UCSR1A & (1<<RXC1))
  71. #define PS2_USART_RX_DATA       UDR1
  72. #define PS2_USART_ERROR         (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
  73. #define PS2_USART_RX_VECT       USART1_RX_vect
  74. #endif
  77. /*
  78.  * PS/2 Interrupt configuration
  79.  */
  80. #ifdef PS2_DRIVER_INTERRUPT
  81. /* uses INT1 for clock line(ATMega32U4) */
  82. #define PS2_CLOCK_PIN   D1
  83. #define PS2_DATA_PIN    D0
  85. #define PS2_INT_INIT()  do {    \
  86.     EICRA |= ((1<<ISC11) |      \
  87.               (0<<ISC10));      \
  88. } while (0)
  89. #define PS2_INT_ON()  do {      \
  90.     EIMSK |= (1<<INT1);         \
  91. } while (0)
  92. #define PS2_INT_OFF() do {      \
  93.     EIMSK &= ~(1<<INT1);        \
  94. } while (0)
  95. #define PS2_INT_VECT    INT1_vect
  96. #endif
  99. /*
  100.  * PS/2 Busywait configuration
  101.  */
  102. #ifdef PS2_DRIVER_BUSYWAIT
  103. #define PS2_CLOCK_PIN   D1
  104. #define PS2_DATA_PIN    D0
  105. #endif