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oasis-root

Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

as.1 (119064B)

    

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  132. .rm #[ #] #H #V #F C
  133. .\" ========================================================================
  134. .\"
  135. .IX Title "AS 1"
  136. .TH AS 1 "2022-08-05" "binutils-2.39" "GNU Development Tools"
  137. .\" For nroff, turn off justification.  Always turn off hyphenation; it makes
  138. .\" way too many mistakes in technical documents.
  139. .if n .ad l
  140. .nh
  141. .SH "NAME"
  142. AS \- the portable GNU assembler.
  143. .SH "SYNOPSIS"
  144. .IX Header "SYNOPSIS"
  145. as [\fB\-a\fR[\fBcdghlns\fR][=\fIfile\fR]] [\fB\-\-alternate\fR] [\fB\-D\fR]
  146.  [\fB\-\-compress\-debug\-sections\fR]  [\fB\-\-nocompress\-debug\-sections\fR]
  147.  [\fB\-\-debug\-prefix\-map\fR \fIold\fR=\fInew\fR]
  148.  [\fB\-\-defsym\fR \fIsym\fR=\fIval\fR] [\fB\-f\fR] [\fB\-g\fR] [\fB\-\-gstabs\fR]
  149.  [\fB\-\-gstabs+\fR] [\fB\-\-gdwarf\-<N>\fR] [\fB\-\-gdwarf\-sections\fR]
  150.  [\fB\-\-gdwarf\-cie\-version\fR=\fI\s-1VERSION\s0\fR]
  151.  [\fB\-\-help\fR] [\fB\-I\fR \fIdir\fR] [\fB\-J\fR]
  152.  [\fB\-K\fR] [\fB\-L\fR] [\fB\-\-listing\-lhs\-width\fR=\fI\s-1NUM\s0\fR]
  153.  [\fB\-\-listing\-lhs\-width2\fR=\fI\s-1NUM\s0\fR] [\fB\-\-listing\-rhs\-width\fR=\fI\s-1NUM\s0\fR]
  154.  [\fB\-\-listing\-cont\-lines\fR=\fI\s-1NUM\s0\fR] [\fB\-\-keep\-locals\fR]
  155.  [\fB\-\-no\-pad\-sections\fR]
  156.  [\fB\-o\fR \fIobjfile\fR] [\fB\-R\fR]
  157.  [\fB\-\-statistics\fR]
  158.  [\fB\-v\fR] [\fB\-version\fR] [\fB\-\-version\fR]
  159.  [\fB\-W\fR] [\fB\-\-warn\fR] [\fB\-\-fatal\-warnings\fR] [\fB\-w\fR] [\fB\-x\fR]
  160.  [\fB\-Z\fR] [\fB@\fR\fI\s-1FILE\s0\fR]
  161.  [\fB\-\-sectname\-subst\fR] [\fB\-\-size\-check=[error|warning]\fR]
  162.  [\fB\-\-elf\-stt\-common=[no|yes]\fR]
  163.  [\fB\-\-generate\-missing\-build\-notes=[no|yes]\fR]
  164.  [\fB\-\-multibyte\-handling=[allow|warn|warn\-sym\-only]\fR]
  165.  [\fB\-\-target\-help\fR] [\fItarget-options\fR]
  166.  [\fB\-\-\fR|\fIfiles\fR ...]
  167. .SH "TARGET"
  168. .IX Header "TARGET"
  169. \&\fITarget AArch64 options:\fR
  170.    [\fB\-EB\fR|\fB\-EL\fR]
  171.    [\fB\-mabi\fR=\fI\s-1ABI\s0\fR]
  172. .PP
  173. \&\fITarget Alpha options:\fR
  174.    [\fB\-m\fR\fIcpu\fR]
  175.    [\fB\-mdebug\fR | \fB\-no\-mdebug\fR]
  176.    [\fB\-replace\fR | \fB\-noreplace\fR]
  177.    [\fB\-relax\fR] [\fB\-g\fR] [\fB\-G\fR\fIsize\fR]
  178.    [\fB\-F\fR] [\fB\-32addr\fR]
  179. .PP
  180. \&\fITarget \s-1ARC\s0 options:\fR
  181.    [\fB\-mcpu=\fR\fIcpu\fR]
  182.    [\fB\-mA6\fR|\fB\-mARC600\fR|\fB\-mARC601\fR|\fB\-mA7\fR|\fB\-mARC700\fR|\fB\-mEM\fR|\fB\-mHS\fR]
  183.    [\fB\-mcode\-density\fR]
  184.    [\fB\-mrelax\fR]
  185.    [\fB\-EB\fR|\fB\-EL\fR]
  186. .PP
  187. \&\fITarget \s-1ARM\s0 options:\fR
  188.    [\fB\-mcpu\fR=\fIprocessor\fR[+\fIextension\fR...]]
  189.    [\fB\-march\fR=\fIarchitecture\fR[+\fIextension\fR...]]
  190.    [\fB\-mfpu\fR=\fIfloating-point-format\fR]
  191.    [\fB\-mfloat\-abi\fR=\fIabi\fR]
  192.    [\fB\-meabi\fR=\fIver\fR]
  193.    [\fB\-mthumb\fR]
  194.    [\fB\-EB\fR|\fB\-EL\fR]
  195.    [\fB\-mapcs\-32\fR|\fB\-mapcs\-26\fR|\fB\-mapcs\-float\fR|
  196.     \fB\-mapcs\-reentrant\fR]
  197.    [\fB\-mthumb\-interwork\fR] [\fB\-k\fR]
  198. .PP
  199. \&\fITarget Blackfin options:\fR
  200.    [\fB\-mcpu\fR=\fIprocessor\fR[\-\fIsirevision\fR]]
  201.    [\fB\-mfdpic\fR]
  202.    [\fB\-mno\-fdpic\fR]
  203.    [\fB\-mnopic\fR]
  204. .PP
  205. \&\fITarget \s-1BPF\s0 options:\fR
  206.    [\fB\-EL\fR] [\fB\-EB\fR]
  207. .PP
  208. \&\fITarget \s-1CRIS\s0 options:\fR
  209.    [\fB\-\-underscore\fR | \fB\-\-no\-underscore\fR]
  210.    [\fB\-\-pic\fR] [\fB\-N\fR]
  211.    [\fB\-\-emulation=criself\fR | \fB\-\-emulation=crisaout\fR]
  212.    [\fB\-\-march=v0_v10\fR | \fB\-\-march=v10\fR | \fB\-\-march=v32\fR | \fB\-\-march=common_v10_v32\fR]
  213. .PP
  214. \&\fITarget C\-SKY options:\fR
  215.    [\fB\-march=\fR\fIarch\fR] [\fB\-mcpu=\fR\fIcpu\fR]
  216.    [\fB\-EL\fR] [\fB\-mlittle\-endian\fR] [\fB\-EB\fR] [\fB\-mbig\-endian\fR]
  217.    [\fB\-fpic\fR] [\fB\-pic\fR]
  218.    [\fB\-mljump\fR] [\fB\-mno\-ljump\fR]
  219.    [\fB\-force2bsr\fR] [\fB\-mforce2bsr\fR] [\fB\-no\-force2bsr\fR] [\fB\-mno\-force2bsr\fR]
  220.    [\fB\-jsri2bsr\fR] [\fB\-mjsri2bsr\fR] [\fB\-no\-jsri2bsr\fR ] [\fB\-mno\-jsri2bsr\fR]
  221.    [\fB\-mnolrw\fR ] [\fB\-mno\-lrw\fR]
  222.    [\fB\-melrw\fR] [\fB\-mno\-elrw\fR]
  223.    [\fB\-mlaf\fR ] [\fB\-mliterals\-after\-func\fR]
  224.    [\fB\-mno\-laf\fR] [\fB\-mno\-literals\-after\-func\fR]
  225.    [\fB\-mlabr\fR] [\fB\-mliterals\-after\-br\fR]
  226.    [\fB\-mno\-labr\fR] [\fB\-mnoliterals\-after\-br\fR]
  227.    [\fB\-mistack\fR] [\fB\-mno\-istack\fR]
  228.    [\fB\-mhard\-float\fR] [\fB\-mmp\fR] [\fB\-mcp\fR] [\fB\-mcache\fR]
  229.    [\fB\-msecurity\fR] [\fB\-mtrust\fR]
  230.    [\fB\-mdsp\fR] [\fB\-medsp\fR] [\fB\-mvdsp\fR]
  231. .PP
  232. \&\fITarget D10V options:\fR
  233.    [\fB\-O\fR]
  234. .PP
  235. \&\fITarget D30V options:\fR
  236.    [\fB\-O\fR|\fB\-n\fR|\fB\-N\fR]
  237. .PP
  238. \&\fITarget \s-1EPIPHANY\s0 options:\fR
  239.    [\fB\-mepiphany\fR|\fB\-mepiphany16\fR]
  240. .PP
  241. \&\fITarget H8/300 options:\fR
  242.    [\-h\-tick\-hex]
  243. .PP
  244. \&\fITarget i386 options:\fR
  245.    [\fB\-\-32\fR|\fB\-\-x32\fR|\fB\-\-64\fR] [\fB\-n\fR]
  246.    [\fB\-march\fR=\fI\s-1CPU\s0\fR[+\fI\s-1EXTENSION\s0\fR...]] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR]
  247. .PP
  248. \&\fITarget \s-1IA\-64\s0 options:\fR
  249.    [\fB\-mconstant\-gp\fR|\fB\-mauto\-pic\fR]
  250.    [\fB\-milp32\fR|\fB\-milp64\fR|\fB\-mlp64\fR|\fB\-mp64\fR]
  251.    [\fB\-mle\fR|\fBmbe\fR]
  252.    [\fB\-mtune=itanium1\fR|\fB\-mtune=itanium2\fR]
  253.    [\fB\-munwind\-check=warning\fR|\fB\-munwind\-check=error\fR]
  254.    [\fB\-mhint.b=ok\fR|\fB\-mhint.b=warning\fR|\fB\-mhint.b=error\fR]
  255.    [\fB\-x\fR|\fB\-xexplicit\fR] [\fB\-xauto\fR] [\fB\-xdebug\fR]
  256. .PP
  257. \&\fITarget \s-1IP2K\s0 options:\fR
  258.    [\fB\-mip2022\fR|\fB\-mip2022ext\fR]
  259. .PP
  260. \&\fITarget M32C options:\fR
  261.    [\fB\-m32c\fR|\fB\-m16c\fR] [\-relax] [\-h\-tick\-hex]
  262. .PP
  263. \&\fITarget M32R options:\fR
  264.    [\fB\-\-m32rx\fR|\fB\-\-[no\-]warn\-explicit\-parallel\-conflicts\fR|
  265.    \fB\-\-W[n]p\fR]
  266. .PP
  267. \&\fITarget M680X0 options:\fR
  268.    [\fB\-l\fR] [\fB\-m68000\fR|\fB\-m68010\fR|\fB\-m68020\fR|...]
  269. .PP
  270. \&\fITarget M68HC11 options:\fR
  271.    [\fB\-m68hc11\fR|\fB\-m68hc12\fR|\fB\-m68hcs12\fR|\fB\-mm9s12x\fR|\fB\-mm9s12xg\fR]
  272.    [\fB\-mshort\fR|\fB\-mlong\fR]
  273.    [\fB\-mshort\-double\fR|\fB\-mlong\-double\fR]
  274.    [\fB\-\-force\-long\-branches\fR] [\fB\-\-short\-branches\fR]
  275.    [\fB\-\-strict\-direct\-mode\fR] [\fB\-\-print\-insn\-syntax\fR]
  276.    [\fB\-\-print\-opcodes\fR] [\fB\-\-generate\-example\fR]
  277. .PP
  278. \&\fITarget \s-1MCORE\s0 options:\fR
  279.    [\fB\-jsri2bsr\fR] [\fB\-sifilter\fR] [\fB\-relax\fR]
  280.    [\fB\-mcpu=[210|340]\fR]
  281. .PP
  282. \&\fITarget Meta options:\fR
  283.    [\fB\-mcpu=\fR\fIcpu\fR] [\fB\-mfpu=\fR\fIcpu\fR] [\fB\-mdsp=\fR\fIcpu\fR]
  284. \&\fITarget \s-1MICROBLAZE\s0 options:\fR
  285. .PP
  286. \&\fITarget \s-1MIPS\s0 options:\fR
  287.    [\fB\-nocpp\fR] [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR[\fIoptimization level\fR]]
  288.    [\fB\-g\fR[\fIdebug level\fR]] [\fB\-G\fR \fInum\fR] [\fB\-KPIC\fR] [\fB\-call_shared\fR]
  289.    [\fB\-non_shared\fR] [\fB\-xgot\fR [\fB\-mvxworks\-pic\fR]
  290.    [\fB\-mabi\fR=\fI\s-1ABI\s0\fR] [\fB\-32\fR] [\fB\-n32\fR] [\fB\-64\fR] [\fB\-mfp32\fR] [\fB\-mgp32\fR]
  291.    [\fB\-mfp64\fR] [\fB\-mgp64\fR] [\fB\-mfpxx\fR]
  292.    [\fB\-modd\-spreg\fR] [\fB\-mno\-odd\-spreg\fR]
  293.    [\fB\-march\fR=\fI\s-1CPU\s0\fR] [\fB\-mtune\fR=\fI\s-1CPU\s0\fR] [\fB\-mips1\fR] [\fB\-mips2\fR]
  294.    [\fB\-mips3\fR] [\fB\-mips4\fR] [\fB\-mips5\fR] [\fB\-mips32\fR] [\fB\-mips32r2\fR]
  295.    [\fB\-mips32r3\fR] [\fB\-mips32r5\fR] [\fB\-mips32r6\fR] [\fB\-mips64\fR] [\fB\-mips64r2\fR]
  296.    [\fB\-mips64r3\fR] [\fB\-mips64r5\fR] [\fB\-mips64r6\fR]
  297.    [\fB\-construct\-floats\fR] [\fB\-no\-construct\-floats\fR]
  298.    [\fB\-mignore\-branch\-isa\fR] [\fB\-mno\-ignore\-branch\-isa\fR]
  299.    [\fB\-mnan=\fR\fIencoding\fR]
  300.    [\fB\-trap\fR] [\fB\-no\-break\fR] [\fB\-break\fR] [\fB\-no\-trap\fR]
  301.    [\fB\-mips16\fR] [\fB\-no\-mips16\fR]
  302.    [\fB\-mmips16e2\fR] [\fB\-mno\-mips16e2\fR]
  303.    [\fB\-mmicromips\fR] [\fB\-mno\-micromips\fR]
  304.    [\fB\-msmartmips\fR] [\fB\-mno\-smartmips\fR]
  305.    [\fB\-mips3d\fR] [\fB\-no\-mips3d\fR]
  306.    [\fB\-mdmx\fR] [\fB\-no\-mdmx\fR]
  307.    [\fB\-mdsp\fR] [\fB\-mno\-dsp\fR]
  308.    [\fB\-mdspr2\fR] [\fB\-mno\-dspr2\fR]
  309.    [\fB\-mdspr3\fR] [\fB\-mno\-dspr3\fR]
  310.    [\fB\-mmsa\fR] [\fB\-mno\-msa\fR]
  311.    [\fB\-mxpa\fR] [\fB\-mno\-xpa\fR]
  312.    [\fB\-mmt\fR] [\fB\-mno\-mt\fR]
  313.    [\fB\-mmcu\fR] [\fB\-mno\-mcu\fR]
  314.    [\fB\-mcrc\fR] [\fB\-mno\-crc\fR]
  315.    [\fB\-mginv\fR] [\fB\-mno\-ginv\fR]
  316.    [\fB\-mloongson\-mmi\fR] [\fB\-mno\-loongson\-mmi\fR]
  317.    [\fB\-mloongson\-cam\fR] [\fB\-mno\-loongson\-cam\fR]
  318.    [\fB\-mloongson\-ext\fR] [\fB\-mno\-loongson\-ext\fR]
  319.    [\fB\-mloongson\-ext2\fR] [\fB\-mno\-loongson\-ext2\fR]
  320.    [\fB\-minsn32\fR] [\fB\-mno\-insn32\fR]
  321.    [\fB\-mfix7000\fR] [\fB\-mno\-fix7000\fR]
  322.    [\fB\-mfix\-rm7000\fR] [\fB\-mno\-fix\-rm7000\fR]
  323.    [\fB\-mfix\-vr4120\fR] [\fB\-mno\-fix\-vr4120\fR]
  324.    [\fB\-mfix\-vr4130\fR] [\fB\-mno\-fix\-vr4130\fR]
  325.    [\fB\-mfix\-r5900\fR] [\fB\-mno\-fix\-r5900\fR]
  326.    [\fB\-mdebug\fR] [\fB\-no\-mdebug\fR]
  327.    [\fB\-mpdr\fR] [\fB\-mno\-pdr\fR]
  328. .PP
  329. \&\fITarget \s-1MMIX\s0 options:\fR
  330.    [\fB\-\-fixed\-special\-register\-names\fR] [\fB\-\-globalize\-symbols\fR]
  331.    [\fB\-\-gnu\-syntax\fR] [\fB\-\-relax\fR] [\fB\-\-no\-predefined\-symbols\fR]
  332.    [\fB\-\-no\-expand\fR] [\fB\-\-no\-merge\-gregs\fR] [\fB\-x\fR]
  333.    [\fB\-\-linker\-allocated\-gregs\fR]
  334. .PP
  335. \&\fITarget Nios \s-1II\s0 options:\fR
  336.    [\fB\-relax\-all\fR] [\fB\-relax\-section\fR] [\fB\-no\-relax\fR]
  337.    [\fB\-EB\fR] [\fB\-EL\fR]
  338. .PP
  339. \&\fITarget \s-1NDS32\s0 options:\fR
  340.     [\fB\-EL\fR] [\fB\-EB\fR] [\fB\-O\fR] [\fB\-Os\fR] [\fB\-mcpu=\fR\fIcpu\fR]
  341.     [\fB\-misa=\fR\fIisa\fR] [\fB\-mabi=\fR\fIabi\fR] [\fB\-mall\-ext\fR]
  342.     [\fB\-m[no\-]16\-bit\fR]  [\fB\-m[no\-]perf\-ext\fR] [\fB\-m[no\-]perf2\-ext\fR]
  343.     [\fB\-m[no\-]string\-ext\fR] [\fB\-m[no\-]dsp\-ext\fR] [\fB\-m[no\-]mac\fR] [\fB\-m[no\-]div\fR]
  344.     [\fB\-m[no\-]audio\-isa\-ext\fR] [\fB\-m[no\-]fpu\-sp\-ext\fR] [\fB\-m[no\-]fpu\-dp\-ext\fR]
  345.     [\fB\-m[no\-]fpu\-fma\fR] [\fB\-mfpu\-freg=\fR\fI\s-1FREG\s0\fR] [\fB\-mreduced\-regs\fR]
  346.     [\fB\-mfull\-regs\fR] [\fB\-m[no\-]dx\-regs\fR] [\fB\-mpic\fR] [\fB\-mno\-relax\fR]
  347.     [\fB\-mb2bb\fR]
  348. .PP
  349. \&\fITarget \s-1PDP11\s0 options:\fR
  350.    [\fB\-mpic\fR|\fB\-mno\-pic\fR] [\fB\-mall\fR] [\fB\-mno\-extensions\fR]
  351.    [\fB\-m\fR\fIextension\fR|\fB\-mno\-\fR\fIextension\fR]
  352.    [\fB\-m\fR\fIcpu\fR] [\fB\-m\fR\fImachine\fR]
  353. .PP
  354. \&\fITarget picoJava options:\fR
  355.    [\fB\-mb\fR|\fB\-me\fR]
  356. .PP
  357. \&\fITarget PowerPC options:\fR
  358.    [\fB\-a32\fR|\fB\-a64\fR]
  359.    [\fB\-mpwrx\fR|\fB\-mpwr2\fR|\fB\-mpwr\fR|\fB\-m601\fR|\fB\-mppc\fR|\fB\-mppc32\fR|\fB\-m603\fR|\fB\-m604\fR|\fB\-m403\fR|\fB\-m405\fR|
  360.     \fB\-m440\fR|\fB\-m464\fR|\fB\-m476\fR|\fB\-m7400\fR|\fB\-m7410\fR|\fB\-m7450\fR|\fB\-m7455\fR|\fB\-m750cl\fR|\fB\-mgekko\fR|
  361.     \fB\-mbroadway\fR|\fB\-mppc64\fR|\fB\-m620\fR|\fB\-me500\fR|\fB\-e500x2\fR|\fB\-me500mc\fR|\fB\-me500mc64\fR|\fB\-me5500\fR|
  362.     \fB\-me6500\fR|\fB\-mppc64bridge\fR|\fB\-mbooke\fR|\fB\-mpower4\fR|\fB\-mpwr4\fR|\fB\-mpower5\fR|\fB\-mpwr5\fR|\fB\-mpwr5x\fR|
  363.     \fB\-mpower6\fR|\fB\-mpwr6\fR|\fB\-mpower7\fR|\fB\-mpwr7\fR|\fB\-mpower8\fR|\fB\-mpwr8\fR|\fB\-mpower9\fR|\fB\-mpwr9\fR\fB\-ma2\fR|
  364.     \fB\-mcell\fR|\fB\-mspe\fR|\fB\-mspe2\fR|\fB\-mtitan\fR|\fB\-me300\fR|\fB\-mcom\fR]
  365.    [\fB\-many\fR] [\fB\-maltivec\fR|\fB\-mvsx\fR|\fB\-mhtm\fR|\fB\-mvle\fR]
  366.    [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
  367.    [\fB\-mrelocatable\fR|\fB\-mrelocatable\-lib\fR|\fB\-K \s-1PIC\s0\fR] [\fB\-memb\fR]
  368.    [\fB\-mlittle\fR|\fB\-mlittle\-endian\fR|\fB\-le\fR|\fB\-mbig\fR|\fB\-mbig\-endian\fR|\fB\-be\fR]
  369.    [\fB\-msolaris\fR|\fB\-mno\-solaris\fR]
  370.    [\fB\-nops=\fR\fIcount\fR]
  371. .PP
  372. \&\fITarget \s-1PRU\s0 options:\fR
  373.    [\fB\-link\-relax\fR]
  374.    [\fB\-mnolink\-relax\fR]
  375.    [\fB\-mno\-warn\-regname\-label\fR]
  376. .PP
  377. \&\fITarget RISC-V options:\fR
  378.    [\fB\-fpic\fR|\fB\-fPIC\fR|\fB\-fno\-pic\fR]
  379.    [\fB\-march\fR=\fI\s-1ISA\s0\fR]
  380.    [\fB\-mabi\fR=\fI\s-1ABI\s0\fR]
  381.    [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR]
  382. .PP
  383. \&\fITarget \s-1RL78\s0 options:\fR
  384.    [\fB\-mg10\fR]
  385.    [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR]
  386. .PP
  387. \&\fITarget \s-1RX\s0 options:\fR
  388.    [\fB\-mlittle\-endian\fR|\fB\-mbig\-endian\fR]
  389.    [\fB\-m32bit\-doubles\fR|\fB\-m64bit\-doubles\fR]
  390.    [\fB\-muse\-conventional\-section\-names\fR]
  391.    [\fB\-msmall\-data\-limit\fR]
  392.    [\fB\-mpid\fR]
  393.    [\fB\-mrelax\fR]
  394.    [\fB\-mint\-register=\fR\fInumber\fR]
  395.    [\fB\-mgcc\-abi\fR|\fB\-mrx\-abi\fR]
  396. .PP
  397. \&\fITarget s390 options:\fR
  398.    [\fB\-m31\fR|\fB\-m64\fR] [\fB\-mesa\fR|\fB\-mzarch\fR] [\fB\-march\fR=\fI\s-1CPU\s0\fR]
  399.    [\fB\-mregnames\fR|\fB\-mno\-regnames\fR]
  400.    [\fB\-mwarn\-areg\-zero\fR]
  401. .PP
  402. \&\fITarget \s-1SCORE\s0 options:\fR
  403.    [\fB\-EB\fR][\fB\-EL\fR][\fB\-FIXDD\fR][\fB\-NWARN\fR]
  404.    [\fB\-SCORE5\fR][\fB\-SCORE5U\fR][\fB\-SCORE7\fR][\fB\-SCORE3\fR]
  405.    [\fB\-march=score7\fR][\fB\-march=score3\fR]
  406.    [\fB\-USE_R1\fR][\fB\-KPIC\fR][\fB\-O0\fR][\fB\-G\fR \fInum\fR][\fB\-V\fR]
  407. .PP
  408. \&\fITarget \s-1SPARC\s0 options:\fR
  409.    [\fB\-Av6\fR|\fB\-Av7\fR|\fB\-Av8\fR|\fB\-Aleon\fR|\fB\-Asparclet\fR|\fB\-Asparclite\fR
  410.     \fB\-Av8plus\fR|\fB\-Av8plusa\fR|\fB\-Av8plusb\fR|\fB\-Av8plusc\fR|\fB\-Av8plusd\fR
  411.     \fB\-Av8plusv\fR|\fB\-Av8plusm\fR|\fB\-Av9\fR|\fB\-Av9a\fR|\fB\-Av9b\fR|\fB\-Av9c\fR
  412.     \fB\-Av9d\fR|\fB\-Av9e\fR|\fB\-Av9v\fR|\fB\-Av9m\fR|\fB\-Asparc\fR|\fB\-Asparcvis\fR
  413.     \fB\-Asparcvis2\fR|\fB\-Asparcfmaf\fR|\fB\-Asparcima\fR|\fB\-Asparcvis3\fR
  414.     \fB\-Asparcvisr\fR|\fB\-Asparc5\fR]
  415.    [\fB\-xarch=v8plus\fR|\fB\-xarch=v8plusa\fR]|\fB\-xarch=v8plusb\fR|\fB\-xarch=v8plusc\fR
  416.     \fB\-xarch=v8plusd\fR|\fB\-xarch=v8plusv\fR|\fB\-xarch=v8plusm\fR|\fB\-xarch=v9\fR
  417.     \fB\-xarch=v9a\fR|\fB\-xarch=v9b\fR|\fB\-xarch=v9c\fR|\fB\-xarch=v9d\fR|\fB\-xarch=v9e\fR
  418.     \fB\-xarch=v9v\fR|\fB\-xarch=v9m\fR|\fB\-xarch=sparc\fR|\fB\-xarch=sparcvis\fR
  419.     \fB\-xarch=sparcvis2\fR|\fB\-xarch=sparcfmaf\fR|\fB\-xarch=sparcima\fR
  420.     \fB\-xarch=sparcvis3\fR|\fB\-xarch=sparcvisr\fR|\fB\-xarch=sparc5\fR
  421.     \fB\-bump\fR]
  422.    [\fB\-32\fR|\fB\-64\fR]
  423.    [\fB\-\-enforce\-aligned\-data\fR][\fB\-\-dcti\-couples\-detect\fR]
  424. .PP
  425. \&\fITarget \s-1TIC54X\s0 options:\fR
  426.  [\fB\-mcpu=54[123589]\fR|\fB\-mcpu=54[56]lp\fR] [\fB\-mfar\-mode\fR|\fB\-mf\fR]
  427.  [\fB\-merrors\-to\-file\fR \fI<filename>\fR|\fB\-me\fR \fI<filename>\fR]
  428. .PP
  429. \&\fITarget \s-1TIC6X\s0 options:\fR
  430.    [\fB\-march=\fR\fIarch\fR] [\fB\-mbig\-endian\fR|\fB\-mlittle\-endian\fR]
  431.    [\fB\-mdsbt\fR|\fB\-mno\-dsbt\fR] [\fB\-mpid=no\fR|\fB\-mpid=near\fR|\fB\-mpid=far\fR]
  432.    [\fB\-mpic\fR|\fB\-mno\-pic\fR]
  433. .PP
  434. \&\fITarget TILE-Gx options:\fR
  435.    [\fB\-m32\fR|\fB\-m64\fR][\fB\-EB\fR][\fB\-EL\fR]
  436. .PP
  437. \&\fITarget Visium options:\fR
  438.    [\fB\-mtune=\fR\fIarch\fR]
  439. .PP
  440. \&\fITarget Xtensa options:\fR
  441.  [\fB\-\-[no\-]text\-section\-literals\fR] [\fB\-\-[no\-]auto\-litpools\fR]
  442.  [\fB\-\-[no\-]absolute\-literals\fR]
  443.  [\fB\-\-[no\-]target\-align\fR] [\fB\-\-[no\-]longcalls\fR]
  444.  [\fB\-\-[no\-]transform\fR]
  445.  [\fB\-\-rename\-section\fR \fIoldname\fR=\fInewname\fR]
  446.  [\fB\-\-[no\-]trampolines\fR]
  447.  [\fB\-\-abi\-windowed\fR|\fB\-\-abi\-call0\fR]
  448. .PP
  449. \&\fITarget Z80 options:\fR
  450.   [\fB\-march=\fR\fI\s-1CPU\s0\fR\fI[\-EXT]\fR\fI[+EXT]\fR]
  451.   [\fB\-local\-prefix=\fR\fI\s-1PREFIX\s0\fR]
  452.   [\fB\-colonless\fR]
  453.   [\fB\-sdcc\fR]
  454.   [\fB\-fp\-s=\fR\fI\s-1FORMAT\s0\fR]
  455.   [\fB\-fp\-d=\fR\fI\s-1FORMAT\s0\fR]
  456. .SH "DESCRIPTION"
  457. .IX Header "DESCRIPTION"
  458. \&\s-1GNU\s0 \fBas\fR is really a family of assemblers.
  459. If you use (or have used) the \s-1GNU\s0 assembler on one architecture, you
  460. should find a fairly similar environment when you use it on another
  461. architecture.  Each version has much in common with the others,
  462. including object file formats, most assembler directives (often called
  463. \&\fIpseudo-ops\fR) and assembler syntax.
  464. .PP
  465. \&\fBas\fR is primarily intended to assemble the output of the
  466. \&\s-1GNU C\s0 compiler \f(CW\*(C`gcc\*(C'\fR for use by the linker
  467. \&\f(CW\*(C`ld\*(C'\fR.  Nevertheless, we've tried to make \fBas\fR
  468. assemble correctly everything that other assemblers for the same
  469. machine would assemble.
  470. Any exceptions are documented explicitly.
  471. This doesn't mean \fBas\fR always uses the same syntax as another
  472. assembler for the same architecture; for example, we know of several
  473. incompatible versions of 680x0 assembly language syntax.
  474. .PP
  475. Each time you run \fBas\fR it assembles exactly one source
  476. program.  The source program is made up of one or more files.
  477. (The standard input is also a file.)
  478. .PP
  479. You give \fBas\fR a command line that has zero or more input file
  480. names.  The input files are read (from left file name to right).  A
  481. command-line argument (in any position) that has no special meaning
  482. is taken to be an input file name.
  483. .PP
  484. If you give \fBas\fR no file names it attempts to read one input file
  485. from the \fBas\fR standard input, which is normally your terminal.  You
  486. may have to type \fBctl-D\fR to tell \fBas\fR there is no more program
  487. to assemble.
  488. .PP
  489. Use \fB\-\-\fR if you need to explicitly name the standard input file
  490. in your command line.
  491. .PP
  492. If the source is empty, \fBas\fR produces a small, empty object
  493. file.
  494. .PP
  495. \&\fBas\fR may write warnings and error messages to the standard error
  496. file (usually your terminal).  This should not happen when  a compiler
  497. runs \fBas\fR automatically.  Warnings report an assumption made so
  498. that \fBas\fR could keep assembling a flawed program; errors report a
  499. grave problem that stops the assembly.
  500. .PP
  501. If you are invoking \fBas\fR via the \s-1GNU C\s0 compiler,
  502. you can use the \fB\-Wa\fR option to pass arguments through to the assembler.
  503. The assembler arguments must be separated from each other (and the \fB\-Wa\fR)
  504. by commas.  For example:
  505. .PP
  506. .Vb 1
  507. \&        gcc \-c \-g \-O \-Wa,\-alh,\-L file.c
  508. .Ve
  509. .PP
  510. This passes two options to the assembler: \fB\-alh\fR (emit a listing to
  511. standard output with high-level and assembly source) and \fB\-L\fR (retain
  512. local symbols in the symbol table).
  513. .PP
  514. Usually you do not need to use this \fB\-Wa\fR mechanism, since many compiler
  515. command-line options are automatically passed to the assembler by the compiler.
  516. (You can call the \s-1GNU\s0 compiler driver with the \fB\-v\fR option to see
  517. precisely what options it passes to each compilation pass, including the
  518. assembler.)
  519. .SH "OPTIONS"
  520. .IX Header "OPTIONS"
  521. .IP "\fB@\fR\fIfile\fR" 4
  522. .IX Item "@file"
  523. Read command-line options from \fIfile\fR.  The options read are
  524. inserted in place of the original @\fIfile\fR option.  If \fIfile\fR
  525. does not exist, or cannot be read, then the option will be treated
  526. literally, and not removed.
  527. .Sp
  528. Options in \fIfile\fR are separated by whitespace.  A whitespace
  529. character may be included in an option by surrounding the entire
  530. option in either single or double quotes.  Any character (including a
  531. backslash) may be included by prefixing the character to be included
  532. with a backslash.  The \fIfile\fR may itself contain additional
  533. @\fIfile\fR options; any such options will be processed recursively.
  534. .IP "\fB\-a[cdghlmns]\fR" 4
  535. .IX Item "-a[cdghlmns]"
  536. Turn on listings, in any of a variety of ways:
  537. .RS 4
  538. .IP "\fB\-ac\fR" 4
  539. .IX Item "-ac"
  540. omit false conditionals
  541. .IP "\fB\-ad\fR" 4
  542. .IX Item "-ad"
  543. omit debugging directives
  544. .IP "\fB\-ag\fR" 4
  545. .IX Item "-ag"
  546. include general information, like as version and options passed
  547. .IP "\fB\-ah\fR" 4
  548. .IX Item "-ah"
  549. include high-level source
  550. .IP "\fB\-al\fR" 4
  551. .IX Item "-al"
  552. include assembly
  553. .IP "\fB\-am\fR" 4
  554. .IX Item "-am"
  555. include macro expansions
  556. .IP "\fB\-an\fR" 4
  557. .IX Item "-an"
  558. omit forms processing
  559. .IP "\fB\-as\fR" 4
  560. .IX Item "-as"
  561. include symbols
  562. .IP "\fB=file\fR" 4
  563. .IX Item "=file"
  564. set the name of the listing file
  565. .RE
  566. .RS 4
  567. .Sp
  568. You may combine these options; for example, use \fB\-aln\fR for assembly
  569. listing without forms processing.  The \fB=file\fR option, if used, must be
  570. the last one.  By itself, \fB\-a\fR defaults to \fB\-ahls\fR.
  571. .RE
  572. .IP "\fB\-\-alternate\fR" 4
  573. .IX Item "--alternate"
  574. Begin in alternate macro mode.
  575. .IP "\fB\-\-compress\-debug\-sections\fR" 4
  576. .IX Item "--compress-debug-sections"
  577. Compress \s-1DWARF\s0 debug sections using zlib with \s-1SHF_COMPRESSED\s0 from the
  578. \&\s-1ELF ABI.\s0  The resulting object file may not be compatible with older
  579. linkers and object file utilities.  Note if compression would make a
  580. given section \fIlarger\fR then it is not compressed.
  581. .IP "\fB\-\-compress\-debug\-sections=none\fR" 4
  582. .IX Item "--compress-debug-sections=none"
  583. .PD 0
  584. .IP "\fB\-\-compress\-debug\-sections=zlib\fR" 4
  585. .IX Item "--compress-debug-sections=zlib"
  586. .IP "\fB\-\-compress\-debug\-sections=zlib\-gnu\fR" 4
  587. .IX Item "--compress-debug-sections=zlib-gnu"
  588. .IP "\fB\-\-compress\-debug\-sections=zlib\-gabi\fR" 4
  589. .IX Item "--compress-debug-sections=zlib-gabi"
  590. .PD
  591. These options control how \s-1DWARF\s0 debug sections are compressed.
  592. \&\fB\-\-compress\-debug\-sections=none\fR is equivalent to
  593. \&\fB\-\-nocompress\-debug\-sections\fR.
  594. \&\fB\-\-compress\-debug\-sections=zlib\fR and
  595. \&\fB\-\-compress\-debug\-sections=zlib\-gabi\fR are equivalent to
  596. \&\fB\-\-compress\-debug\-sections\fR.
  597. \&\fB\-\-compress\-debug\-sections=zlib\-gnu\fR compresses \s-1DWARF\s0 debug
  598. sections using zlib.  The debug sections are renamed to begin with
  599. \&\fB.zdebug\fR.  Note if compression would make a given section
  600. \&\fIlarger\fR then it is not compressed nor renamed.
  601. .IP "\fB\-\-nocompress\-debug\-sections\fR" 4
  602. .IX Item "--nocompress-debug-sections"
  603. Do not compress \s-1DWARF\s0 debug sections.  This is usually the default for all
  604. targets except the x86/x86_64, but a configure time option can be used to
  605. override this.
  606. .IP "\fB\-D\fR" 4
  607. .IX Item "-D"
  608. Ignored.  This option is accepted for script compatibility with calls to
  609. other assemblers.
  610. .IP "\fB\-\-debug\-prefix\-map\fR \fIold\fR\fB=\fR\fInew\fR" 4
  611. .IX Item "--debug-prefix-map old=new"
  612. When assembling files in directory \fI\fIold\fI\fR, record debugging
  613. information describing them as in \fI\fInew\fI\fR instead.
  614. .IP "\fB\-\-defsym\fR \fIsym\fR\fB=\fR\fIvalue\fR" 4
  615. .IX Item "--defsym sym=value"
  616. Define the symbol \fIsym\fR to be \fIvalue\fR before assembling the input file.
  617. \&\fIvalue\fR must be an integer constant.  As in C, a leading \fB0x\fR
  618. indicates a hexadecimal value, and a leading \fB0\fR indicates an octal
  619. value.  The value of the symbol can be overridden inside a source file via the
  620. use of a \f(CW\*(C`.set\*(C'\fR pseudo-op.
  621. .IP "\fB\-f\fR" 4
  622. .IX Item "-f"
  623. \&\*(L"fast\*(R"\-\-\-skip whitespace and comment preprocessing (assume source is
  624. compiler output).
  625. .IP "\fB\-g\fR" 4
  626. .IX Item "-g"
  627. .PD 0
  628. .IP "\fB\-\-gen\-debug\fR" 4
  629. .IX Item "--gen-debug"
  630. .PD
  631. Generate debugging information for each assembler source line using whichever
  632. debug format is preferred by the target.  This currently means either \s-1STABS,
  633. ECOFF\s0 or \s-1DWARF2.\s0  When the debug format is \s-1DWARF\s0 then a \f(CW\*(C`.debug_info\*(C'\fR and
  634. \&\f(CW\*(C`.debug_line\*(C'\fR section is only emitted when the assembly file doesn't
  635. generate one itself.
  636. .IP "\fB\-\-gstabs\fR" 4
  637. .IX Item "--gstabs"
  638. Generate stabs debugging information for each assembler line.  This
  639. may help debugging assembler code, if the debugger can handle it.
  640. .IP "\fB\-\-gstabs+\fR" 4
  641. .IX Item "--gstabs+"
  642. Generate stabs debugging information for each assembler line, with \s-1GNU\s0
  643. extensions that probably only gdb can handle, and that could make other
  644. debuggers crash or refuse to read your program.  This
  645. may help debugging assembler code.  Currently the only \s-1GNU\s0 extension is
  646. the location of the current working directory at assembling time.
  647. .IP "\fB\-\-gdwarf\-2\fR" 4
  648. .IX Item "--gdwarf-2"
  649. Generate \s-1DWARF2\s0 debugging information for each assembler line.  This
  650. may help debugging assembler code, if the debugger can handle it.  Note\-\-\-this
  651. option is only supported by some targets, not all of them.
  652. .IP "\fB\-\-gdwarf\-3\fR" 4
  653. .IX Item "--gdwarf-3"
  654. This option is the same as the \fB\-\-gdwarf\-2\fR option, except that it
  655. allows for the possibility of the generation of extra debug information as per
  656. version 3 of the \s-1DWARF\s0 specification.  Note \- enabling this option does not
  657. guarantee the generation of any extra information, the choice to do so is on a
  658. per target basis.
  659. .IP "\fB\-\-gdwarf\-4\fR" 4
  660. .IX Item "--gdwarf-4"
  661. This option is the same as the \fB\-\-gdwarf\-2\fR option, except that it
  662. allows for the possibility of the generation of extra debug information as per
  663. version 4 of the \s-1DWARF\s0 specification.  Note \- enabling this option does not
  664. guarantee the generation of any extra information, the choice to do so is on a
  665. per target basis.
  666. .IP "\fB\-\-gdwarf\-5\fR" 4
  667. .IX Item "--gdwarf-5"
  668. This option is the same as the \fB\-\-gdwarf\-2\fR option, except that it
  669. allows for the possibility of the generation of extra debug information as per
  670. version 5 of the \s-1DWARF\s0 specification.  Note \- enabling this option does not
  671. guarantee the generation of any extra information, the choice to do so is on a
  672. per target basis.
  673. .IP "\fB\-\-gdwarf\-sections\fR" 4
  674. .IX Item "--gdwarf-sections"
  675. Instead of creating a .debug_line section, create a series of
  676. \&.debug_line.\fIfoo\fR sections where \fIfoo\fR is the name of the
  677. corresponding code section.  For example a code section called \fI.text.func\fR
  678. will have its dwarf line number information placed into a section called
  679. \&\fI.debug_line.text.func\fR.  If the code section is just called \fI.text\fR
  680. then debug line section will still be called just \fI.debug_line\fR without any
  681. suffix.
  682. .IP "\fB\-\-gdwarf\-cie\-version=\fR\fIversion\fR" 4
  683. .IX Item "--gdwarf-cie-version=version"
  684. Control which version of \s-1DWARF\s0 Common Information Entries (CIEs) are produced.
  685. When this flag is not specificed the default is version 1, though some targets
  686. can modify this default.  Other possible values for \fIversion\fR are 3 or 4.
  687. .IP "\fB\-\-size\-check=error\fR" 4
  688. .IX Item "--size-check=error"
  689. .PD 0
  690. .IP "\fB\-\-size\-check=warning\fR" 4
  691. .IX Item "--size-check=warning"
  692. .PD
  693. Issue an error or warning for invalid \s-1ELF\s0 .size directive.
  694. .IP "\fB\-\-elf\-stt\-common=no\fR" 4
  695. .IX Item "--elf-stt-common=no"
  696. .PD 0
  697. .IP "\fB\-\-elf\-stt\-common=yes\fR" 4
  698. .IX Item "--elf-stt-common=yes"
  699. .PD
  700. These options control whether the \s-1ELF\s0 assembler should generate common
  701. symbols with the \f(CW\*(C`STT_COMMON\*(C'\fR type.  The default can be controlled
  702. by a configure option \fB\-\-enable\-elf\-stt\-common\fR.
  703. .IP "\fB\-\-generate\-missing\-build\-notes=yes\fR" 4
  704. .IX Item "--generate-missing-build-notes=yes"
  705. .PD 0
  706. .IP "\fB\-\-generate\-missing\-build\-notes=no\fR" 4
  707. .IX Item "--generate-missing-build-notes=no"
  708. .PD
  709. These options control whether the \s-1ELF\s0 assembler should generate \s-1GNU\s0 Build
  710. attribute notes if none are present in the input sources.
  711. The default can be controlled by the \fB\-\-enable\-generate\-build\-notes\fR
  712. configure option.
  713. .IP "\fB\-\-help\fR" 4
  714. .IX Item "--help"
  715. Print a summary of the command-line options and exit.
  716. .IP "\fB\-\-target\-help\fR" 4
  717. .IX Item "--target-help"
  718. Print a summary of all target specific options and exit.
  719. .IP "\fB\-I\fR \fIdir\fR" 4
  720. .IX Item "-I dir"
  721. Add directory \fIdir\fR to the search list for \f(CW\*(C`.include\*(C'\fR directives.
  722. .IP "\fB\-J\fR" 4
  723. .IX Item "-J"
  724. Don't warn about signed overflow.
  725. .IP "\fB\-K\fR" 4
  726. .IX Item "-K"
  727. Issue warnings when difference tables altered for long displacements.
  728. .IP "\fB\-L\fR" 4
  729. .IX Item "-L"
  730. .PD 0
  731. .IP "\fB\-\-keep\-locals\fR" 4
  732. .IX Item "--keep-locals"
  733. .PD
  734. Keep (in the symbol table) local symbols.  These symbols start with
  735. system-specific local label prefixes, typically \fB.L\fR for \s-1ELF\s0 systems
  736. or \fBL\fR for traditional a.out systems.
  737. .IP "\fB\-\-listing\-lhs\-width=\fR\fInumber\fR" 4
  738. .IX Item "--listing-lhs-width=number"
  739. Set the maximum width, in words, of the output data column for an assembler
  740. listing to \fInumber\fR.
  741. .IP "\fB\-\-listing\-lhs\-width2=\fR\fInumber\fR" 4
  742. .IX Item "--listing-lhs-width2=number"
  743. Set the maximum width, in words, of the output data column for continuation
  744. lines in an assembler listing to \fInumber\fR.
  745. .IP "\fB\-\-listing\-rhs\-width=\fR\fInumber\fR" 4
  746. .IX Item "--listing-rhs-width=number"
  747. Set the maximum width of an input source line, as displayed in a listing, to
  748. \&\fInumber\fR bytes.
  749. .IP "\fB\-\-listing\-cont\-lines=\fR\fInumber\fR" 4
  750. .IX Item "--listing-cont-lines=number"
  751. Set the maximum number of lines printed in a listing for a single line of input
  752. to \fInumber\fR + 1.
  753. .IP "\fB\-\-multibyte\-handling=allow\fR" 4
  754. .IX Item "--multibyte-handling=allow"
  755. .PD 0
  756. .IP "\fB\-\-multibyte\-handling=warn\fR" 4
  757. .IX Item "--multibyte-handling=warn"
  758. .IP "\fB\-\-multibyte\-handling=warn\-sym\-only\fR" 4
  759. .IX Item "--multibyte-handling=warn-sym-only"
  760. .PD
  761. Controls how the assembler handles multibyte characters in the input.  The
  762. default (which can be restored by using the \fBallow\fR argument) is to
  763. allow such characters without complaint.  Using the \fBwarn\fR argument will
  764. make the assembler generate a warning message whenever any multibyte character
  765. is encountered.  Using the \fBwarn-sym-only\fR argument will only cause a
  766. warning to be generated when a symbol is defined with a name that contains
  767. multibyte characters.  (References to undefined symbols will not generate a
  768. warning).
  769. .IP "\fB\-\-no\-pad\-sections\fR" 4
  770. .IX Item "--no-pad-sections"
  771. Stop the assembler for padding the ends of output sections to the alignment
  772. of that section.  The default is to pad the sections, but this can waste space
  773. which might be needed on targets which have tight memory constraints.
  774. .IP "\fB\-o\fR \fIobjfile\fR" 4
  775. .IX Item "-o objfile"
  776. Name the object-file output from \fBas\fR \fIobjfile\fR.
  777. .IP "\fB\-R\fR" 4
  778. .IX Item "-R"
  779. Fold the data section into the text section.
  780. .IP "\fB\-\-sectname\-subst\fR" 4
  781. .IX Item "--sectname-subst"
  782. Honor substitution sequences in section names.
  783. .IP "\fB\-\-statistics\fR" 4
  784. .IX Item "--statistics"
  785. Print the maximum space (in bytes) and total time (in seconds) used by
  786. assembly.
  787. .IP "\fB\-\-strip\-local\-absolute\fR" 4
  788. .IX Item "--strip-local-absolute"
  789. Remove local absolute symbols from the outgoing symbol table.
  790. .IP "\fB\-v\fR" 4
  791. .IX Item "-v"
  792. .PD 0
  793. .IP "\fB\-version\fR" 4
  794. .IX Item "-version"
  795. .PD
  796. Print the \fBas\fR version.
  797. .IP "\fB\-\-version\fR" 4
  798. .IX Item "--version"
  799. Print the \fBas\fR version and exit.
  800. .IP "\fB\-W\fR" 4
  801. .IX Item "-W"
  802. .PD 0
  803. .IP "\fB\-\-no\-warn\fR" 4
  804. .IX Item "--no-warn"
  805. .PD
  806. Suppress warning messages.
  807. .IP "\fB\-\-fatal\-warnings\fR" 4
  808. .IX Item "--fatal-warnings"
  809. Treat warnings as errors.
  810. .IP "\fB\-\-warn\fR" 4
  811. .IX Item "--warn"
  812. Don't suppress warning messages or treat them as errors.
  813. .IP "\fB\-w\fR" 4
  814. .IX Item "-w"
  815. Ignored.
  816. .IP "\fB\-x\fR" 4
  817. .IX Item "-x"
  818. Ignored.
  819. .IP "\fB\-Z\fR" 4
  820. .IX Item "-Z"
  821. Generate an object file even after errors.
  822. .IP "\fB\-\- |\fR \fIfiles\fR \fB...\fR" 4
  823. .IX Item "-- | files ..."
  824. Standard input, or source files to assemble.
  825. .PP
  826. The following options are available when as is configured for the
  827. 64\-bit mode of the \s-1ARM\s0 Architecture (AArch64).
  828. .IP "\fB\-EB\fR" 4
  829. .IX Item "-EB"
  830. This option specifies that the output generated by the assembler should
  831. be marked as being encoded for a big-endian processor.
  832. .IP "\fB\-EL\fR" 4
  833. .IX Item "-EL"
  834. This option specifies that the output generated by the assembler should
  835. be marked as being encoded for a little-endian processor.
  836. .IP "\fB\-mabi=\fR\fIabi\fR" 4
  837. .IX Item "-mabi=abi"
  838. Specify which \s-1ABI\s0 the source code uses.  The recognized arguments
  839. are: \f(CW\*(C`ilp32\*(C'\fR and \f(CW\*(C`lp64\*(C'\fR, which decides the generated object
  840. file in \s-1ELF32\s0 and \s-1ELF64\s0 format respectively.  The default is \f(CW\*(C`lp64\*(C'\fR.
  841. .IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
  842. .IX Item "-mcpu=processor[+extension...]"
  843. This option specifies the target processor.  The assembler will issue an error
  844. message if an attempt is made to assemble an instruction which will not execute
  845. on the target processor.  The following processor names are recognized:
  846. \&\f(CW\*(C`cortex\-a34\*(C'\fR,
  847. \&\f(CW\*(C`cortex\-a35\*(C'\fR,
  848. \&\f(CW\*(C`cortex\-a53\*(C'\fR,
  849. \&\f(CW\*(C`cortex\-a55\*(C'\fR,
  850. \&\f(CW\*(C`cortex\-a57\*(C'\fR,
  851. \&\f(CW\*(C`cortex\-a65\*(C'\fR,
  852. \&\f(CW\*(C`cortex\-a65ae\*(C'\fR,
  853. \&\f(CW\*(C`cortex\-a72\*(C'\fR,
  854. \&\f(CW\*(C`cortex\-a73\*(C'\fR,
  855. \&\f(CW\*(C`cortex\-a75\*(C'\fR,
  856. \&\f(CW\*(C`cortex\-a76\*(C'\fR,
  857. \&\f(CW\*(C`cortex\-a76ae\*(C'\fR,
  858. \&\f(CW\*(C`cortex\-a77\*(C'\fR,
  859. \&\f(CW\*(C`cortex\-a78\*(C'\fR,
  860. \&\f(CW\*(C`cortex\-a78ae\*(C'\fR,
  861. \&\f(CW\*(C`cortex\-a78c\*(C'\fR,
  862. \&\f(CW\*(C`cortex\-a510\*(C'\fR,
  863. \&\f(CW\*(C`cortex\-a710\*(C'\fR,
  864. \&\f(CW\*(C`ares\*(C'\fR,
  865. \&\f(CW\*(C`exynos\-m1\*(C'\fR,
  866. \&\f(CW\*(C`falkor\*(C'\fR,
  867. \&\f(CW\*(C`neoverse\-n1\*(C'\fR,
  868. \&\f(CW\*(C`neoverse\-n2\*(C'\fR,
  869. \&\f(CW\*(C`neoverse\-e1\*(C'\fR,
  870. \&\f(CW\*(C`neoverse\-v1\*(C'\fR,
  871. \&\f(CW\*(C`qdf24xx\*(C'\fR,
  872. \&\f(CW\*(C`saphira\*(C'\fR,
  873. \&\f(CW\*(C`thunderx\*(C'\fR,
  874. \&\f(CW\*(C`vulcan\*(C'\fR,
  875. \&\f(CW\*(C`xgene1\*(C'\fR
  876. \&\f(CW\*(C`xgene2\*(C'\fR,
  877. \&\f(CW\*(C`cortex\-r82\*(C'\fR,
  878. \&\f(CW\*(C`cortex\-x1\*(C'\fR,
  879. and
  880. \&\f(CW\*(C`cortex\-x2\*(C'\fR.
  881. The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
  882. instructions valid for any supported processor, including all optional
  883. extensions.
  884. .Sp
  885. In addition to the basic instruction set, the assembler can be told to
  886. accept, or restrict, various extension mnemonics that extend the
  887. processor.
  888. .Sp
  889. If some implementations of a particular processor can have an
  890. extension, then then those extensions are automatically enabled.
  891. Consequently, you will not normally have to specify any additional
  892. extensions.
  893. .IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
  894. .IX Item "-march=architecture[+extension...]"
  895. This option specifies the target architecture.  The assembler will
  896. issue an error message if an attempt is made to assemble an
  897. instruction which will not execute on the target architecture.  The
  898. following architecture names are recognized: \f(CW\*(C`armv8\-a\*(C'\fR,
  899. \&\f(CW\*(C`armv8.1\-a\*(C'\fR, \f(CW\*(C`armv8.2\-a\*(C'\fR, \f(CW\*(C`armv8.3\-a\*(C'\fR, \f(CW\*(C`armv8.4\-a\*(C'\fR
  900. \&\f(CW\*(C`armv8.5\-a\*(C'\fR, \f(CW\*(C`armv8.6\-a\*(C'\fR, \f(CW\*(C`armv8.7\-a\*(C'\fR, \f(CW\*(C`armv8.8\-a\*(C'\fR,
  901. \&\f(CW\*(C`armv8\-r\*(C'\fR, \f(CW\*(C`armv9\-a\*(C'\fR, \f(CW\*(C`armv9.1\-a\*(C'\fR, \f(CW\*(C`armv9.2\-a\*(C'\fR,
  902. and \f(CW\*(C`armv9.3\-a\*(C'\fR.
  903. .Sp
  904. If both \fB\-mcpu\fR and \fB\-march\fR are specified, the
  905. assembler will use the setting for \fB\-mcpu\fR.  If neither are
  906. specified, the assembler will default to \fB\-mcpu=all\fR.
  907. .Sp
  908. The architecture option can be extended with the same instruction set
  909. extension options as the \fB\-mcpu\fR option.  Unlike
  910. \&\fB\-mcpu\fR, extensions are not always enabled by default,
  911. .IP "\fB\-mverbose\-error\fR" 4
  912. .IX Item "-mverbose-error"
  913. This option enables verbose error messages for AArch64 gas.  This option
  914. is enabled by default.
  915. .IP "\fB\-mno\-verbose\-error\fR" 4
  916. .IX Item "-mno-verbose-error"
  917. This option disables verbose error messages in AArch64 gas.
  918. .PP
  919. The following options are available when as is configured for an Alpha
  920. processor.
  921. .IP "\fB\-m\fR\fIcpu\fR" 4
  922. .IX Item "-mcpu"
  923. This option specifies the target processor.  If an attempt is made to
  924. assemble an instruction which will not execute on the target processor,
  925. the assembler may either expand the instruction as a macro or issue an
  926. error message.  This option is equivalent to the \f(CW\*(C`.arch\*(C'\fR directive.
  927. .Sp
  928. The following processor names are recognized:
  929. \&\f(CW21064\fR,
  930. \&\f(CW\*(C`21064a\*(C'\fR,
  931. \&\f(CW21066\fR,
  932. \&\f(CW21068\fR,
  933. \&\f(CW21164\fR,
  934. \&\f(CW\*(C`21164a\*(C'\fR,
  935. \&\f(CW\*(C`21164pc\*(C'\fR,
  936. \&\f(CW21264\fR,
  937. \&\f(CW\*(C`21264a\*(C'\fR,
  938. \&\f(CW\*(C`21264b\*(C'\fR,
  939. \&\f(CW\*(C`ev4\*(C'\fR,
  940. \&\f(CW\*(C`ev5\*(C'\fR,
  941. \&\f(CW\*(C`lca45\*(C'\fR,
  942. \&\f(CW\*(C`ev5\*(C'\fR,
  943. \&\f(CW\*(C`ev56\*(C'\fR,
  944. \&\f(CW\*(C`pca56\*(C'\fR,
  945. \&\f(CW\*(C`ev6\*(C'\fR,
  946. \&\f(CW\*(C`ev67\*(C'\fR,
  947. \&\f(CW\*(C`ev68\*(C'\fR.
  948. The special name \f(CW\*(C`all\*(C'\fR may be used to allow the assembler to accept
  949. instructions valid for any Alpha processor.
  950. .Sp
  951. In order to support existing practice in \s-1OSF/1\s0 with respect to \f(CW\*(C`.arch\*(C'\fR,
  952. and existing practice within \fB\s-1MILO\s0\fR (the Linux \s-1ARC\s0 bootloader), the
  953. numbered processor names (e.g. 21064) enable the processor-specific PALcode
  954. instructions, while the \*(L"electro-vlasic\*(R" names (e.g. \f(CW\*(C`ev4\*(C'\fR) do not.
  955. .IP "\fB\-mdebug\fR" 4
  956. .IX Item "-mdebug"
  957. .PD 0
  958. .IP "\fB\-no\-mdebug\fR" 4
  959. .IX Item "-no-mdebug"
  960. .PD
  961. Enables or disables the generation of \f(CW\*(C`.mdebug\*(C'\fR encapsulation for
  962. stabs directives and procedure descriptors.  The default is to automatically
  963. enable \f(CW\*(C`.mdebug\*(C'\fR when the first stabs directive is seen.
  964. .IP "\fB\-relax\fR" 4
  965. .IX Item "-relax"
  966. This option forces all relocations to be put into the object file, instead
  967. of saving space and resolving some relocations at assembly time.  Note that
  968. this option does not propagate all symbol arithmetic into the object file,
  969. because not all symbol arithmetic can be represented.  However, the option
  970. can still be useful in specific applications.
  971. .IP "\fB\-replace\fR" 4
  972. .IX Item "-replace"
  973. .PD 0
  974. .IP "\fB\-noreplace\fR" 4
  975. .IX Item "-noreplace"
  976. .PD
  977. Enables or disables the optimization of procedure calls, both at assemblage
  978. and at link time.  These options are only available for \s-1VMS\s0 targets and
  979. \&\f(CW\*(C`\-replace\*(C'\fR is the default.  See section 1.4.1 of the OpenVMS Linker
  980. Utility Manual.
  981. .IP "\fB\-g\fR" 4
  982. .IX Item "-g"
  983. This option is used when the compiler generates debug information.  When
  984. \&\fBgcc\fR is using \fBmips-tfile\fR to generate debug
  985. information for \s-1ECOFF,\s0 local labels must be passed through to the object
  986. file.  Otherwise this option has no effect.
  987. .IP "\fB\-G\fR\fIsize\fR" 4
  988. .IX Item "-Gsize"
  989. A local common symbol larger than \fIsize\fR is placed in \f(CW\*(C`.bss\*(C'\fR,
  990. while smaller symbols are placed in \f(CW\*(C`.sbss\*(C'\fR.
  991. .IP "\fB\-F\fR" 4
  992. .IX Item "-F"
  993. .PD 0
  994. .IP "\fB\-32addr\fR" 4
  995. .IX Item "-32addr"
  996. .PD
  997. These options are ignored for backward compatibility.
  998. .PP
  999. The following options are available when as is configured for an \s-1ARC\s0
  1000. processor.
  1001. .IP "\fB\-mcpu=\fR\fIcpu\fR" 4
  1002. .IX Item "-mcpu=cpu"
  1003. This option selects the core processor variant.
  1004. .IP "\fB\-EB | \-EL\fR" 4
  1005. .IX Item "-EB | -EL"
  1006. Select either big-endian (\-EB) or little-endian (\-EL) output.
  1007. .IP "\fB\-mcode\-density\fR" 4
  1008. .IX Item "-mcode-density"
  1009. Enable Code Density extension instructions.
  1010. .PP
  1011. The following options are available when as is configured for the \s-1ARM\s0
  1012. processor family.
  1013. .IP "\fB\-mcpu=\fR\fIprocessor\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
  1014. .IX Item "-mcpu=processor[+extension...]"
  1015. Specify which \s-1ARM\s0 processor variant is the target.
  1016. .IP "\fB\-march=\fR\fIarchitecture\fR\fB[+\fR\fIextension\fR\fB...]\fR" 4
  1017. .IX Item "-march=architecture[+extension...]"
  1018. Specify which \s-1ARM\s0 architecture variant is used by the target.
  1019. .IP "\fB\-mfpu=\fR\fIfloating-point-format\fR" 4
  1020. .IX Item "-mfpu=floating-point-format"
  1021. Select which Floating Point architecture is the target.
  1022. .IP "\fB\-mfloat\-abi=\fR\fIabi\fR" 4
  1023. .IX Item "-mfloat-abi=abi"
  1024. Select which floating point \s-1ABI\s0 is in use.
  1025. .IP "\fB\-mthumb\fR" 4
  1026. .IX Item "-mthumb"
  1027. Enable Thumb only instruction decoding.
  1028. .IP "\fB\-mapcs\-32 | \-mapcs\-26 | \-mapcs\-float | \-mapcs\-reentrant\fR" 4
  1029. .IX Item "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant"
  1030. Select which procedure calling convention is in use.
  1031. .IP "\fB\-EB | \-EL\fR" 4
  1032. .IX Item "-EB | -EL"
  1033. Select either big-endian (\-EB) or little-endian (\-EL) output.
  1034. .IP "\fB\-mthumb\-interwork\fR" 4
  1035. .IX Item "-mthumb-interwork"
  1036. Specify that the code has been generated with interworking between Thumb and
  1037. \&\s-1ARM\s0 code in mind.
  1038. .IP "\fB\-mccs\fR" 4
  1039. .IX Item "-mccs"
  1040. Turns on CodeComposer Studio assembly syntax compatibility mode.
  1041. .IP "\fB\-k\fR" 4
  1042. .IX Item "-k"
  1043. Specify that \s-1PIC\s0 code has been generated.
  1044. .PP
  1045. The following options are available when as is configured for
  1046. the Blackfin processor family.
  1047. .IP "\fB\-mcpu=\fR\fIprocessor\fR[\fB\-\fR\fIsirevision\fR]" 4
  1048. .IX Item "-mcpu=processor[-sirevision]"
  1049. This option specifies the target processor.  The optional \fIsirevision\fR
  1050. is not used in assembler.  It's here such that \s-1GCC\s0 can easily pass down its
  1051. \&\f(CW\*(C`\-mcpu=\*(C'\fR option.  The assembler will issue an
  1052. error message if an attempt is made to assemble an instruction which
  1053. will not execute on the target processor.  The following processor names are
  1054. recognized:
  1055. \&\f(CW\*(C`bf504\*(C'\fR,
  1056. \&\f(CW\*(C`bf506\*(C'\fR,
  1057. \&\f(CW\*(C`bf512\*(C'\fR,
  1058. \&\f(CW\*(C`bf514\*(C'\fR,
  1059. \&\f(CW\*(C`bf516\*(C'\fR,
  1060. \&\f(CW\*(C`bf518\*(C'\fR,
  1061. \&\f(CW\*(C`bf522\*(C'\fR,
  1062. \&\f(CW\*(C`bf523\*(C'\fR,
  1063. \&\f(CW\*(C`bf524\*(C'\fR,
  1064. \&\f(CW\*(C`bf525\*(C'\fR,
  1065. \&\f(CW\*(C`bf526\*(C'\fR,
  1066. \&\f(CW\*(C`bf527\*(C'\fR,
  1067. \&\f(CW\*(C`bf531\*(C'\fR,
  1068. \&\f(CW\*(C`bf532\*(C'\fR,
  1069. \&\f(CW\*(C`bf533\*(C'\fR,
  1070. \&\f(CW\*(C`bf534\*(C'\fR,
  1071. \&\f(CW\*(C`bf535\*(C'\fR (not implemented yet),
  1072. \&\f(CW\*(C`bf536\*(C'\fR,
  1073. \&\f(CW\*(C`bf537\*(C'\fR,
  1074. \&\f(CW\*(C`bf538\*(C'\fR,
  1075. \&\f(CW\*(C`bf539\*(C'\fR,
  1076. \&\f(CW\*(C`bf542\*(C'\fR,
  1077. \&\f(CW\*(C`bf542m\*(C'\fR,
  1078. \&\f(CW\*(C`bf544\*(C'\fR,
  1079. \&\f(CW\*(C`bf544m\*(C'\fR,
  1080. \&\f(CW\*(C`bf547\*(C'\fR,
  1081. \&\f(CW\*(C`bf547m\*(C'\fR,
  1082. \&\f(CW\*(C`bf548\*(C'\fR,
  1083. \&\f(CW\*(C`bf548m\*(C'\fR,
  1084. \&\f(CW\*(C`bf549\*(C'\fR,
  1085. \&\f(CW\*(C`bf549m\*(C'\fR,
  1086. \&\f(CW\*(C`bf561\*(C'\fR,
  1087. and
  1088. \&\f(CW\*(C`bf592\*(C'\fR.
  1089. .IP "\fB\-mfdpic\fR" 4
  1090. .IX Item "-mfdpic"
  1091. Assemble for the \s-1FDPIC ABI.\s0
  1092. .IP "\fB\-mno\-fdpic\fR" 4
  1093. .IX Item "-mno-fdpic"
  1094. .PD 0
  1095. .IP "\fB\-mnopic\fR" 4
  1096. .IX Item "-mnopic"
  1097. .PD
  1098. Disable \-mfdpic.
  1099. .PP
  1100. The following options are available when as is configured for
  1101. the Linux kernel \s-1BPF\s0 processor family.
  1102. .PP
  1103. \&\f(CW@chapter\fR \s-1BPF\s0 Dependent Features
  1104. .SS "Options"
  1105. .IX Subsection "Options"
  1106. .IP "\fB\-EB\fR" 4
  1107. .IX Item "-EB"
  1108. This option specifies that the assembler should emit big-endian eBPF.
  1109. .IP "\fB\-EL\fR" 4
  1110. .IX Item "-EL"
  1111. This option specifies that the assembler should emit little-endian
  1112. eBPF.
  1113. .PP
  1114. Note that if no endianness option is specified in the command line,
  1115. the host endianness is used.
  1116. See the info pages for documentation of the CRIS-specific options.
  1117. .PP
  1118. The following options are available when as is configured for
  1119. the C\-SKY processor family.
  1120. .IP "\fB\-march=\fR\fIarchname\fR" 4
  1121. .IX Item "-march=archname"
  1122. Assemble for architecture \fIarchname\fR.  The \fB\-\-help\fR option
  1123. lists valid values for \fIarchname\fR.
  1124. .IP "\fB\-mcpu=\fR\fIcpuname\fR" 4
  1125. .IX Item "-mcpu=cpuname"
  1126. Assemble for architecture \fIcpuname\fR.  The \fB\-\-help\fR option
  1127. lists valid values for \fIcpuname\fR.
  1128. .IP "\fB\-EL\fR" 4
  1129. .IX Item "-EL"
  1130. .PD 0
  1131. .IP "\fB\-mlittle\-endian\fR" 4
  1132. .IX Item "-mlittle-endian"
  1133. .PD
  1134. Generate little-endian output.
  1135. .IP "\fB\-EB\fR" 4
  1136. .IX Item "-EB"
  1137. .PD 0
  1138. .IP "\fB\-mbig\-endian\fR" 4
  1139. .IX Item "-mbig-endian"
  1140. .PD
  1141. Generate big-endian output.
  1142. .IP "\fB\-fpic\fR" 4
  1143. .IX Item "-fpic"
  1144. .PD 0
  1145. .IP "\fB\-pic\fR" 4
  1146. .IX Item "-pic"
  1147. .PD
  1148. Generate position-independent code.
  1149. .IP "\fB\-mljump\fR" 4
  1150. .IX Item "-mljump"
  1151. .PD 0
  1152. .IP "\fB\-mno\-ljump\fR" 4
  1153. .IX Item "-mno-ljump"
  1154. .PD
  1155. Enable/disable transformation of the short branch instructions
  1156. \&\f(CW\*(C`jbf\*(C'\fR, \f(CW\*(C`jbt\*(C'\fR, and \f(CW\*(C`jbr\*(C'\fR to \f(CW\*(C`jmpi\*(C'\fR.
  1157. This option is for V2 processors only.
  1158. It is ignored on \s-1CK801\s0 and \s-1CK802\s0 targets, which do not support the \f(CW\*(C`jmpi\*(C'\fR
  1159. instruction, and is enabled by default for other processors.
  1160. .IP "\fB\-mbranch\-stub\fR" 4
  1161. .IX Item "-mbranch-stub"
  1162. .PD 0
  1163. .IP "\fB\-mno\-branch\-stub\fR" 4
  1164. .IX Item "-mno-branch-stub"
  1165. .PD
  1166. Pass through \f(CW\*(C`R_CKCORE_PCREL_IMM26BY2\*(C'\fR relocations for \f(CW\*(C`bsr\*(C'\fR
  1167. instructions to the linker.
  1168. .Sp
  1169. This option is only available for bare-metal C\-SKY V2 \s-1ELF\s0 targets,
  1170. where it is enabled by default.  It cannot be used in code that will be
  1171. dynamically linked against shared libraries.
  1172. .IP "\fB\-force2bsr\fR" 4
  1173. .IX Item "-force2bsr"
  1174. .PD 0
  1175. .IP "\fB\-mforce2bsr\fR" 4
  1176. .IX Item "-mforce2bsr"
  1177. .IP "\fB\-no\-force2bsr\fR" 4
  1178. .IX Item "-no-force2bsr"
  1179. .IP "\fB\-mno\-force2bsr\fR" 4
  1180. .IX Item "-mno-force2bsr"
  1181. .PD
  1182. Enable/disable transformation of \f(CW\*(C`jbsr\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR.
  1183. This option is always enabled (and \fB\-mno\-force2bsr\fR is ignored)
  1184. for \s-1CK801/CK802\s0 targets.  It is also always enabled when
  1185. \&\fB\-mbranch\-stub\fR is in effect.
  1186. .IP "\fB\-jsri2bsr\fR" 4
  1187. .IX Item "-jsri2bsr"
  1188. .PD 0
  1189. .IP "\fB\-mjsri2bsr\fR" 4
  1190. .IX Item "-mjsri2bsr"
  1191. .IP "\fB\-no\-jsri2bsr\fR" 4
  1192. .IX Item "-no-jsri2bsr"
  1193. .IP "\fB\-mno\-jsri2bsr\fR" 4
  1194. .IX Item "-mno-jsri2bsr"
  1195. .PD
  1196. Enable/disable transformation of \f(CW\*(C`jsri\*(C'\fR instructions to \f(CW\*(C`bsr\*(C'\fR.
  1197. This option is enabled by default.
  1198. .IP "\fB\-mnolrw\fR" 4
  1199. .IX Item "-mnolrw"
  1200. .PD 0
  1201. .IP "\fB\-mno\-lrw\fR" 4
  1202. .IX Item "-mno-lrw"
  1203. .PD
  1204. Enable/disable transformation of \f(CW\*(C`lrw\*(C'\fR instructions into a
  1205. \&\f(CW\*(C`movih\*(C'\fR/\f(CW\*(C`ori\*(C'\fR pair.
  1206. .IP "\fB\-melrw\fR" 4
  1207. .IX Item "-melrw"
  1208. .PD 0
  1209. .IP "\fB\-mno\-elrw\fR" 4
  1210. .IX Item "-mno-elrw"
  1211. .PD
  1212. Enable/disable extended \f(CW\*(C`lrw\*(C'\fR instructions.
  1213. This option is enabled by default for CK800\-series processors.
  1214. .IP "\fB\-mlaf\fR" 4
  1215. .IX Item "-mlaf"
  1216. .PD 0
  1217. .IP "\fB\-mliterals\-after\-func\fR" 4
  1218. .IX Item "-mliterals-after-func"
  1219. .IP "\fB\-mno\-laf\fR" 4
  1220. .IX Item "-mno-laf"
  1221. .IP "\fB\-mno\-literals\-after\-func\fR" 4
  1222. .IX Item "-mno-literals-after-func"
  1223. .PD
  1224. Enable/disable placement of literal pools after each function.
  1225. .IP "\fB\-mlabr\fR" 4
  1226. .IX Item "-mlabr"
  1227. .PD 0
  1228. .IP "\fB\-mliterals\-after\-br\fR" 4
  1229. .IX Item "-mliterals-after-br"
  1230. .IP "\fB\-mno\-labr\fR" 4
  1231. .IX Item "-mno-labr"
  1232. .IP "\fB\-mnoliterals\-after\-br\fR" 4
  1233. .IX Item "-mnoliterals-after-br"
  1234. .PD
  1235. Enable/disable placement of literal pools after unconditional branches.
  1236. This option is enabled by default.
  1237. .IP "\fB\-mistack\fR" 4
  1238. .IX Item "-mistack"
  1239. .PD 0
  1240. .IP "\fB\-mno\-istack\fR" 4
  1241. .IX Item "-mno-istack"
  1242. .PD
  1243. Enable/disable interrupt stack instructions.  This option is enabled by
  1244. default on \s-1CK801, CK802,\s0 and \s-1CK802\s0 processors.
  1245. .PP
  1246. The following options explicitly enable certain optional instructions.
  1247. These features are also enabled implicitly by using \f(CW\*(C`\-mcpu=\*(C'\fR to specify
  1248. a processor that supports it.
  1249. .IP "\fB\-mhard\-float\fR" 4
  1250. .IX Item "-mhard-float"
  1251. Enable hard float instructions.
  1252. .IP "\fB\-mmp\fR" 4
  1253. .IX Item "-mmp"
  1254. Enable multiprocessor instructions.
  1255. .IP "\fB\-mcp\fR" 4
  1256. .IX Item "-mcp"
  1257. Enable coprocessor instructions.
  1258. .IP "\fB\-mcache\fR" 4
  1259. .IX Item "-mcache"
  1260. Enable cache prefetch instruction.
  1261. .IP "\fB\-msecurity\fR" 4
  1262. .IX Item "-msecurity"
  1263. Enable C\-SKY security instructions.
  1264. .IP "\fB\-mtrust\fR" 4
  1265. .IX Item "-mtrust"
  1266. Enable C\-SKY trust instructions.
  1267. .IP "\fB\-mdsp\fR" 4
  1268. .IX Item "-mdsp"
  1269. Enable \s-1DSP\s0 instructions.
  1270. .IP "\fB\-medsp\fR" 4
  1271. .IX Item "-medsp"
  1272. Enable enhanced \s-1DSP\s0 instructions.
  1273. .IP "\fB\-mvdsp\fR" 4
  1274. .IX Item "-mvdsp"
  1275. Enable vector \s-1DSP\s0 instructions.
  1276. .PP
  1277. The following options are available when as is configured for
  1278. an Epiphany processor.
  1279. .IP "\fB\-mepiphany\fR" 4
  1280. .IX Item "-mepiphany"
  1281. Specifies that the both 32 and 16 bit instructions are allowed.  This is the
  1282. default behavior.
  1283. .IP "\fB\-mepiphany16\fR" 4
  1284. .IX Item "-mepiphany16"
  1285. Restricts the permitted instructions to just the 16 bit set.
  1286. .PP
  1287. The following options are available when as is configured for an H8/300
  1288. processor.
  1289. \&\f(CW@chapter\fR H8/300 Dependent Features
  1290. .SS "Options"
  1291. .IX Subsection "Options"
  1292. The Renesas H8/300 version of \f(CW\*(C`as\*(C'\fR has one
  1293. machine-dependent option:
  1294. .IP "\fB\-h\-tick\-hex\fR" 4
  1295. .IX Item "-h-tick-hex"
  1296. Support H'00 style hex constants in addition to 0x00 style.
  1297. .IP "\fB\-mach=\fR\fIname\fR" 4
  1298. .IX Item "-mach=name"
  1299. Sets the H8300 machine variant.  The following machine names
  1300. are recognised:
  1301. \&\f(CW\*(C`h8300h\*(C'\fR,
  1302. \&\f(CW\*(C`h8300hn\*(C'\fR,
  1303. \&\f(CW\*(C`h8300s\*(C'\fR,
  1304. \&\f(CW\*(C`h8300sn\*(C'\fR,
  1305. \&\f(CW\*(C`h8300sx\*(C'\fR and 
  1306. \&\f(CW\*(C`h8300sxn\*(C'\fR.
  1307. .PP
  1308. The following options are available when as is configured for
  1309. an i386 processor.
  1310. .IP "\fB\-\-32 | \-\-x32 | \-\-64\fR" 4
  1311. .IX Item "--32 | --x32 | --64"
  1312. Select the word size, either 32 bits or 64 bits.  \fB\-\-32\fR
  1313. implies Intel i386 architecture, while \fB\-\-x32\fR and \fB\-\-64\fR
  1314. imply \s-1AMD\s0 x86\-64 architecture with 32\-bit or 64\-bit word-size
  1315. respectively.
  1316. .Sp
  1317. These options are only available with the \s-1ELF\s0 object file format, and
  1318. require that the necessary \s-1BFD\s0 support has been included (on a 32\-bit
  1319. platform you have to add \-\-enable\-64\-bit\-bfd to configure enable 64\-bit
  1320. usage and use x86\-64 as target platform).
  1321. .IP "\fB\-n\fR" 4
  1322. .IX Item "-n"
  1323. By default, x86 \s-1GAS\s0 replaces multiple nop instructions used for
  1324. alignment within code sections with multi-byte nop instructions such
  1325. as leal 0(%esi,1),%esi.  This switch disables the optimization if a single
  1326. byte nop (0x90) is explicitly specified as the fill byte for alignment.
  1327. .IP "\fB\-\-divide\fR" 4
  1328. .IX Item "--divide"
  1329. On SVR4\-derived platforms, the character \fB/\fR is treated as a comment
  1330. character, which means that it cannot be used in expressions.  The
  1331. \&\fB\-\-divide\fR option turns \fB/\fR into a normal character.  This does
  1332. not disable \fB/\fR at the beginning of a line starting a comment, or
  1333. affect using \fB#\fR for starting a comment.
  1334. .IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[+\fR\fI\s-1EXTENSION\s0\fR\fB...]\fR" 4
  1335. .IX Item "-march=CPU[+EXTENSION...]"
  1336. This option specifies the target processor.  The assembler will
  1337. issue an error message if an attempt is made to assemble an instruction
  1338. which will not execute on the target processor.  The following
  1339. processor names are recognized:
  1340. \&\f(CW\*(C`i8086\*(C'\fR,
  1341. \&\f(CW\*(C`i186\*(C'\fR,
  1342. \&\f(CW\*(C`i286\*(C'\fR,
  1343. \&\f(CW\*(C`i386\*(C'\fR,
  1344. \&\f(CW\*(C`i486\*(C'\fR,
  1345. \&\f(CW\*(C`i586\*(C'\fR,
  1346. \&\f(CW\*(C`i686\*(C'\fR,
  1347. \&\f(CW\*(C`pentium\*(C'\fR,
  1348. \&\f(CW\*(C`pentiumpro\*(C'\fR,
  1349. \&\f(CW\*(C`pentiumii\*(C'\fR,
  1350. \&\f(CW\*(C`pentiumiii\*(C'\fR,
  1351. \&\f(CW\*(C`pentium4\*(C'\fR,
  1352. \&\f(CW\*(C`prescott\*(C'\fR,
  1353. \&\f(CW\*(C`nocona\*(C'\fR,
  1354. \&\f(CW\*(C`core\*(C'\fR,
  1355. \&\f(CW\*(C`core2\*(C'\fR,
  1356. \&\f(CW\*(C`corei7\*(C'\fR,
  1357. \&\f(CW\*(C`iamcu\*(C'\fR,
  1358. \&\f(CW\*(C`k6\*(C'\fR,
  1359. \&\f(CW\*(C`k6_2\*(C'\fR,
  1360. \&\f(CW\*(C`athlon\*(C'\fR,
  1361. \&\f(CW\*(C`opteron\*(C'\fR,
  1362. \&\f(CW\*(C`k8\*(C'\fR,
  1363. \&\f(CW\*(C`amdfam10\*(C'\fR,
  1364. \&\f(CW\*(C`bdver1\*(C'\fR,
  1365. \&\f(CW\*(C`bdver2\*(C'\fR,
  1366. \&\f(CW\*(C`bdver3\*(C'\fR,
  1367. \&\f(CW\*(C`bdver4\*(C'\fR,
  1368. \&\f(CW\*(C`znver1\*(C'\fR,
  1369. \&\f(CW\*(C`znver2\*(C'\fR,
  1370. \&\f(CW\*(C`znver3\*(C'\fR,
  1371. \&\f(CW\*(C`btver1\*(C'\fR,
  1372. \&\f(CW\*(C`btver2\*(C'\fR,
  1373. \&\f(CW\*(C`generic32\*(C'\fR and
  1374. \&\f(CW\*(C`generic64\*(C'\fR.
  1375. .Sp
  1376. In addition to the basic instruction set, the assembler can be told to
  1377. accept various extension mnemonics.  For example,
  1378. \&\f(CW\*(C`\-march=i686+sse4+vmx\*(C'\fR extends \fIi686\fR with \fIsse4\fR and
  1379. \&\fIvmx\fR.  The following extensions are currently supported:
  1380. \&\f(CW8087\fR,
  1381. \&\f(CW287\fR,
  1382. \&\f(CW387\fR,
  1383. \&\f(CW687\fR,
  1384. \&\f(CW\*(C`no87\*(C'\fR,
  1385. \&\f(CW\*(C`no287\*(C'\fR,
  1386. \&\f(CW\*(C`no387\*(C'\fR,
  1387. \&\f(CW\*(C`no687\*(C'\fR,
  1388. \&\f(CW\*(C`cmov\*(C'\fR,
  1389. \&\f(CW\*(C`nocmov\*(C'\fR,
  1390. \&\f(CW\*(C`fxsr\*(C'\fR,
  1391. \&\f(CW\*(C`nofxsr\*(C'\fR,
  1392. \&\f(CW\*(C`mmx\*(C'\fR,
  1393. \&\f(CW\*(C`nommx\*(C'\fR,
  1394. \&\f(CW\*(C`sse\*(C'\fR,
  1395. \&\f(CW\*(C`sse2\*(C'\fR,
  1396. \&\f(CW\*(C`sse3\*(C'\fR,
  1397. \&\f(CW\*(C`sse4a\*(C'\fR,
  1398. \&\f(CW\*(C`ssse3\*(C'\fR,
  1399. \&\f(CW\*(C`sse4.1\*(C'\fR,
  1400. \&\f(CW\*(C`sse4.2\*(C'\fR,
  1401. \&\f(CW\*(C`sse4\*(C'\fR,
  1402. \&\f(CW\*(C`nosse\*(C'\fR,
  1403. \&\f(CW\*(C`nosse2\*(C'\fR,
  1404. \&\f(CW\*(C`nosse3\*(C'\fR,
  1405. \&\f(CW\*(C`nosse4a\*(C'\fR,
  1406. \&\f(CW\*(C`nossse3\*(C'\fR,
  1407. \&\f(CW\*(C`nosse4.1\*(C'\fR,
  1408. \&\f(CW\*(C`nosse4.2\*(C'\fR,
  1409. \&\f(CW\*(C`nosse4\*(C'\fR,
  1410. \&\f(CW\*(C`avx\*(C'\fR,
  1411. \&\f(CW\*(C`avx2\*(C'\fR,
  1412. \&\f(CW\*(C`noavx\*(C'\fR,
  1413. \&\f(CW\*(C`noavx2\*(C'\fR,
  1414. \&\f(CW\*(C`adx\*(C'\fR,
  1415. \&\f(CW\*(C`rdseed\*(C'\fR,
  1416. \&\f(CW\*(C`prfchw\*(C'\fR,
  1417. \&\f(CW\*(C`smap\*(C'\fR,
  1418. \&\f(CW\*(C`mpx\*(C'\fR,
  1419. \&\f(CW\*(C`sha\*(C'\fR,
  1420. \&\f(CW\*(C`rdpid\*(C'\fR,
  1421. \&\f(CW\*(C`ptwrite\*(C'\fR,
  1422. \&\f(CW\*(C`cet\*(C'\fR,
  1423. \&\f(CW\*(C`gfni\*(C'\fR,
  1424. \&\f(CW\*(C`vaes\*(C'\fR,
  1425. \&\f(CW\*(C`vpclmulqdq\*(C'\fR,
  1426. \&\f(CW\*(C`prefetchwt1\*(C'\fR,
  1427. \&\f(CW\*(C`clflushopt\*(C'\fR,
  1428. \&\f(CW\*(C`se1\*(C'\fR,
  1429. \&\f(CW\*(C`clwb\*(C'\fR,
  1430. \&\f(CW\*(C`movdiri\*(C'\fR,
  1431. \&\f(CW\*(C`movdir64b\*(C'\fR,
  1432. \&\f(CW\*(C`enqcmd\*(C'\fR,
  1433. \&\f(CW\*(C`serialize\*(C'\fR,
  1434. \&\f(CW\*(C`tsxldtrk\*(C'\fR,
  1435. \&\f(CW\*(C`kl\*(C'\fR,
  1436. \&\f(CW\*(C`nokl\*(C'\fR,
  1437. \&\f(CW\*(C`widekl\*(C'\fR,
  1438. \&\f(CW\*(C`nowidekl\*(C'\fR,
  1439. \&\f(CW\*(C`hreset\*(C'\fR,
  1440. \&\f(CW\*(C`avx512f\*(C'\fR,
  1441. \&\f(CW\*(C`avx512cd\*(C'\fR,
  1442. \&\f(CW\*(C`avx512er\*(C'\fR,
  1443. \&\f(CW\*(C`avx512pf\*(C'\fR,
  1444. \&\f(CW\*(C`avx512vl\*(C'\fR,
  1445. \&\f(CW\*(C`avx512bw\*(C'\fR,
  1446. \&\f(CW\*(C`avx512dq\*(C'\fR,
  1447. \&\f(CW\*(C`avx512ifma\*(C'\fR,
  1448. \&\f(CW\*(C`avx512vbmi\*(C'\fR,
  1449. \&\f(CW\*(C`avx512_4fmaps\*(C'\fR,
  1450. \&\f(CW\*(C`avx512_4vnniw\*(C'\fR,
  1451. \&\f(CW\*(C`avx512_vpopcntdq\*(C'\fR,
  1452. \&\f(CW\*(C`avx512_vbmi2\*(C'\fR,
  1453. \&\f(CW\*(C`avx512_vnni\*(C'\fR,
  1454. \&\f(CW\*(C`avx512_bitalg\*(C'\fR,
  1455. \&\f(CW\*(C`avx512_vp2intersect\*(C'\fR,
  1456. \&\f(CW\*(C`tdx\*(C'\fR,
  1457. \&\f(CW\*(C`avx512_bf16\*(C'\fR,
  1458. \&\f(CW\*(C`avx_vnni\*(C'\fR,
  1459. \&\f(CW\*(C`avx512_fp16\*(C'\fR,
  1460. \&\f(CW\*(C`noavx512f\*(C'\fR,
  1461. \&\f(CW\*(C`noavx512cd\*(C'\fR,
  1462. \&\f(CW\*(C`noavx512er\*(C'\fR,
  1463. \&\f(CW\*(C`noavx512pf\*(C'\fR,
  1464. \&\f(CW\*(C`noavx512vl\*(C'\fR,
  1465. \&\f(CW\*(C`noavx512bw\*(C'\fR,
  1466. \&\f(CW\*(C`noavx512dq\*(C'\fR,
  1467. \&\f(CW\*(C`noavx512ifma\*(C'\fR,
  1468. \&\f(CW\*(C`noavx512vbmi\*(C'\fR,
  1469. \&\f(CW\*(C`noavx512_4fmaps\*(C'\fR,
  1470. \&\f(CW\*(C`noavx512_4vnniw\*(C'\fR,
  1471. \&\f(CW\*(C`noavx512_vpopcntdq\*(C'\fR,
  1472. \&\f(CW\*(C`noavx512_vbmi2\*(C'\fR,
  1473. \&\f(CW\*(C`noavx512_vnni\*(C'\fR,
  1474. \&\f(CW\*(C`noavx512_bitalg\*(C'\fR,
  1475. \&\f(CW\*(C`noavx512_vp2intersect\*(C'\fR,
  1476. \&\f(CW\*(C`notdx\*(C'\fR,
  1477. \&\f(CW\*(C`noavx512_bf16\*(C'\fR,
  1478. \&\f(CW\*(C`noavx_vnni\*(C'\fR,
  1479. \&\f(CW\*(C`noavx512_fp16\*(C'\fR,
  1480. \&\f(CW\*(C`noenqcmd\*(C'\fR,
  1481. \&\f(CW\*(C`noserialize\*(C'\fR,
  1482. \&\f(CW\*(C`notsxldtrk\*(C'\fR,
  1483. \&\f(CW\*(C`amx_int8\*(C'\fR,
  1484. \&\f(CW\*(C`noamx_int8\*(C'\fR,
  1485. \&\f(CW\*(C`amx_bf16\*(C'\fR,
  1486. \&\f(CW\*(C`noamx_bf16\*(C'\fR,
  1487. \&\f(CW\*(C`amx_tile\*(C'\fR,
  1488. \&\f(CW\*(C`noamx_tile\*(C'\fR,
  1489. \&\f(CW\*(C`nouintr\*(C'\fR,
  1490. \&\f(CW\*(C`nohreset\*(C'\fR,
  1491. \&\f(CW\*(C`vmx\*(C'\fR,
  1492. \&\f(CW\*(C`vmfunc\*(C'\fR,
  1493. \&\f(CW\*(C`smx\*(C'\fR,
  1494. \&\f(CW\*(C`xsave\*(C'\fR,
  1495. \&\f(CW\*(C`xsaveopt\*(C'\fR,
  1496. \&\f(CW\*(C`xsavec\*(C'\fR,
  1497. \&\f(CW\*(C`xsaves\*(C'\fR,
  1498. \&\f(CW\*(C`aes\*(C'\fR,
  1499. \&\f(CW\*(C`pclmul\*(C'\fR,
  1500. \&\f(CW\*(C`fsgsbase\*(C'\fR,
  1501. \&\f(CW\*(C`rdrnd\*(C'\fR,
  1502. \&\f(CW\*(C`f16c\*(C'\fR,
  1503. \&\f(CW\*(C`bmi2\*(C'\fR,
  1504. \&\f(CW\*(C`fma\*(C'\fR,
  1505. \&\f(CW\*(C`movbe\*(C'\fR,
  1506. \&\f(CW\*(C`ept\*(C'\fR,
  1507. \&\f(CW\*(C`lzcnt\*(C'\fR,
  1508. \&\f(CW\*(C`popcnt\*(C'\fR,
  1509. \&\f(CW\*(C`hle\*(C'\fR,
  1510. \&\f(CW\*(C`rtm\*(C'\fR,
  1511. \&\f(CW\*(C`invpcid\*(C'\fR,
  1512. \&\f(CW\*(C`clflush\*(C'\fR,
  1513. \&\f(CW\*(C`mwaitx\*(C'\fR,
  1514. \&\f(CW\*(C`clzero\*(C'\fR,
  1515. \&\f(CW\*(C`wbnoinvd\*(C'\fR,
  1516. \&\f(CW\*(C`pconfig\*(C'\fR,
  1517. \&\f(CW\*(C`waitpkg\*(C'\fR,
  1518. \&\f(CW\*(C`uintr\*(C'\fR,
  1519. \&\f(CW\*(C`cldemote\*(C'\fR,
  1520. \&\f(CW\*(C`rdpru\*(C'\fR,
  1521. \&\f(CW\*(C`mcommit\*(C'\fR,
  1522. \&\f(CW\*(C`sev_es\*(C'\fR,
  1523. \&\f(CW\*(C`lwp\*(C'\fR,
  1524. \&\f(CW\*(C`fma4\*(C'\fR,
  1525. \&\f(CW\*(C`xop\*(C'\fR,
  1526. \&\f(CW\*(C`cx16\*(C'\fR,
  1527. \&\f(CW\*(C`syscall\*(C'\fR,
  1528. \&\f(CW\*(C`rdtscp\*(C'\fR,
  1529. \&\f(CW\*(C`3dnow\*(C'\fR,
  1530. \&\f(CW\*(C`3dnowa\*(C'\fR,
  1531. \&\f(CW\*(C`sse4a\*(C'\fR,
  1532. \&\f(CW\*(C`sse5\*(C'\fR,
  1533. \&\f(CW\*(C`snp\*(C'\fR,
  1534. \&\f(CW\*(C`invlpgb\*(C'\fR,
  1535. \&\f(CW\*(C`tlbsync\*(C'\fR,
  1536. \&\f(CW\*(C`svme\*(C'\fR and
  1537. \&\f(CW\*(C`padlock\*(C'\fR.
  1538. Note that rather than extending a basic instruction set, the extension
  1539. mnemonics starting with \f(CW\*(C`no\*(C'\fR revoke the respective functionality.
  1540. .Sp
  1541. When the \f(CW\*(C`.arch\*(C'\fR directive is used with \fB\-march\fR, the
  1542. \&\f(CW\*(C`.arch\*(C'\fR directive will take precedent.
  1543. .IP "\fB\-mtune=\fR\fI\s-1CPU\s0\fR" 4
  1544. .IX Item "-mtune=CPU"
  1545. This option specifies a processor to optimize for. When used in
  1546. conjunction with the \fB\-march\fR option, only instructions
  1547. of the processor specified by the \fB\-march\fR option will be
  1548. generated.
  1549. .Sp
  1550. Valid \fI\s-1CPU\s0\fR values are identical to the processor list of
  1551. \&\fB\-march=\fR\fI\s-1CPU\s0\fR.
  1552. .IP "\fB\-msse2avx\fR" 4
  1553. .IX Item "-msse2avx"
  1554. This option specifies that the assembler should encode \s-1SSE\s0 instructions
  1555. with \s-1VEX\s0 prefix.
  1556. .IP "\fB\-muse\-unaligned\-vector\-move\fR" 4
  1557. .IX Item "-muse-unaligned-vector-move"
  1558. This option specifies that the assembler should encode aligned vector
  1559. move as unaligned vector move.
  1560. .IP "\fB\-msse\-check=\fR\fInone\fR" 4
  1561. .IX Item "-msse-check=none"
  1562. .PD 0
  1563. .IP "\fB\-msse\-check=\fR\fIwarning\fR" 4
  1564. .IX Item "-msse-check=warning"
  1565. .IP "\fB\-msse\-check=\fR\fIerror\fR" 4
  1566. .IX Item "-msse-check=error"
  1567. .PD
  1568. These options control if the assembler should check \s-1SSE\s0 instructions.
  1569. \&\fB\-msse\-check=\fR\fInone\fR will make the assembler not to check \s-1SSE\s0
  1570. instructions,  which is the default.  \fB\-msse\-check=\fR\fIwarning\fR
  1571. will make the assembler issue a warning for any \s-1SSE\s0 instruction.
  1572. \&\fB\-msse\-check=\fR\fIerror\fR will make the assembler issue an error
  1573. for any \s-1SSE\s0 instruction.
  1574. .IP "\fB\-mavxscalar=\fR\fI128\fR" 4
  1575. .IX Item "-mavxscalar=128"
  1576. .PD 0
  1577. .IP "\fB\-mavxscalar=\fR\fI256\fR" 4
  1578. .IX Item "-mavxscalar=256"
  1579. .PD
  1580. These options control how the assembler should encode scalar \s-1AVX\s0
  1581. instructions.  \fB\-mavxscalar=\fR\fI128\fR will encode scalar
  1582. \&\s-1AVX\s0 instructions with 128bit vector length, which is the default.
  1583. \&\fB\-mavxscalar=\fR\fI256\fR will encode scalar \s-1AVX\s0 instructions
  1584. with 256bit vector length.
  1585. .Sp
  1586. \&\s-1WARNING:\s0 Don't use this for production code \- due to \s-1CPU\s0 errata the
  1587. resulting code may not work on certain models.
  1588. .IP "\fB\-mvexwig=\fR\fI0\fR" 4
  1589. .IX Item "-mvexwig=0"
  1590. .PD 0
  1591. .IP "\fB\-mvexwig=\fR\fI1\fR" 4
  1592. .IX Item "-mvexwig=1"
  1593. .PD
  1594. These options control how the assembler should encode \s-1VEX\s0.W\-ignored (\s-1WIG\s0)
  1595. \&\s-1VEX\s0 instructions.  \fB\-mvexwig=\fR\fI0\fR will encode \s-1WIG VEX\s0
  1596. instructions with vex.w = 0, which is the default.
  1597. \&\fB\-mvexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with
  1598. vex.w = 1.
  1599. .Sp
  1600. \&\s-1WARNING:\s0 Don't use this for production code \- due to \s-1CPU\s0 errata the
  1601. resulting code may not work on certain models.
  1602. .IP "\fB\-mevexlig=\fR\fI128\fR" 4
  1603. .IX Item "-mevexlig=128"
  1604. .PD 0
  1605. .IP "\fB\-mevexlig=\fR\fI256\fR" 4
  1606. .IX Item "-mevexlig=256"
  1607. .IP "\fB\-mevexlig=\fR\fI512\fR" 4
  1608. .IX Item "-mevexlig=512"
  1609. .PD
  1610. These options control how the assembler should encode length-ignored
  1611. (\s-1LIG\s0) \s-1EVEX\s0 instructions.  \fB\-mevexlig=\fR\fI128\fR will encode \s-1LIG
  1612. EVEX\s0 instructions with 128bit vector length, which is the default.
  1613. \&\fB\-mevexlig=\fR\fI256\fR and \fB\-mevexlig=\fR\fI512\fR will
  1614. encode \s-1LIG EVEX\s0 instructions with 256bit and 512bit vector length,
  1615. respectively.
  1616. .IP "\fB\-mevexwig=\fR\fI0\fR" 4
  1617. .IX Item "-mevexwig=0"
  1618. .PD 0
  1619. .IP "\fB\-mevexwig=\fR\fI1\fR" 4
  1620. .IX Item "-mevexwig=1"
  1621. .PD
  1622. These options control how the assembler should encode w\-ignored (\s-1WIG\s0)
  1623. \&\s-1EVEX\s0 instructions.  \fB\-mevexwig=\fR\fI0\fR will encode \s-1WIG
  1624. EVEX\s0 instructions with evex.w = 0, which is the default.
  1625. \&\fB\-mevexwig=\fR\fI1\fR will encode \s-1WIG EVEX\s0 instructions with
  1626. evex.w = 1.
  1627. .IP "\fB\-mmnemonic=\fR\fIatt\fR" 4
  1628. .IX Item "-mmnemonic=att"
  1629. .PD 0
  1630. .IP "\fB\-mmnemonic=\fR\fIintel\fR" 4
  1631. .IX Item "-mmnemonic=intel"
  1632. .PD
  1633. This option specifies instruction mnemonic for matching instructions.
  1634. The \f(CW\*(C`.att_mnemonic\*(C'\fR and \f(CW\*(C`.intel_mnemonic\*(C'\fR directives will
  1635. take precedent.
  1636. .IP "\fB\-msyntax=\fR\fIatt\fR" 4
  1637. .IX Item "-msyntax=att"
  1638. .PD 0
  1639. .IP "\fB\-msyntax=\fR\fIintel\fR" 4
  1640. .IX Item "-msyntax=intel"
  1641. .PD
  1642. This option specifies instruction syntax when processing instructions.
  1643. The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will
  1644. take precedent.
  1645. .IP "\fB\-mnaked\-reg\fR" 4
  1646. .IX Item "-mnaked-reg"
  1647. This option specifies that registers don't require a \fB%\fR prefix.
  1648. The \f(CW\*(C`.att_syntax\*(C'\fR and \f(CW\*(C`.intel_syntax\*(C'\fR directives will take precedent.
  1649. .IP "\fB\-madd\-bnd\-prefix\fR" 4
  1650. .IX Item "-madd-bnd-prefix"
  1651. This option forces the assembler to add \s-1BND\s0 prefix to all branches, even
  1652. if such prefix was not explicitly specified in the source code.
  1653. .IP "\fB\-mno\-shared\fR" 4
  1654. .IX Item "-mno-shared"
  1655. On \s-1ELF\s0 target, the assembler normally optimizes out non-PLT relocations
  1656. against defined non-weak global branch targets with default visibility.
  1657. The \fB\-mshared\fR option tells the assembler to generate code which
  1658. may go into a shared library where all non-weak global branch targets
  1659. with default visibility can be preempted.  The resulting code is
  1660. slightly bigger.  This option only affects the handling of branch
  1661. instructions.
  1662. .IP "\fB\-mbig\-obj\fR" 4
  1663. .IX Item "-mbig-obj"
  1664. On \s-1PE/COFF\s0 target this option forces the use of big object file
  1665. format, which allows more than 32768 sections.
  1666. .IP "\fB\-momit\-lock\-prefix=\fR\fIno\fR" 4
  1667. .IX Item "-momit-lock-prefix=no"
  1668. .PD 0
  1669. .IP "\fB\-momit\-lock\-prefix=\fR\fIyes\fR" 4
  1670. .IX Item "-momit-lock-prefix=yes"
  1671. .PD
  1672. These options control how the assembler should encode lock prefix.
  1673. This option is intended as a workaround for processors, that fail on
  1674. lock prefix. This option can only be safely used with single-core,
  1675. single-thread computers
  1676. \&\fB\-momit\-lock\-prefix=\fR\fIyes\fR will omit all lock prefixes.
  1677. \&\fB\-momit\-lock\-prefix=\fR\fIno\fR will encode lock prefix as usual,
  1678. which is the default.
  1679. .IP "\fB\-mfence\-as\-lock\-add=\fR\fIno\fR" 4
  1680. .IX Item "-mfence-as-lock-add=no"
  1681. .PD 0
  1682. .IP "\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR" 4
  1683. .IX Item "-mfence-as-lock-add=yes"
  1684. .PD
  1685. These options control how the assembler should encode lfence, mfence and
  1686. sfence.
  1687. \&\fB\-mfence\-as\-lock\-add=\fR\fIyes\fR will encode lfence, mfence and
  1688. sfence as \fBlock addl \f(CB$0x0\fB, (%rsp)\fR in 64\-bit mode and
  1689. \&\fBlock addl \f(CB$0x0\fB, (%esp)\fR in 32\-bit mode.
  1690. \&\fB\-mfence\-as\-lock\-add=\fR\fIno\fR will encode lfence, mfence and
  1691. sfence as usual, which is the default.
  1692. .IP "\fB\-mrelax\-relocations=\fR\fIno\fR" 4
  1693. .IX Item "-mrelax-relocations=no"
  1694. .PD 0
  1695. .IP "\fB\-mrelax\-relocations=\fR\fIyes\fR" 4
  1696. .IX Item "-mrelax-relocations=yes"
  1697. .PD
  1698. These options control whether the assembler should generate relax
  1699. relocations, R_386_GOT32X, in 32\-bit mode, or R_X86_64_GOTPCRELX and
  1700. R_X86_64_REX_GOTPCRELX, in 64\-bit mode.
  1701. \&\fB\-mrelax\-relocations=\fR\fIyes\fR will generate relax relocations.
  1702. \&\fB\-mrelax\-relocations=\fR\fIno\fR will not generate relax
  1703. relocations.  The default can be controlled by a configure option
  1704. \&\fB\-\-enable\-x86\-relax\-relocations\fR.
  1705. .IP "\fB\-malign\-branch\-boundary=\fR\fI\s-1NUM\s0\fR" 4
  1706. .IX Item "-malign-branch-boundary=NUM"
  1707. This option controls how the assembler should align branches with segment
  1708. prefixes or \s-1NOP.\s0  \fI\s-1NUM\s0\fR must be a power of 2.  It should be 0 or
  1709. no less than 16.  Branches will be aligned within \fI\s-1NUM\s0\fR byte
  1710. boundary.  \fB\-malign\-branch\-boundary=0\fR, which is the default,
  1711. doesn't align branches.
  1712. .IP "\fB\-malign\-branch=\fR\fI\s-1TYPE\s0\fR\fB[+\fR\fI\s-1TYPE\s0\fR\fB...]\fR" 4
  1713. .IX Item "-malign-branch=TYPE[+TYPE...]"
  1714. This option specifies types of branches to align. \fI\s-1TYPE\s0\fR is
  1715. combination of \fBjcc\fR, which aligns conditional jumps,
  1716. \&\fBfused\fR, which aligns fused conditional jumps, \fBjmp\fR,
  1717. which aligns unconditional jumps, \fBcall\fR which aligns calls,
  1718. \&\fBret\fR, which aligns rets, \fBindirect\fR, which aligns indirect
  1719. jumps and calls.  The default is \fB\-malign\-branch=jcc+fused+jmp\fR.
  1720. .IP "\fB\-malign\-branch\-prefix\-size=\fR\fI\s-1NUM\s0\fR" 4
  1721. .IX Item "-malign-branch-prefix-size=NUM"
  1722. This option specifies the maximum number of prefixes on an instruction
  1723. to align branches.  \fI\s-1NUM\s0\fR should be between 0 and 5.  The default
  1724. \&\fI\s-1NUM\s0\fR is 5.
  1725. .IP "\fB\-mbranches\-within\-32B\-boundaries\fR" 4
  1726. .IX Item "-mbranches-within-32B-boundaries"
  1727. This option aligns conditional jumps, fused conditional jumps and
  1728. unconditional jumps within 32 byte boundary with up to 5 segment prefixes
  1729. on an instruction.  It is equivalent to
  1730. \&\fB\-malign\-branch\-boundary=32\fR
  1731. \&\fB\-malign\-branch=jcc+fused+jmp\fR
  1732. \&\fB\-malign\-branch\-prefix\-size=5\fR.
  1733. The default doesn't align branches.
  1734. .IP "\fB\-mlfence\-after\-load=\fR\fIno\fR" 4
  1735. .IX Item "-mlfence-after-load=no"
  1736. .PD 0
  1737. .IP "\fB\-mlfence\-after\-load=\fR\fIyes\fR" 4
  1738. .IX Item "-mlfence-after-load=yes"
  1739. .PD
  1740. These options control whether the assembler should generate lfence
  1741. after load instructions.  \fB\-mlfence\-after\-load=\fR\fIyes\fR will
  1742. generate lfence.  \fB\-mlfence\-after\-load=\fR\fIno\fR will not generate
  1743. lfence, which is the default.
  1744. .IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fInone\fR" 4
  1745. .IX Item "-mlfence-before-indirect-branch=none"
  1746. .PD 0
  1747. .IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fIall\fR" 4
  1748. .IX Item "-mlfence-before-indirect-branch=all"
  1749. .IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fIregister\fR" 4
  1750. .IX Item "-mlfence-before-indirect-branch=register"
  1751. .IP "\fB\-mlfence\-before\-indirect\-branch=\fR\fImemory\fR" 4
  1752. .IX Item "-mlfence-before-indirect-branch=memory"
  1753. .PD
  1754. These options control whether the assembler should generate lfence
  1755. before indirect near branch instructions.
  1756. \&\fB\-mlfence\-before\-indirect\-branch=\fR\fIall\fR will generate lfence
  1757. before indirect near branch via register and issue a warning before
  1758. indirect near branch via memory.
  1759. It also implicitly sets \fB\-mlfence\-before\-ret=\fR\fIshl\fR when
  1760. there's no explicit \fB\-mlfence\-before\-ret=\fR.
  1761. \&\fB\-mlfence\-before\-indirect\-branch=\fR\fIregister\fR will generate
  1762. lfence before indirect near branch via register.
  1763. \&\fB\-mlfence\-before\-indirect\-branch=\fR\fImemory\fR will issue a
  1764. warning before indirect near branch via memory.
  1765. \&\fB\-mlfence\-before\-indirect\-branch=\fR\fInone\fR will not generate
  1766. lfence nor issue warning, which is the default.  Note that lfence won't
  1767. be generated before indirect near branch via register with
  1768. \&\fB\-mlfence\-after\-load=\fR\fIyes\fR since lfence will be generated
  1769. after loading branch target register.
  1770. .IP "\fB\-mlfence\-before\-ret=\fR\fInone\fR" 4
  1771. .IX Item "-mlfence-before-ret=none"
  1772. .PD 0
  1773. .IP "\fB\-mlfence\-before\-ret=\fR\fIshl\fR" 4
  1774. .IX Item "-mlfence-before-ret=shl"
  1775. .IP "\fB\-mlfence\-before\-ret=\fR\fIor\fR" 4
  1776. .IX Item "-mlfence-before-ret=or"
  1777. .IP "\fB\-mlfence\-before\-ret=\fR\fIyes\fR" 4
  1778. .IX Item "-mlfence-before-ret=yes"
  1779. .IP "\fB\-mlfence\-before\-ret=\fR\fInot\fR" 4
  1780. .IX Item "-mlfence-before-ret=not"
  1781. .PD
  1782. These options control whether the assembler should generate lfence
  1783. before ret.  \fB\-mlfence\-before\-ret=\fR\fIor\fR will generate
  1784. generate or instruction with lfence.
  1785. \&\fB\-mlfence\-before\-ret=\fR\fIshl/yes\fR will generate shl instruction
  1786. with lfence. \fB\-mlfence\-before\-ret=\fR\fInot\fR will generate not
  1787. instruction with lfence. \fB\-mlfence\-before\-ret=\fR\fInone\fR will not
  1788. generate lfence, which is the default.
  1789. .IP "\fB\-mx86\-used\-note=\fR\fIno\fR" 4
  1790. .IX Item "-mx86-used-note=no"
  1791. .PD 0
  1792. .IP "\fB\-mx86\-used\-note=\fR\fIyes\fR" 4
  1793. .IX Item "-mx86-used-note=yes"
  1794. .PD
  1795. These options control whether the assembler should generate
  1796. \&\s-1GNU_PROPERTY_X86_ISA_1_USED\s0 and \s-1GNU_PROPERTY_X86_FEATURE_2_USED
  1797. GNU\s0 property notes.  The default can be controlled by the
  1798. \&\fB\-\-enable\-x86\-used\-note\fR configure option.
  1799. .IP "\fB\-mevexrcig=\fR\fIrne\fR" 4
  1800. .IX Item "-mevexrcig=rne"
  1801. .PD 0
  1802. .IP "\fB\-mevexrcig=\fR\fIrd\fR" 4
  1803. .IX Item "-mevexrcig=rd"
  1804. .IP "\fB\-mevexrcig=\fR\fIru\fR" 4
  1805. .IX Item "-mevexrcig=ru"
  1806. .IP "\fB\-mevexrcig=\fR\fIrz\fR" 4
  1807. .IX Item "-mevexrcig=rz"
  1808. .PD
  1809. These options control how the assembler should encode SAE-only
  1810. \&\s-1EVEX\s0 instructions.  \fB\-mevexrcig=\fR\fIrne\fR will encode \s-1RC\s0 bits
  1811. of \s-1EVEX\s0 instruction with 00, which is the default.
  1812. \&\fB\-mevexrcig=\fR\fIrd\fR, \fB\-mevexrcig=\fR\fIru\fR
  1813. and \fB\-mevexrcig=\fR\fIrz\fR will encode SAE-only \s-1EVEX\s0 instructions
  1814. with 01, 10 and 11 \s-1RC\s0 bits, respectively.
  1815. .IP "\fB\-mamd64\fR" 4
  1816. .IX Item "-mamd64"
  1817. .PD 0
  1818. .IP "\fB\-mintel64\fR" 4
  1819. .IX Item "-mintel64"
  1820. .PD
  1821. This option specifies that the assembler should accept only \s-1AMD64\s0 or
  1822. Intel64 \s-1ISA\s0 in 64\-bit mode.  The default is to accept common, Intel64
  1823. only and \s-1AMD64\s0 ISAs.
  1824. .IP "\fB\-O0 | \-O | \-O1 | \-O2 | \-Os\fR" 4
  1825. .IX Item "-O0 | -O | -O1 | -O2 | -Os"
  1826. Optimize instruction encoding with smaller instruction size.  \fB\-O\fR
  1827. and \fB\-O1\fR encode 64\-bit register load instructions with 64\-bit
  1828. immediate as 32\-bit register load instructions with 31\-bit or 32\-bits
  1829. immediates, encode 64\-bit register clearing instructions with 32\-bit
  1830. register clearing instructions, encode 256\-bit/512\-bit \s-1VEX/EVEX\s0 vector
  1831. register clearing instructions with 128\-bit \s-1VEX\s0 vector register
  1832. clearing instructions, encode 128\-bit/256\-bit \s-1EVEX\s0 vector
  1833. register load/store instructions with \s-1VEX\s0 vector register load/store
  1834. instructions, and encode 128\-bit/256\-bit \s-1EVEX\s0 packed integer logical
  1835. instructions with 128\-bit/256\-bit \s-1VEX\s0 packed integer logical.
  1836. .Sp
  1837. \&\fB\-O2\fR includes \fB\-O1\fR optimization plus encodes
  1838. 256\-bit/512\-bit \s-1EVEX\s0 vector register clearing instructions with 128\-bit
  1839. \&\s-1EVEX\s0 vector register clearing instructions.  In 64\-bit mode \s-1VEX\s0 encoded
  1840. instructions with commutative source operands will also have their
  1841. source operands swapped if this allows using the 2\-byte \s-1VEX\s0 prefix form
  1842. instead of the 3\-byte one.  Certain forms of \s-1AND\s0 as well as \s-1OR\s0 with the
  1843. same (register) operand specified twice will also be changed to \s-1TEST.\s0
  1844. .Sp
  1845. \&\fB\-Os\fR includes \fB\-O2\fR optimization plus encodes 16\-bit, 32\-bit
  1846. and 64\-bit register tests with immediate as 8\-bit register test with
  1847. immediate.  \fB\-O0\fR turns off this optimization.
  1848. .PP
  1849. The following options are available when as is configured for the
  1850. Ubicom \s-1IP2K\s0 series.
  1851. .IP "\fB\-mip2022ext\fR" 4
  1852. .IX Item "-mip2022ext"
  1853. Specifies that the extended \s-1IP2022\s0 instructions are allowed.
  1854. .IP "\fB\-mip2022\fR" 4
  1855. .IX Item "-mip2022"
  1856. Restores the default behaviour, which restricts the permitted instructions to
  1857. just the basic \s-1IP2022\s0 ones.
  1858. .PP
  1859. The following options are available when as is configured for the
  1860. Renesas M32C and M16C processors.
  1861. .IP "\fB\-m32c\fR" 4
  1862. .IX Item "-m32c"
  1863. Assemble M32C instructions.
  1864. .IP "\fB\-m16c\fR" 4
  1865. .IX Item "-m16c"
  1866. Assemble M16C instructions (the default).
  1867. .IP "\fB\-relax\fR" 4
  1868. .IX Item "-relax"
  1869. Enable support for link-time relaxations.
  1870. .IP "\fB\-h\-tick\-hex\fR" 4
  1871. .IX Item "-h-tick-hex"
  1872. Support H'00 style hex constants in addition to 0x00 style.
  1873. .PP
  1874. The following options are available when as is configured for the
  1875. Renesas M32R (formerly Mitsubishi M32R) series.
  1876. .IP "\fB\-\-m32rx\fR" 4
  1877. .IX Item "--m32rx"
  1878. Specify which processor in the M32R family is the target.  The default
  1879. is normally the M32R, but this option changes it to the M32RX.
  1880. .IP "\fB\-\-warn\-explicit\-parallel\-conflicts or \-\-Wp\fR" 4
  1881. .IX Item "--warn-explicit-parallel-conflicts or --Wp"
  1882. Produce warning messages when questionable parallel constructs are
  1883. encountered.
  1884. .IP "\fB\-\-no\-warn\-explicit\-parallel\-conflicts or \-\-Wnp\fR" 4
  1885. .IX Item "--no-warn-explicit-parallel-conflicts or --Wnp"
  1886. Do not produce warning messages when questionable parallel constructs are
  1887. encountered.
  1888. .PP
  1889. The following options are available when as is configured for the
  1890. Motorola 68000 series.
  1891. .IP "\fB\-l\fR" 4
  1892. .IX Item "-l"
  1893. Shorten references to undefined symbols, to one word instead of two.
  1894. .IP "\fB\-m68000 | \-m68008 | \-m68010 | \-m68020 | \-m68030\fR" 4
  1895. .IX Item "-m68000 | -m68008 | -m68010 | -m68020 | -m68030"
  1896. .PD 0
  1897. .IP "\fB| \-m68040 | \-m68060 | \-m68302 | \-m68331 | \-m68332\fR" 4
  1898. .IX Item "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332"
  1899. .IP "\fB| \-m68333 | \-m68340 | \-mcpu32 | \-m5200\fR" 4
  1900. .IX Item "| -m68333 | -m68340 | -mcpu32 | -m5200"
  1901. .PD
  1902. Specify what processor in the 68000 family is the target.  The default
  1903. is normally the 68020, but this can be changed at configuration time.
  1904. .IP "\fB\-m68881 | \-m68882 | \-mno\-68881 | \-mno\-68882\fR" 4
  1905. .IX Item "-m68881 | -m68882 | -mno-68881 | -mno-68882"
  1906. The target machine does (or does not) have a floating-point coprocessor.
  1907. The default is to assume a coprocessor for 68020, 68030, and cpu32.  Although
  1908. the basic 68000 is not compatible with the 68881, a combination of the
  1909. two can be specified, since it's possible to do emulation of the
  1910. coprocessor instructions with the main processor.
  1911. .IP "\fB\-m68851 | \-mno\-68851\fR" 4
  1912. .IX Item "-m68851 | -mno-68851"
  1913. The target machine does (or does not) have a memory-management
  1914. unit coprocessor.  The default is to assume an \s-1MMU\s0 for 68020 and up.
  1915. .PP
  1916. The following options are available when as is configured for an
  1917. Altera Nios \s-1II\s0 processor.
  1918. .IP "\fB\-relax\-section\fR" 4
  1919. .IX Item "-relax-section"
  1920. Replace identified out-of-range branches with PC-relative \f(CW\*(C`jmp\*(C'\fR
  1921. sequences when possible.  The generated code sequences are suitable
  1922. for use in position-independent code, but there is a practical limit
  1923. on the extended branch range because of the length of the sequences.
  1924. This option is the default.
  1925. .IP "\fB\-relax\-all\fR" 4
  1926. .IX Item "-relax-all"
  1927. Replace branch instructions not determinable to be in range
  1928. and all call instructions with \f(CW\*(C`jmp\*(C'\fR and \f(CW\*(C`callr\*(C'\fR sequences
  1929. (respectively).  This option generates absolute relocations against the
  1930. target symbols and is not appropriate for position-independent code.
  1931. .IP "\fB\-no\-relax\fR" 4
  1932. .IX Item "-no-relax"
  1933. Do not replace any branches or calls.
  1934. .IP "\fB\-EB\fR" 4
  1935. .IX Item "-EB"
  1936. Generate big-endian output.
  1937. .IP "\fB\-EL\fR" 4
  1938. .IX Item "-EL"
  1939. Generate little-endian output.  This is the default.
  1940. .IP "\fB\-march=\fR\fIarchitecture\fR" 4
  1941. .IX Item "-march=architecture"
  1942. This option specifies the target architecture.  The assembler issues
  1943. an error message if an attempt is made to assemble an instruction which
  1944. will not execute on the target architecture.  The following architecture
  1945. names are recognized:
  1946. \&\f(CW\*(C`r1\*(C'\fR,
  1947. \&\f(CW\*(C`r2\*(C'\fR.  
  1948. The default is \f(CW\*(C`r1\*(C'\fR.
  1949. .PP
  1950. The following options are available when as is configured for a
  1951. \&\s-1PRU\s0 processor.
  1952. .IP "\fB\-mlink\-relax\fR" 4
  1953. .IX Item "-mlink-relax"
  1954. Assume that \s-1LD\s0 would optimize \s-1LDI32\s0 instructions by checking the upper
  1955. 16 bits of the \fIexpression\fR. If they are all zeros, then \s-1LD\s0 would
  1956. shorten the \s-1LDI32\s0 instruction to a single \s-1LDI.\s0 In such case \f(CW\*(C`as\*(C'\fR
  1957. will output \s-1DIFF\s0 relocations for diff expressions.
  1958. .IP "\fB\-mno\-link\-relax\fR" 4
  1959. .IX Item "-mno-link-relax"
  1960. Assume that \s-1LD\s0 would not optimize \s-1LDI32\s0 instructions. As a consequence,
  1961. \&\s-1DIFF\s0 relocations will not be emitted.
  1962. .IP "\fB\-mno\-warn\-regname\-label\fR" 4
  1963. .IX Item "-mno-warn-regname-label"
  1964. Do not warn if a label name matches a register name. Usually assembler
  1965. programmers will want this warning to be emitted. C compilers may want
  1966. to turn this off.
  1967. .PP
  1968. The following options are available when as is configured for
  1969. a \s-1MIPS\s0 processor.
  1970. .IP "\fB\-G\fR \fInum\fR" 4
  1971. .IX Item "-G num"
  1972. This option sets the largest size of an object that can be referenced
  1973. implicitly with the \f(CW\*(C`gp\*(C'\fR register.  It is only accepted for targets that
  1974. use \s-1ECOFF\s0 format, such as a DECstation running Ultrix.  The default value is 8.
  1975. .IP "\fB\-EB\fR" 4
  1976. .IX Item "-EB"
  1977. Generate \*(L"big endian\*(R" format output.
  1978. .IP "\fB\-EL\fR" 4
  1979. .IX Item "-EL"
  1980. Generate \*(L"little endian\*(R" format output.
  1981. .IP "\fB\-mips1\fR" 4
  1982. .IX Item "-mips1"
  1983. .PD 0
  1984. .IP "\fB\-mips2\fR" 4
  1985. .IX Item "-mips2"
  1986. .IP "\fB\-mips3\fR" 4
  1987. .IX Item "-mips3"
  1988. .IP "\fB\-mips4\fR" 4
  1989. .IX Item "-mips4"
  1990. .IP "\fB\-mips5\fR" 4
  1991. .IX Item "-mips5"
  1992. .IP "\fB\-mips32\fR" 4
  1993. .IX Item "-mips32"
  1994. .IP "\fB\-mips32r2\fR" 4
  1995. .IX Item "-mips32r2"
  1996. .IP "\fB\-mips32r3\fR" 4
  1997. .IX Item "-mips32r3"
  1998. .IP "\fB\-mips32r5\fR" 4
  1999. .IX Item "-mips32r5"
  2000. .IP "\fB\-mips32r6\fR" 4
  2001. .IX Item "-mips32r6"
  2002. .IP "\fB\-mips64\fR" 4
  2003. .IX Item "-mips64"
  2004. .IP "\fB\-mips64r2\fR" 4
  2005. .IX Item "-mips64r2"
  2006. .IP "\fB\-mips64r3\fR" 4
  2007. .IX Item "-mips64r3"
  2008. .IP "\fB\-mips64r5\fR" 4
  2009. .IX Item "-mips64r5"
  2010. .IP "\fB\-mips64r6\fR" 4
  2011. .IX Item "-mips64r6"
  2012. .PD
  2013. Generate code for a particular \s-1MIPS\s0 Instruction Set Architecture level.
  2014. \&\fB\-mips1\fR is an alias for \fB\-march=r3000\fR, \fB\-mips2\fR is an
  2015. alias for \fB\-march=r6000\fR, \fB\-mips3\fR is an alias for
  2016. \&\fB\-march=r4000\fR and \fB\-mips4\fR is an alias for \fB\-march=r8000\fR.
  2017. \&\fB\-mips5\fR, \fB\-mips32\fR, \fB\-mips32r2\fR, \fB\-mips32r3\fR,
  2018. \&\fB\-mips32r5\fR, \fB\-mips32r6\fR, \fB\-mips64\fR, \fB\-mips64r2\fR,
  2019. \&\fB\-mips64r3\fR, \fB\-mips64r5\fR, and \fB\-mips64r6\fR correspond to generic
  2020. \&\s-1MIPS V, MIPS32, MIPS32\s0 Release 2, \s-1MIPS32\s0 Release 3, \s-1MIPS32\s0 Release 5, \s-1MIPS32\s0
  2021. Release 6, \s-1MIPS64, MIPS64\s0 Release 2, \s-1MIPS64\s0 Release 3, \s-1MIPS64\s0 Release 5, and
  2022. \&\s-1MIPS64\s0 Release 6 \s-1ISA\s0 processors, respectively.
  2023. .IP "\fB\-march=\fR\fIcpu\fR" 4
  2024. .IX Item "-march=cpu"
  2025. Generate code for a particular \s-1MIPS CPU.\s0
  2026. .IP "\fB\-mtune=\fR\fIcpu\fR" 4
  2027. .IX Item "-mtune=cpu"
  2028. Schedule and tune for a particular \s-1MIPS CPU.\s0
  2029. .IP "\fB\-mfix7000\fR" 4
  2030. .IX Item "-mfix7000"
  2031. .PD 0
  2032. .IP "\fB\-mno\-fix7000\fR" 4
  2033. .IX Item "-mno-fix7000"
  2034. .PD
  2035. Cause nops to be inserted if the read of the destination register
  2036. of an mfhi or mflo instruction occurs in the following two instructions.
  2037. .IP "\fB\-mfix\-rm7000\fR" 4
  2038. .IX Item "-mfix-rm7000"
  2039. .PD 0
  2040. .IP "\fB\-mno\-fix\-rm7000\fR" 4
  2041. .IX Item "-mno-fix-rm7000"
  2042. .PD
  2043. Cause nops to be inserted if a dmult or dmultu instruction is
  2044. followed by a load instruction.
  2045. .IP "\fB\-mfix\-r5900\fR" 4
  2046. .IX Item "-mfix-r5900"
  2047. .PD 0
  2048. .IP "\fB\-mno\-fix\-r5900\fR" 4
  2049. .IX Item "-mno-fix-r5900"
  2050. .PD
  2051. Do not attempt to schedule the preceding instruction into the delay slot
  2052. of a branch instruction placed at the end of a short loop of six
  2053. instructions or fewer and always schedule a \f(CW\*(C`nop\*(C'\fR instruction there
  2054. instead.  The short loop bug under certain conditions causes loops to
  2055. execute only once or twice, due to a hardware bug in the R5900 chip.
  2056. .IP "\fB\-mdebug\fR" 4
  2057. .IX Item "-mdebug"
  2058. .PD 0
  2059. .IP "\fB\-no\-mdebug\fR" 4
  2060. .IX Item "-no-mdebug"
  2061. .PD
  2062. Cause stabs-style debugging output to go into an ECOFF-style .mdebug
  2063. section instead of the standard \s-1ELF\s0 .stabs sections.
  2064. .IP "\fB\-mpdr\fR" 4
  2065. .IX Item "-mpdr"
  2066. .PD 0
  2067. .IP "\fB\-mno\-pdr\fR" 4
  2068. .IX Item "-mno-pdr"
  2069. .PD
  2070. Control generation of \f(CW\*(C`.pdr\*(C'\fR sections.
  2071. .IP "\fB\-mgp32\fR" 4
  2072. .IX Item "-mgp32"
  2073. .PD 0
  2074. .IP "\fB\-mfp32\fR" 4
  2075. .IX Item "-mfp32"
  2076. .PD
  2077. The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but these
  2078. flags force a certain group of registers to be treated as 32 bits wide at
  2079. all times.  \fB\-mgp32\fR controls the size of general-purpose registers
  2080. and \fB\-mfp32\fR controls the size of floating-point registers.
  2081. .IP "\fB\-mgp64\fR" 4
  2082. .IX Item "-mgp64"
  2083. .PD 0
  2084. .IP "\fB\-mfp64\fR" 4
  2085. .IX Item "-mfp64"
  2086. .PD
  2087. The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but these
  2088. flags force a certain group of registers to be treated as 64 bits wide at
  2089. all times.  \fB\-mgp64\fR controls the size of general-purpose registers
  2090. and \fB\-mfp64\fR controls the size of floating-point registers.
  2091. .IP "\fB\-mfpxx\fR" 4
  2092. .IX Item "-mfpxx"
  2093. The register sizes are normally inferred from the \s-1ISA\s0 and \s-1ABI,\s0 but using
  2094. this flag in combination with \fB\-mabi=32\fR enables an \s-1ABI\s0 variant
  2095. which will operate correctly with floating-point registers which are
  2096. 32 or 64 bits wide.
  2097. .IP "\fB\-modd\-spreg\fR" 4
  2098. .IX Item "-modd-spreg"
  2099. .PD 0
  2100. .IP "\fB\-mno\-odd\-spreg\fR" 4
  2101. .IX Item "-mno-odd-spreg"
  2102. .PD
  2103. Enable use of floating-point operations on odd-numbered single-precision
  2104. registers when supported by the \s-1ISA.\s0  \fB\-mfpxx\fR implies
  2105. \&\fB\-mno\-odd\-spreg\fR, otherwise the default is \fB\-modd\-spreg\fR.
  2106. .IP "\fB\-mips16\fR" 4
  2107. .IX Item "-mips16"
  2108. .PD 0
  2109. .IP "\fB\-no\-mips16\fR" 4
  2110. .IX Item "-no-mips16"
  2111. .PD
  2112. Generate code for the \s-1MIPS 16\s0 processor.  This is equivalent to putting
  2113. \&\f(CW\*(C`.module mips16\*(C'\fR at the start of the assembly file.  \fB\-no\-mips16\fR
  2114. turns off this option.
  2115. .IP "\fB\-mmips16e2\fR" 4
  2116. .IX Item "-mmips16e2"
  2117. .PD 0
  2118. .IP "\fB\-mno\-mips16e2\fR" 4
  2119. .IX Item "-mno-mips16e2"
  2120. .PD
  2121. Enable the use of MIPS16e2 instructions in \s-1MIPS16\s0 mode.  This is equivalent
  2122. to putting \f(CW\*(C`.module mips16e2\*(C'\fR at the start of the assembly file.
  2123. \&\fB\-mno\-mips16e2\fR turns off this option.
  2124. .IP "\fB\-mmicromips\fR" 4
  2125. .IX Item "-mmicromips"
  2126. .PD 0
  2127. .IP "\fB\-mno\-micromips\fR" 4
  2128. .IX Item "-mno-micromips"
  2129. .PD
  2130. Generate code for the microMIPS processor.  This is equivalent to putting
  2131. \&\f(CW\*(C`.module micromips\*(C'\fR at the start of the assembly file.
  2132. \&\fB\-mno\-micromips\fR turns off this option.  This is equivalent to putting
  2133. \&\f(CW\*(C`.module nomicromips\*(C'\fR at the start of the assembly file.
  2134. .IP "\fB\-msmartmips\fR" 4
  2135. .IX Item "-msmartmips"
  2136. .PD 0
  2137. .IP "\fB\-mno\-smartmips\fR" 4
  2138. .IX Item "-mno-smartmips"
  2139. .PD
  2140. Enables the SmartMIPS extension to the \s-1MIPS32\s0 instruction set.  This is
  2141. equivalent to putting \f(CW\*(C`.module smartmips\*(C'\fR at the start of the assembly
  2142. file.  \fB\-mno\-smartmips\fR turns off this option.
  2143. .IP "\fB\-mips3d\fR" 4
  2144. .IX Item "-mips3d"
  2145. .PD 0
  2146. .IP "\fB\-no\-mips3d\fR" 4
  2147. .IX Item "-no-mips3d"
  2148. .PD
  2149. Generate code for the \s-1MIPS\-3D\s0 Application Specific Extension.
  2150. This tells the assembler to accept \s-1MIPS\-3D\s0 instructions.
  2151. \&\fB\-no\-mips3d\fR turns off this option.
  2152. .IP "\fB\-mdmx\fR" 4
  2153. .IX Item "-mdmx"
  2154. .PD 0
  2155. .IP "\fB\-no\-mdmx\fR" 4
  2156. .IX Item "-no-mdmx"
  2157. .PD
  2158. Generate code for the \s-1MDMX\s0 Application Specific Extension.
  2159. This tells the assembler to accept \s-1MDMX\s0 instructions.
  2160. \&\fB\-no\-mdmx\fR turns off this option.
  2161. .IP "\fB\-mdsp\fR" 4
  2162. .IX Item "-mdsp"
  2163. .PD 0
  2164. .IP "\fB\-mno\-dsp\fR" 4
  2165. .IX Item "-mno-dsp"
  2166. .PD
  2167. Generate code for the \s-1DSP\s0 Release 1 Application Specific Extension.
  2168. This tells the assembler to accept \s-1DSP\s0 Release 1 instructions.
  2169. \&\fB\-mno\-dsp\fR turns off this option.
  2170. .IP "\fB\-mdspr2\fR" 4
  2171. .IX Item "-mdspr2"
  2172. .PD 0
  2173. .IP "\fB\-mno\-dspr2\fR" 4
  2174. .IX Item "-mno-dspr2"
  2175. .PD
  2176. Generate code for the \s-1DSP\s0 Release 2 Application Specific Extension.
  2177. This option implies \fB\-mdsp\fR.
  2178. This tells the assembler to accept \s-1DSP\s0 Release 2 instructions.
  2179. \&\fB\-mno\-dspr2\fR turns off this option.
  2180. .IP "\fB\-mdspr3\fR" 4
  2181. .IX Item "-mdspr3"
  2182. .PD 0
  2183. .IP "\fB\-mno\-dspr3\fR" 4
  2184. .IX Item "-mno-dspr3"
  2185. .PD
  2186. Generate code for the \s-1DSP\s0 Release 3 Application Specific Extension.
  2187. This option implies \fB\-mdsp\fR and \fB\-mdspr2\fR.
  2188. This tells the assembler to accept \s-1DSP\s0 Release 3 instructions.
  2189. \&\fB\-mno\-dspr3\fR turns off this option.
  2190. .IP "\fB\-mmsa\fR" 4
  2191. .IX Item "-mmsa"
  2192. .PD 0
  2193. .IP "\fB\-mno\-msa\fR" 4
  2194. .IX Item "-mno-msa"
  2195. .PD
  2196. Generate code for the \s-1MIPS SIMD\s0 Architecture Extension.
  2197. This tells the assembler to accept \s-1MSA\s0 instructions.
  2198. \&\fB\-mno\-msa\fR turns off this option.
  2199. .IP "\fB\-mxpa\fR" 4
  2200. .IX Item "-mxpa"
  2201. .PD 0
  2202. .IP "\fB\-mno\-xpa\fR" 4
  2203. .IX Item "-mno-xpa"
  2204. .PD
  2205. Generate code for the \s-1MIPS\s0 eXtended Physical Address (\s-1XPA\s0) Extension.
  2206. This tells the assembler to accept \s-1XPA\s0 instructions.
  2207. \&\fB\-mno\-xpa\fR turns off this option.
  2208. .IP "\fB\-mmt\fR" 4
  2209. .IX Item "-mmt"
  2210. .PD 0
  2211. .IP "\fB\-mno\-mt\fR" 4
  2212. .IX Item "-mno-mt"
  2213. .PD
  2214. Generate code for the \s-1MT\s0 Application Specific Extension.
  2215. This tells the assembler to accept \s-1MT\s0 instructions.
  2216. \&\fB\-mno\-mt\fR turns off this option.
  2217. .IP "\fB\-mmcu\fR" 4
  2218. .IX Item "-mmcu"
  2219. .PD 0
  2220. .IP "\fB\-mno\-mcu\fR" 4
  2221. .IX Item "-mno-mcu"
  2222. .PD
  2223. Generate code for the \s-1MCU\s0 Application Specific Extension.
  2224. This tells the assembler to accept \s-1MCU\s0 instructions.
  2225. \&\fB\-mno\-mcu\fR turns off this option.
  2226. .IP "\fB\-mcrc\fR" 4
  2227. .IX Item "-mcrc"
  2228. .PD 0
  2229. .IP "\fB\-mno\-crc\fR" 4
  2230. .IX Item "-mno-crc"
  2231. .PD
  2232. Generate code for the \s-1MIPS\s0 cyclic redundancy check (\s-1CRC\s0) Application
  2233. Specific Extension.  This tells the assembler to accept \s-1CRC\s0 instructions.
  2234. \&\fB\-mno\-crc\fR turns off this option.
  2235. .IP "\fB\-mginv\fR" 4
  2236. .IX Item "-mginv"
  2237. .PD 0
  2238. .IP "\fB\-mno\-ginv\fR" 4
  2239. .IX Item "-mno-ginv"
  2240. .PD
  2241. Generate code for the Global INValidate (\s-1GINV\s0) Application Specific
  2242. Extension.  This tells the assembler to accept \s-1GINV\s0 instructions.
  2243. \&\fB\-mno\-ginv\fR turns off this option.
  2244. .IP "\fB\-mloongson\-mmi\fR" 4
  2245. .IX Item "-mloongson-mmi"
  2246. .PD 0
  2247. .IP "\fB\-mno\-loongson\-mmi\fR" 4
  2248. .IX Item "-mno-loongson-mmi"
  2249. .PD
  2250. Generate code for the Loongson MultiMedia extensions Instructions (\s-1MMI\s0)
  2251. Application Specific Extension.  This tells the assembler to accept \s-1MMI\s0
  2252. instructions.
  2253. \&\fB\-mno\-loongson\-mmi\fR turns off this option.
  2254. .IP "\fB\-mloongson\-cam\fR" 4
  2255. .IX Item "-mloongson-cam"
  2256. .PD 0
  2257. .IP "\fB\-mno\-loongson\-cam\fR" 4
  2258. .IX Item "-mno-loongson-cam"
  2259. .PD
  2260. Generate code for the Loongson Content Address Memory (\s-1CAM\s0) instructions.
  2261. This tells the assembler to accept Loongson \s-1CAM\s0 instructions.
  2262. \&\fB\-mno\-loongson\-cam\fR turns off this option.
  2263. .IP "\fB\-mloongson\-ext\fR" 4
  2264. .IX Item "-mloongson-ext"
  2265. .PD 0
  2266. .IP "\fB\-mno\-loongson\-ext\fR" 4
  2267. .IX Item "-mno-loongson-ext"
  2268. .PD
  2269. Generate code for the Loongson EXTensions (\s-1EXT\s0) instructions.
  2270. This tells the assembler to accept Loongson \s-1EXT\s0 instructions.
  2271. \&\fB\-mno\-loongson\-ext\fR turns off this option.
  2272. .IP "\fB\-mloongson\-ext2\fR" 4
  2273. .IX Item "-mloongson-ext2"
  2274. .PD 0
  2275. .IP "\fB\-mno\-loongson\-ext2\fR" 4
  2276. .IX Item "-mno-loongson-ext2"
  2277. .PD
  2278. Generate code for the Loongson EXTensions R2 (\s-1EXT2\s0) instructions.
  2279. This option implies \fB\-mloongson\-ext\fR.
  2280. This tells the assembler to accept Loongson \s-1EXT2\s0 instructions.
  2281. \&\fB\-mno\-loongson\-ext2\fR turns off this option.
  2282. .IP "\fB\-minsn32\fR" 4
  2283. .IX Item "-minsn32"
  2284. .PD 0
  2285. .IP "\fB\-mno\-insn32\fR" 4
  2286. .IX Item "-mno-insn32"
  2287. .PD
  2288. Only use 32\-bit instruction encodings when generating code for the
  2289. microMIPS processor.  This option inhibits the use of any 16\-bit
  2290. instructions.  This is equivalent to putting \f(CW\*(C`.set insn32\*(C'\fR at
  2291. the start of the assembly file.  \fB\-mno\-insn32\fR turns off this
  2292. option.  This is equivalent to putting \f(CW\*(C`.set noinsn32\*(C'\fR at the
  2293. start of the assembly file.  By default \fB\-mno\-insn32\fR is
  2294. selected, allowing all instructions to be used.
  2295. .IP "\fB\-\-construct\-floats\fR" 4
  2296. .IX Item "--construct-floats"
  2297. .PD 0
  2298. .IP "\fB\-\-no\-construct\-floats\fR" 4
  2299. .IX Item "--no-construct-floats"
  2300. .PD
  2301. The \fB\-\-no\-construct\-floats\fR option disables the construction of
  2302. double width floating point constants by loading the two halves of the
  2303. value into the two single width floating point registers that make up
  2304. the double width register.  By default \fB\-\-construct\-floats\fR is
  2305. selected, allowing construction of these floating point constants.
  2306. .IP "\fB\-\-relax\-branch\fR" 4
  2307. .IX Item "--relax-branch"
  2308. .PD 0
  2309. .IP "\fB\-\-no\-relax\-branch\fR" 4
  2310. .IX Item "--no-relax-branch"
  2311. .PD
  2312. The \fB\-\-relax\-branch\fR option enables the relaxation of out-of-range
  2313. branches.  By default \fB\-\-no\-relax\-branch\fR is selected, causing any
  2314. out-of-range branches to produce an error.
  2315. .IP "\fB\-mignore\-branch\-isa\fR" 4
  2316. .IX Item "-mignore-branch-isa"
  2317. .PD 0
  2318. .IP "\fB\-mno\-ignore\-branch\-isa\fR" 4
  2319. .IX Item "-mno-ignore-branch-isa"
  2320. .PD
  2321. Ignore branch checks for invalid transitions between \s-1ISA\s0 modes.  The
  2322. semantics of branches does not provide for an \s-1ISA\s0 mode switch, so in
  2323. most cases the \s-1ISA\s0 mode a branch has been encoded for has to be the
  2324. same as the \s-1ISA\s0 mode of the branch's target label.  Therefore \s-1GAS\s0 has
  2325. checks implemented that verify in branch assembly that the two \s-1ISA\s0
  2326. modes match.  \fB\-mignore\-branch\-isa\fR disables these checks.  By
  2327. default \fB\-mno\-ignore\-branch\-isa\fR is selected, causing any invalid
  2328. branch requiring a transition between \s-1ISA\s0 modes to produce an error.
  2329. .IP "\fB\-mnan=\fR\fIencoding\fR" 4
  2330. .IX Item "-mnan=encoding"
  2331. Select between the \s-1IEEE 754\-2008\s0 (\fB\-mnan=2008\fR) or the legacy
  2332. (\fB\-mnan=legacy\fR) NaN encoding format.  The latter is the default.
  2333. .IP "\fB\-\-emulation=\fR\fIname\fR" 4
  2334. .IX Item "--emulation=name"
  2335. This option was formerly used to switch between \s-1ELF\s0 and \s-1ECOFF\s0 output
  2336. on targets like \s-1IRIX 5\s0 that supported both.  \s-1MIPS ECOFF\s0 support was
  2337. removed in \s-1GAS 2.24,\s0 so the option now serves little purpose.
  2338. It is retained for backwards compatibility.
  2339. .Sp
  2340. The available configuration names are: \fBmipself\fR, \fBmipslelf\fR and
  2341. \&\fBmipsbelf\fR.  Choosing \fBmipself\fR now has no effect, since the output
  2342. is always \s-1ELF.\s0  \fBmipslelf\fR and \fBmipsbelf\fR select little\- and
  2343. big-endian output respectively, but \fB\-EL\fR and \fB\-EB\fR are now the
  2344. preferred options instead.
  2345. .IP "\fB\-nocpp\fR" 4
  2346. .IX Item "-nocpp"
  2347. \&\fBas\fR ignores this option.  It is accepted for compatibility with
  2348. the native tools.
  2349. .IP "\fB\-\-trap\fR" 4
  2350. .IX Item "--trap"
  2351. .PD 0
  2352. .IP "\fB\-\-no\-trap\fR" 4
  2353. .IX Item "--no-trap"
  2354. .IP "\fB\-\-break\fR" 4
  2355. .IX Item "--break"
  2356. .IP "\fB\-\-no\-break\fR" 4
  2357. .IX Item "--no-break"
  2358. .PD
  2359. Control how to deal with multiplication overflow and division by zero.
  2360. \&\fB\-\-trap\fR or \fB\-\-no\-break\fR (which are synonyms) take a trap exception
  2361. (and only work for Instruction Set Architecture level 2 and higher);
  2362. \&\fB\-\-break\fR or \fB\-\-no\-trap\fR (also synonyms, and the default) take a
  2363. break exception.
  2364. .IP "\fB\-n\fR" 4
  2365. .IX Item "-n"
  2366. When this option is used, \fBas\fR will issue a warning every
  2367. time it generates a nop instruction from a macro.
  2368. .PP
  2369. The following options are available when as is configured for a
  2370. LoongArch processor.
  2371. .IP "\fB\-fpic\fR" 4
  2372. .IX Item "-fpic"
  2373. .PD 0
  2374. .IP "\fB\-fPIC\fR" 4
  2375. .IX Item "-fPIC"
  2376. .PD
  2377. Generate position-independent code
  2378. .IP "\fB\-fno\-pic\fR" 4
  2379. .IX Item "-fno-pic"
  2380. Don't generate position-independent code (default)
  2381. .PP
  2382. The following options are available when as is configured for a
  2383. Meta processor.
  2384. .ie n .IP """\-mcpu=metac11""" 4
  2385. .el .IP "\f(CW\-mcpu=metac11\fR" 4
  2386. .IX Item "-mcpu=metac11"
  2387. Generate code for Meta 1.1.
  2388. .ie n .IP """\-mcpu=metac12""" 4
  2389. .el .IP "\f(CW\-mcpu=metac12\fR" 4
  2390. .IX Item "-mcpu=metac12"
  2391. Generate code for Meta 1.2.
  2392. .ie n .IP """\-mcpu=metac21""" 4
  2393. .el .IP "\f(CW\-mcpu=metac21\fR" 4
  2394. .IX Item "-mcpu=metac21"
  2395. Generate code for Meta 2.1.
  2396. .ie n .IP """\-mfpu=metac21""" 4
  2397. .el .IP "\f(CW\-mfpu=metac21\fR" 4
  2398. .IX Item "-mfpu=metac21"
  2399. Allow code to use \s-1FPU\s0 hardware of Meta 2.1.
  2400. .PP
  2401. See the info pages for documentation of the MMIX-specific options.
  2402. .PP
  2403. The following options are available when as is configured for a
  2404. \&\s-1NDS32\s0 processor.
  2405. .ie n .IP """\-O1""" 4
  2406. .el .IP "\f(CW\-O1\fR" 4
  2407. .IX Item "-O1"
  2408. Optimize for performance.
  2409. .ie n .IP """\-Os""" 4
  2410. .el .IP "\f(CW\-Os\fR" 4
  2411. .IX Item "-Os"
  2412. Optimize for space.
  2413. .ie n .IP """\-EL""" 4
  2414. .el .IP "\f(CW\-EL\fR" 4
  2415. .IX Item "-EL"
  2416. Produce little endian data output.
  2417. .ie n .IP """\-EB""" 4
  2418. .el .IP "\f(CW\-EB\fR" 4
  2419. .IX Item "-EB"
  2420. Produce little endian data output.
  2421. .ie n .IP """\-mpic""" 4
  2422. .el .IP "\f(CW\-mpic\fR" 4
  2423. .IX Item "-mpic"
  2424. Generate \s-1PIC.\s0
  2425. .ie n .IP """\-mno\-fp\-as\-gp\-relax""" 4
  2426. .el .IP "\f(CW\-mno\-fp\-as\-gp\-relax\fR" 4
  2427. .IX Item "-mno-fp-as-gp-relax"
  2428. Suppress fp-as-gp relaxation for this file.
  2429. .ie n .IP """\-mb2bb\-relax""" 4
  2430. .el .IP "\f(CW\-mb2bb\-relax\fR" 4
  2431. .IX Item "-mb2bb-relax"
  2432. Back-to-back branch optimization.
  2433. .ie n .IP """\-mno\-all\-relax""" 4
  2434. .el .IP "\f(CW\-mno\-all\-relax\fR" 4
  2435. .IX Item "-mno-all-relax"
  2436. Suppress all relaxation for this file.
  2437. .ie n .IP """\-march=<arch name>""" 4
  2438. .el .IP "\f(CW\-march=<arch name>\fR" 4
  2439. .IX Item "-march=<arch name>"
  2440. Assemble for architecture <arch name> which could be v3, v3j, v3m, v3f,
  2441. v3s, v2, v2j, v2f, v2s.
  2442. .ie n .IP """\-mbaseline=<baseline>""" 4
  2443. .el .IP "\f(CW\-mbaseline=<baseline>\fR" 4
  2444. .IX Item "-mbaseline=<baseline>"
  2445. Assemble for baseline <baseline> which could be v2, v3, v3m.
  2446. .ie n .IP """\-mfpu\-freg=\fIFREG\fP""" 4
  2447. .el .IP "\f(CW\-mfpu\-freg=\f(CIFREG\f(CW\fR" 4
  2448. .IX Item "-mfpu-freg=FREG"
  2449. Specify a \s-1FPU\s0 configuration.
  2450. .RS 4
  2451. .ie n .IP """0      8 SP /  4 DP registers""" 4
  2452. .el .IP "\f(CW0      8 SP /  4 DP registers\fR" 4
  2453. .IX Item "0 8 SP / 4 DP registers"
  2454. .PD 0
  2455. .ie n .IP """1     16 SP /  8 DP registers""" 4
  2456. .el .IP "\f(CW1     16 SP /  8 DP registers\fR" 4
  2457. .IX Item "1 16 SP / 8 DP registers"
  2458. .ie n .IP """2     32 SP / 16 DP registers""" 4
  2459. .el .IP "\f(CW2     32 SP / 16 DP registers\fR" 4
  2460. .IX Item "2 32 SP / 16 DP registers"
  2461. .ie n .IP """3     32 SP / 32 DP registers""" 4
  2462. .el .IP "\f(CW3     32 SP / 32 DP registers\fR" 4
  2463. .IX Item "3 32 SP / 32 DP registers"
  2464. .RE
  2465. .RS 4
  2466. .RE
  2467. .ie n .IP """\-mabi=\fIabi\fP""" 4
  2468. .el .IP "\f(CW\-mabi=\f(CIabi\f(CW\fR" 4
  2469. .IX Item "-mabi=abi"
  2470. .PD
  2471. Specify a abi version <abi> could be v1, v2, v2fp, v2fpp.
  2472. .ie n .IP """\-m[no\-]mac""" 4
  2473. .el .IP "\f(CW\-m[no\-]mac\fR" 4
  2474. .IX Item "-m[no-]mac"
  2475. Enable/Disable Multiply instructions support.
  2476. .ie n .IP """\-m[no\-]div""" 4
  2477. .el .IP "\f(CW\-m[no\-]div\fR" 4
  2478. .IX Item "-m[no-]div"
  2479. Enable/Disable Divide instructions support.
  2480. .ie n .IP """\-m[no\-]16bit\-ext""" 4
  2481. .el .IP "\f(CW\-m[no\-]16bit\-ext\fR" 4
  2482. .IX Item "-m[no-]16bit-ext"
  2483. Enable/Disable 16\-bit extension
  2484. .ie n .IP """\-m[no\-]dx\-regs""" 4
  2485. .el .IP "\f(CW\-m[no\-]dx\-regs\fR" 4
  2486. .IX Item "-m[no-]dx-regs"
  2487. Enable/Disable d0/d1 registers
  2488. .ie n .IP """\-m[no\-]perf\-ext""" 4
  2489. .el .IP "\f(CW\-m[no\-]perf\-ext\fR" 4
  2490. .IX Item "-m[no-]perf-ext"
  2491. Enable/Disable Performance extension
  2492. .ie n .IP """\-m[no\-]perf2\-ext""" 4
  2493. .el .IP "\f(CW\-m[no\-]perf2\-ext\fR" 4
  2494. .IX Item "-m[no-]perf2-ext"
  2495. Enable/Disable Performance extension 2
  2496. .ie n .IP """\-m[no\-]string\-ext""" 4
  2497. .el .IP "\f(CW\-m[no\-]string\-ext\fR" 4
  2498. .IX Item "-m[no-]string-ext"
  2499. Enable/Disable String extension
  2500. .ie n .IP """\-m[no\-]reduced\-regs""" 4
  2501. .el .IP "\f(CW\-m[no\-]reduced\-regs\fR" 4
  2502. .IX Item "-m[no-]reduced-regs"
  2503. Enable/Disable Reduced Register configuration (\s-1GPR16\s0) option
  2504. .ie n .IP """\-m[no\-]audio\-isa\-ext""" 4
  2505. .el .IP "\f(CW\-m[no\-]audio\-isa\-ext\fR" 4
  2506. .IX Item "-m[no-]audio-isa-ext"
  2507. Enable/Disable \s-1AUDIO ISA\s0 extension
  2508. .ie n .IP """\-m[no\-]fpu\-sp\-ext""" 4
  2509. .el .IP "\f(CW\-m[no\-]fpu\-sp\-ext\fR" 4
  2510. .IX Item "-m[no-]fpu-sp-ext"
  2511. Enable/Disable \s-1FPU SP\s0 extension
  2512. .ie n .IP """\-m[no\-]fpu\-dp\-ext""" 4
  2513. .el .IP "\f(CW\-m[no\-]fpu\-dp\-ext\fR" 4
  2514. .IX Item "-m[no-]fpu-dp-ext"
  2515. Enable/Disable \s-1FPU DP\s0 extension
  2516. .ie n .IP """\-m[no\-]fpu\-fma""" 4
  2517. .el .IP "\f(CW\-m[no\-]fpu\-fma\fR" 4
  2518. .IX Item "-m[no-]fpu-fma"
  2519. Enable/Disable \s-1FPU\s0 fused-multiply-add instructions
  2520. .ie n .IP """\-mall\-ext""" 4
  2521. .el .IP "\f(CW\-mall\-ext\fR" 4
  2522. .IX Item "-mall-ext"
  2523. Turn on all extensions and instructions support
  2524. .PP
  2525. The following options are available when as is configured for a
  2526. PowerPC processor.
  2527. .IP "\fB\-a32\fR" 4
  2528. .IX Item "-a32"
  2529. Generate \s-1ELF32\s0 or \s-1XCOFF32.\s0
  2530. .IP "\fB\-a64\fR" 4
  2531. .IX Item "-a64"
  2532. Generate \s-1ELF64\s0 or \s-1XCOFF64.\s0
  2533. .IP "\fB\-K \s-1PIC\s0\fR" 4
  2534. .IX Item "-K PIC"
  2535. Set \s-1EF_PPC_RELOCATABLE_LIB\s0 in \s-1ELF\s0 flags.
  2536. .IP "\fB\-mpwrx | \-mpwr2\fR" 4
  2537. .IX Item "-mpwrx | -mpwr2"
  2538. Generate code for \s-1POWER/2\s0 (\s-1RIOS2\s0).
  2539. .IP "\fB\-mpwr\fR" 4
  2540. .IX Item "-mpwr"
  2541. Generate code for \s-1POWER\s0 (\s-1RIOS1\s0)
  2542. .IP "\fB\-m601\fR" 4
  2543. .IX Item "-m601"
  2544. Generate code for PowerPC 601.
  2545. .IP "\fB\-mppc, \-mppc32, \-m603, \-m604\fR" 4
  2546. .IX Item "-mppc, -mppc32, -m603, -m604"
  2547. Generate code for PowerPC 603/604.
  2548. .IP "\fB\-m403, \-m405\fR" 4
  2549. .IX Item "-m403, -m405"
  2550. Generate code for PowerPC 403/405.
  2551. .IP "\fB\-m440\fR" 4
  2552. .IX Item "-m440"
  2553. Generate code for PowerPC 440.  BookE and some 405 instructions.
  2554. .IP "\fB\-m464\fR" 4
  2555. .IX Item "-m464"
  2556. Generate code for PowerPC 464.
  2557. .IP "\fB\-m476\fR" 4
  2558. .IX Item "-m476"
  2559. Generate code for PowerPC 476.
  2560. .IP "\fB\-m7400, \-m7410, \-m7450, \-m7455\fR" 4
  2561. .IX Item "-m7400, -m7410, -m7450, -m7455"
  2562. Generate code for PowerPC 7400/7410/7450/7455.
  2563. .IP "\fB\-m750cl, \-mgekko, \-mbroadway\fR" 4
  2564. .IX Item "-m750cl, -mgekko, -mbroadway"
  2565. Generate code for PowerPC 750CL/Gekko/Broadway.
  2566. .IP "\fB\-m821, \-m850, \-m860\fR" 4
  2567. .IX Item "-m821, -m850, -m860"
  2568. Generate code for PowerPC 821/850/860.
  2569. .IP "\fB\-mppc64, \-m620\fR" 4
  2570. .IX Item "-mppc64, -m620"
  2571. Generate code for PowerPC 620/625/630.
  2572. .IP "\fB\-me500, \-me500x2\fR" 4
  2573. .IX Item "-me500, -me500x2"
  2574. Generate code for Motorola e500 core complex.
  2575. .IP "\fB\-me500mc\fR" 4
  2576. .IX Item "-me500mc"
  2577. Generate code for Freescale e500mc core complex.
  2578. .IP "\fB\-me500mc64\fR" 4
  2579. .IX Item "-me500mc64"
  2580. Generate code for Freescale e500mc64 core complex.
  2581. .IP "\fB\-me5500\fR" 4
  2582. .IX Item "-me5500"
  2583. Generate code for Freescale e5500 core complex.
  2584. .IP "\fB\-me6500\fR" 4
  2585. .IX Item "-me6500"
  2586. Generate code for Freescale e6500 core complex.
  2587. .IP "\fB\-mspe\fR" 4
  2588. .IX Item "-mspe"
  2589. Generate code for Motorola \s-1SPE\s0 instructions.
  2590. .IP "\fB\-mspe2\fR" 4
  2591. .IX Item "-mspe2"
  2592. Generate code for Freescale \s-1SPE2\s0 instructions.
  2593. .IP "\fB\-mtitan\fR" 4
  2594. .IX Item "-mtitan"
  2595. Generate code for AppliedMicro Titan core complex.
  2596. .IP "\fB\-mppc64bridge\fR" 4
  2597. .IX Item "-mppc64bridge"
  2598. Generate code for PowerPC 64, including bridge insns.
  2599. .IP "\fB\-mbooke\fR" 4
  2600. .IX Item "-mbooke"
  2601. Generate code for 32\-bit BookE.
  2602. .IP "\fB\-ma2\fR" 4
  2603. .IX Item "-ma2"
  2604. Generate code for A2 architecture.
  2605. .IP "\fB\-me300\fR" 4
  2606. .IX Item "-me300"
  2607. Generate code for PowerPC e300 family.
  2608. .IP "\fB\-maltivec\fR" 4
  2609. .IX Item "-maltivec"
  2610. Generate code for processors with AltiVec instructions.
  2611. .IP "\fB\-mvle\fR" 4
  2612. .IX Item "-mvle"
  2613. Generate code for Freescale PowerPC \s-1VLE\s0 instructions.
  2614. .IP "\fB\-mvsx\fR" 4
  2615. .IX Item "-mvsx"
  2616. Generate code for processors with Vector-Scalar (\s-1VSX\s0) instructions.
  2617. .IP "\fB\-mhtm\fR" 4
  2618. .IX Item "-mhtm"
  2619. Generate code for processors with Hardware Transactional Memory instructions.
  2620. .IP "\fB\-mpower4, \-mpwr4\fR" 4
  2621. .IX Item "-mpower4, -mpwr4"
  2622. Generate code for Power4 architecture.
  2623. .IP "\fB\-mpower5, \-mpwr5, \-mpwr5x\fR" 4
  2624. .IX Item "-mpower5, -mpwr5, -mpwr5x"
  2625. Generate code for Power5 architecture.
  2626. .IP "\fB\-mpower6, \-mpwr6\fR" 4
  2627. .IX Item "-mpower6, -mpwr6"
  2628. Generate code for Power6 architecture.
  2629. .IP "\fB\-mpower7, \-mpwr7\fR" 4
  2630. .IX Item "-mpower7, -mpwr7"
  2631. Generate code for Power7 architecture.
  2632. .IP "\fB\-mpower8, \-mpwr8\fR" 4
  2633. .IX Item "-mpower8, -mpwr8"
  2634. Generate code for Power8 architecture.
  2635. .IP "\fB\-mpower9, \-mpwr9\fR" 4
  2636. .IX Item "-mpower9, -mpwr9"
  2637. Generate code for Power9 architecture.
  2638. .IP "\fB\-mpower10, \-mpwr10\fR" 4
  2639. .IX Item "-mpower10, -mpwr10"
  2640. Generate code for Power10 architecture.
  2641. .IP "\fB\-mcell\fR" 4
  2642. .IX Item "-mcell"
  2643. .PD 0
  2644. .IP "\fB\-mcell\fR" 4
  2645. .IX Item "-mcell"
  2646. .PD
  2647. Generate code for Cell Broadband Engine architecture.
  2648. .IP "\fB\-mcom\fR" 4
  2649. .IX Item "-mcom"
  2650. Generate code Power/PowerPC common instructions.
  2651. .IP "\fB\-many\fR" 4
  2652. .IX Item "-many"
  2653. Generate code for any architecture (\s-1PWR/PWRX/PPC\s0).
  2654. .IP "\fB\-mregnames\fR" 4
  2655. .IX Item "-mregnames"
  2656. Allow symbolic names for registers.
  2657. .IP "\fB\-mno\-regnames\fR" 4
  2658. .IX Item "-mno-regnames"
  2659. Do not allow symbolic names for registers.
  2660. .IP "\fB\-mrelocatable\fR" 4
  2661. .IX Item "-mrelocatable"
  2662. Support for \s-1GCC\s0's \-mrelocatable option.
  2663. .IP "\fB\-mrelocatable\-lib\fR" 4
  2664. .IX Item "-mrelocatable-lib"
  2665. Support for \s-1GCC\s0's \-mrelocatable\-lib option.
  2666. .IP "\fB\-memb\fR" 4
  2667. .IX Item "-memb"
  2668. Set \s-1PPC_EMB\s0 bit in \s-1ELF\s0 flags.
  2669. .IP "\fB\-mlittle, \-mlittle\-endian, \-le\fR" 4
  2670. .IX Item "-mlittle, -mlittle-endian, -le"
  2671. Generate code for a little endian machine.
  2672. .IP "\fB\-mbig, \-mbig\-endian, \-be\fR" 4
  2673. .IX Item "-mbig, -mbig-endian, -be"
  2674. Generate code for a big endian machine.
  2675. .IP "\fB\-msolaris\fR" 4
  2676. .IX Item "-msolaris"
  2677. Generate code for Solaris.
  2678. .IP "\fB\-mno\-solaris\fR" 4
  2679. .IX Item "-mno-solaris"
  2680. Do not generate code for Solaris.
  2681. .IP "\fB\-nops=\fR\fIcount\fR" 4
  2682. .IX Item "-nops=count"
  2683. If an alignment directive inserts more than \fIcount\fR nops, put a
  2684. branch at the beginning to skip execution of the nops.
  2685. .PP
  2686. The following options are available when as is configured for a
  2687. RISC-V processor.
  2688. .IP "\fB\-fpic\fR" 4
  2689. .IX Item "-fpic"
  2690. .PD 0
  2691. .IP "\fB\-fPIC\fR" 4
  2692. .IX Item "-fPIC"
  2693. .PD
  2694. Generate position-independent code
  2695. .IP "\fB\-fno\-pic\fR" 4
  2696. .IX Item "-fno-pic"
  2697. Don't generate position-independent code (default)
  2698. .IP "\fB\-march=ISA\fR" 4
  2699. .IX Item "-march=ISA"
  2700. Select the base isa, as specified by \s-1ISA.\s0  For example \-march=rv32ima.
  2701. If this option and the architecture attributes aren't set, then assembler
  2702. will check the default configure setting \-\-with\-arch=ISA.
  2703. .IP "\fB\-misa\-spec=ISAspec\fR" 4
  2704. .IX Item "-misa-spec=ISAspec"
  2705. Select the default isa spec version.  If the version of \s-1ISA\s0 isn't set
  2706. by \-march, then assembler helps to set the version according to
  2707. the default chosen spec.  If this option isn't set, then assembler will
  2708. check the default configure setting \-\-with\-isa\-spec=ISAspec.
  2709. .IP "\fB\-mpriv\-spec=PRIVspec\fR" 4
  2710. .IX Item "-mpriv-spec=PRIVspec"
  2711. Select the privileged spec version.  We can decide whether the \s-1CSR\s0 is valid or
  2712. not according to the chosen spec.  If this option and the privilege attributes
  2713. aren't set, then assembler will check the default configure setting
  2714. \&\-\-with\-priv\-spec=PRIVspec.
  2715. .IP "\fB\-mabi=ABI\fR" 4
  2716. .IX Item "-mabi=ABI"
  2717. Selects the \s-1ABI,\s0 which is either \*(L"ilp32\*(R" or \*(L"lp64\*(R", optionally followed
  2718. by \*(L"f\*(R", \*(L"d\*(R", or \*(L"q\*(R" to indicate single-precision, double-precision, or
  2719. quad-precision floating-point calling convention, or none to indicate
  2720. the soft-float calling convention.  Also, \*(L"ilp32\*(R" can optionally be followed
  2721. by \*(L"e\*(R" to indicate the \s-1RVE ABI,\s0 which is always soft-float.
  2722. .IP "\fB\-mrelax\fR" 4
  2723. .IX Item "-mrelax"
  2724. Take advantage of linker relaxations to reduce the number of instructions
  2725. required to materialize symbol addresses. (default)
  2726. .IP "\fB\-mno\-relax\fR" 4
  2727. .IX Item "-mno-relax"
  2728. Don't do linker relaxations.
  2729. .IP "\fB\-march\-attr\fR" 4
  2730. .IX Item "-march-attr"
  2731. Generate the default contents for the riscv elf attribute section if the
  2732. \&.attribute directives are not set.  This section is used to record the
  2733. information that a linker or runtime loader needs to check compatibility.
  2734. This information includes \s-1ISA\s0 string, stack alignment requirement, unaligned
  2735. memory accesses, and the major, minor and revision version of privileged
  2736. specification.
  2737. .IP "\fB\-mno\-arch\-attr\fR" 4
  2738. .IX Item "-mno-arch-attr"
  2739. Don't generate the default riscv elf attribute section if the .attribute
  2740. directives are not set.
  2741. .IP "\fB\-mcsr\-check\fR" 4
  2742. .IX Item "-mcsr-check"
  2743. Enable the \s-1CSR\s0 checking for the ISA-dependent \s-1CRS\s0 and the read-only \s-1CSR.\s0
  2744. The ISA-dependent \s-1CSR\s0 are only valid when the specific \s-1ISA\s0 is set.  The
  2745. read-only \s-1CSR\s0 can not be written by the \s-1CSR\s0 instructions.
  2746. .IP "\fB\-mno\-csr\-check\fR" 4
  2747. .IX Item "-mno-csr-check"
  2748. Don't do \s-1CSR\s0 checking.
  2749. .IP "\fB\-mlittle\-endian\fR" 4
  2750. .IX Item "-mlittle-endian"
  2751. Generate code for a little endian machine.
  2752. .IP "\fB\-mbig\-endian\fR" 4
  2753. .IX Item "-mbig-endian"
  2754. Generate code for a big endian machine.
  2755. .PP
  2756. See the info pages for documentation of the RX-specific options.
  2757. .PP
  2758. The following options are available when as is configured for the s390
  2759. processor family.
  2760. .IP "\fB\-m31\fR" 4
  2761. .IX Item "-m31"
  2762. .PD 0
  2763. .IP "\fB\-m64\fR" 4
  2764. .IX Item "-m64"
  2765. .PD
  2766. Select the word size, either 31/32 bits or 64 bits.
  2767. .IP "\fB\-mesa\fR" 4
  2768. .IX Item "-mesa"
  2769. .PD 0
  2770. .IP "\fB\-mzarch\fR" 4
  2771. .IX Item "-mzarch"
  2772. .PD
  2773. Select the architecture mode, either the Enterprise System
  2774. Architecture (esa) or the z/Architecture mode (zarch).
  2775. .IP "\fB\-march=\fR\fIprocessor\fR" 4
  2776. .IX Item "-march=processor"
  2777. Specify which s390 processor variant is the target, \fBg5\fR (or
  2778. \&\fBarch3\fR), \fBg6\fR, \fBz900\fR (or \fBarch5\fR), \fBz990\fR (or
  2779. \&\fBarch6\fR), \fBz9\-109\fR, \fBz9\-ec\fR (or \fBarch7\fR), \fBz10\fR (or
  2780. \&\fBarch8\fR), \fBz196\fR (or \fBarch9\fR), \fBzEC12\fR (or \fBarch10\fR),
  2781. \&\fBz13\fR (or \fBarch11\fR), \fBz14\fR (or \fBarch12\fR), \fBz15\fR
  2782. (or \fBarch13\fR), or \fBz16\fR (or \fBarch14\fR).
  2783. .IP "\fB\-mregnames\fR" 4
  2784. .IX Item "-mregnames"
  2785. .PD 0
  2786. .IP "\fB\-mno\-regnames\fR" 4
  2787. .IX Item "-mno-regnames"
  2788. .PD
  2789. Allow or disallow symbolic names for registers.
  2790. .IP "\fB\-mwarn\-areg\-zero\fR" 4
  2791. .IX Item "-mwarn-areg-zero"
  2792. Warn whenever the operand for a base or index register has been specified
  2793. but evaluates to zero.
  2794. .PP
  2795. The following options are available when as is configured for a
  2796. \&\s-1TMS320C6000\s0 processor.
  2797. .IP "\fB\-march=\fR\fIarch\fR" 4
  2798. .IX Item "-march=arch"
  2799. Enable (only) instructions from architecture \fIarch\fR.  By default,
  2800. all instructions are permitted.
  2801. .Sp
  2802. The following values of \fIarch\fR are accepted: \f(CW\*(C`c62x\*(C'\fR,
  2803. \&\f(CW\*(C`c64x\*(C'\fR, \f(CW\*(C`c64x+\*(C'\fR, \f(CW\*(C`c67x\*(C'\fR, \f(CW\*(C`c67x+\*(C'\fR, \f(CW\*(C`c674x\*(C'\fR.
  2804. .IP "\fB\-mdsbt\fR" 4
  2805. .IX Item "-mdsbt"
  2806. .PD 0
  2807. .IP "\fB\-mno\-dsbt\fR" 4
  2808. .IX Item "-mno-dsbt"
  2809. .PD
  2810. The \fB\-mdsbt\fR option causes the assembler to generate the
  2811. \&\f(CW\*(C`Tag_ABI_DSBT\*(C'\fR attribute with a value of 1, indicating that the
  2812. code is using \s-1DSBT\s0 addressing.  The \fB\-mno\-dsbt\fR option, the
  2813. default, causes the tag to have a value of 0, indicating that the code
  2814. does not use \s-1DSBT\s0 addressing.  The linker will emit a warning if
  2815. objects of different type (\s-1DSBT\s0 and non-DSBT) are linked together.
  2816. .IP "\fB\-mpid=no\fR" 4
  2817. .IX Item "-mpid=no"
  2818. .PD 0
  2819. .IP "\fB\-mpid=near\fR" 4
  2820. .IX Item "-mpid=near"
  2821. .IP "\fB\-mpid=far\fR" 4
  2822. .IX Item "-mpid=far"
  2823. .PD
  2824. The \fB\-mpid=\fR option causes the assembler to generate the
  2825. \&\f(CW\*(C`Tag_ABI_PID\*(C'\fR attribute with a value indicating the form of data
  2826. addressing used by the code.  \fB\-mpid=no\fR, the default,
  2827. indicates position-dependent data addressing, \fB\-mpid=near\fR
  2828. indicates position-independent addressing with \s-1GOT\s0 accesses using near
  2829. \&\s-1DP\s0 addressing, and \fB\-mpid=far\fR indicates position-independent
  2830. addressing with \s-1GOT\s0 accesses using far \s-1DP\s0 addressing.  The linker will
  2831. emit a warning if objects built with different settings of this option
  2832. are linked together.
  2833. .IP "\fB\-mpic\fR" 4
  2834. .IX Item "-mpic"
  2835. .PD 0
  2836. .IP "\fB\-mno\-pic\fR" 4
  2837. .IX Item "-mno-pic"
  2838. .PD
  2839. The \fB\-mpic\fR option causes the assembler to generate the
  2840. \&\f(CW\*(C`Tag_ABI_PIC\*(C'\fR attribute with a value of 1, indicating that the
  2841. code is using position-independent code addressing,  The
  2842. \&\f(CW\*(C`\-mno\-pic\*(C'\fR option, the default, causes the tag to have a value of
  2843. 0, indicating position-dependent code addressing.  The linker will
  2844. emit a warning if objects of different type (position-dependent and
  2845. position-independent) are linked together.
  2846. .IP "\fB\-mbig\-endian\fR" 4
  2847. .IX Item "-mbig-endian"
  2848. .PD 0
  2849. .IP "\fB\-mlittle\-endian\fR" 4
  2850. .IX Item "-mlittle-endian"
  2851. .PD
  2852. Generate code for the specified endianness.  The default is
  2853. little-endian.
  2854. .PP
  2855. The following options are available when as is configured for a TILE-Gx
  2856. processor.
  2857. .IP "\fB\-m32 | \-m64\fR" 4
  2858. .IX Item "-m32 | -m64"
  2859. Select the word size, either 32 bits or 64 bits.
  2860. .IP "\fB\-EB | \-EL\fR" 4
  2861. .IX Item "-EB | -EL"
  2862. Select the endianness, either big-endian (\-EB) or little-endian (\-EL).
  2863. .PP
  2864. The following option is available when as is configured for a Visium
  2865. processor.
  2866. .IP "\fB\-mtune=\fR\fIarch\fR" 4
  2867. .IX Item "-mtune=arch"
  2868. This option specifies the target architecture.  If an attempt is made to
  2869. assemble an instruction that will not execute on the target architecture,
  2870. the assembler will issue an error message.
  2871. .Sp
  2872. The following names are recognized:
  2873. \&\f(CW\*(C`mcm24\*(C'\fR
  2874. \&\f(CW\*(C`mcm\*(C'\fR
  2875. \&\f(CW\*(C`gr5\*(C'\fR
  2876. \&\f(CW\*(C`gr6\*(C'\fR
  2877. .PP
  2878. The following options are available when as is configured for an
  2879. Xtensa processor.
  2880. .IP "\fB\-\-text\-section\-literals | \-\-no\-text\-section\-literals\fR" 4
  2881. .IX Item "--text-section-literals | --no-text-section-literals"
  2882. Control the treatment of literal pools.  The default is
  2883. \&\fB\-\-no\-text\-section\-literals\fR, which places literals in
  2884. separate sections in the output file.  This allows the literal pool to be
  2885. placed in a data \s-1RAM/ROM.\s0  With \fB\-\-text\-section\-literals\fR, the
  2886. literals are interspersed in the text section in order to keep them as
  2887. close as possible to their references.  This may be necessary for large
  2888. assembly files, where the literals would otherwise be out of range of the
  2889. \&\f(CW\*(C`L32R\*(C'\fR instructions in the text section.  Literals are grouped into
  2890. pools following \f(CW\*(C`.literal_position\*(C'\fR directives or preceding
  2891. \&\f(CW\*(C`ENTRY\*(C'\fR instructions.  These options only affect literals referenced
  2892. via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals for absolute mode
  2893. \&\f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
  2894. .IP "\fB\-\-auto\-litpools | \-\-no\-auto\-litpools\fR" 4
  2895. .IX Item "--auto-litpools | --no-auto-litpools"
  2896. Control the treatment of literal pools.  The default is
  2897. \&\fB\-\-no\-auto\-litpools\fR, which in the absence of
  2898. \&\fB\-\-text\-section\-literals\fR places literals in separate sections
  2899. in the output file.  This allows the literal pool to be placed in a data
  2900. \&\s-1RAM/ROM.\s0  With \fB\-\-auto\-litpools\fR, the literals are interspersed
  2901. in the text section in order to keep them as close as possible to their
  2902. references, explicit \f(CW\*(C`.literal_position\*(C'\fR directives are not
  2903. required.  This may be necessary for very large functions, where single
  2904. literal pool at the beginning of the function may not be reachable by
  2905. \&\f(CW\*(C`L32R\*(C'\fR instructions at the end.  These options only affect
  2906. literals referenced via PC-relative \f(CW\*(C`L32R\*(C'\fR instructions; literals
  2907. for absolute mode \f(CW\*(C`L32R\*(C'\fR instructions are handled separately.
  2908. When used together with \fB\-\-text\-section\-literals\fR,
  2909. \&\fB\-\-auto\-litpools\fR takes precedence.
  2910. .IP "\fB\-\-absolute\-literals | \-\-no\-absolute\-literals\fR" 4
  2911. .IX Item "--absolute-literals | --no-absolute-literals"
  2912. Indicate to the assembler whether \f(CW\*(C`L32R\*(C'\fR instructions use absolute
  2913. or PC-relative addressing.  If the processor includes the absolute
  2914. addressing option, the default is to use absolute \f(CW\*(C`L32R\*(C'\fR
  2915. relocations.  Otherwise, only the PC-relative \f(CW\*(C`L32R\*(C'\fR relocations
  2916. can be used.
  2917. .IP "\fB\-\-target\-align | \-\-no\-target\-align\fR" 4
  2918. .IX Item "--target-align | --no-target-align"
  2919. Enable or disable automatic alignment to reduce branch penalties at some
  2920. expense in code size.    This optimization is enabled by default.  Note
  2921. that the assembler will always align instructions like \f(CW\*(C`LOOP\*(C'\fR that
  2922. have fixed alignment requirements.
  2923. .IP "\fB\-\-longcalls | \-\-no\-longcalls\fR" 4
  2924. .IX Item "--longcalls | --no-longcalls"
  2925. Enable or disable transformation of call instructions to allow calls
  2926. across a greater range of addresses.    This option should be used when call
  2927. targets can potentially be out of range.  It may degrade both code size
  2928. and performance, but the linker can generally optimize away the
  2929. unnecessary overhead when a call ends up within range.  The default is
  2930. \&\fB\-\-no\-longcalls\fR.
  2931. .IP "\fB\-\-transform | \-\-no\-transform\fR" 4
  2932. .IX Item "--transform | --no-transform"
  2933. Enable or disable all assembler transformations of Xtensa instructions,
  2934. including both relaxation and optimization.  The default is
  2935. \&\fB\-\-transform\fR; \fB\-\-no\-transform\fR should only be used in the
  2936. rare cases when the instructions must be exactly as specified in the
  2937. assembly source.  Using \fB\-\-no\-transform\fR causes out of range
  2938. instruction operands to be errors.
  2939. .IP "\fB\-\-rename\-section\fR \fIoldname\fR\fB=\fR\fInewname\fR" 4
  2940. .IX Item "--rename-section oldname=newname"
  2941. Rename the \fIoldname\fR section to \fInewname\fR.  This option can be used
  2942. multiple times to rename multiple sections.
  2943. .IP "\fB\-\-trampolines | \-\-no\-trampolines\fR" 4
  2944. .IX Item "--trampolines | --no-trampolines"
  2945. Enable or disable transformation of jump instructions to allow jumps
  2946. across a greater range of addresses.    This option should be used when jump targets can
  2947. potentially be out of range.  In the absence of such jumps this option
  2948. does not affect code size or performance.  The default is
  2949. \&\fB\-\-trampolines\fR.
  2950. .IP "\fB\-\-abi\-windowed | \-\-abi\-call0\fR" 4
  2951. .IX Item "--abi-windowed | --abi-call0"
  2952. Choose \s-1ABI\s0 tag written to the \f(CW\*(C`.xtensa.info\*(C'\fR section.  \s-1ABI\s0 tag
  2953. indicates \s-1ABI\s0 of the assembly code.  A warning is issued by the linker
  2954. on an attempt to link object files with inconsistent \s-1ABI\s0 tags.
  2955. Default \s-1ABI\s0 is chosen by the Xtensa core configuration.
  2956. .PP
  2957. The following options are available when as is configured for an
  2958. Z80 processor.
  2959. .PP
  2960. \&\f(CW@chapter\fR Z80 Dependent Features
  2961. .SS "Command-line Options"
  2962. .IX Subsection "Command-line Options"
  2963. .IP "\fB\-march=\fR\fI\s-1CPU\s0\fR\fB[\-\fR\fI\s-1EXT\s0\fR\fB...][+\fR\fI\s-1EXT\s0\fR\fB...]\fR" 4
  2964. .IX Item "-march=CPU[-EXT...][+EXT...]"
  2965. This option specifies the target processor. The assembler will issue
  2966. an error message if an attempt is made to assemble an instruction which
  2967. will not execute on the target processor. The following processor names
  2968. are recognized:
  2969. \&\f(CW\*(C`z80\*(C'\fR,
  2970. \&\f(CW\*(C`z180\*(C'\fR,
  2971. \&\f(CW\*(C`ez80\*(C'\fR,
  2972. \&\f(CW\*(C`gbz80\*(C'\fR,
  2973. \&\f(CW\*(C`z80n\*(C'\fR,
  2974. \&\f(CW\*(C`r800\*(C'\fR.
  2975. In addition to the basic instruction set, the assembler can be told to
  2976. accept some extention mnemonics. For example,
  2977. \&\f(CW\*(C`\-march=z180+sli+infc\*(C'\fR extends \fIz180\fR with \fI\s-1SLI\s0\fR instructions and
  2978. \&\fI\s-1IN F,\s0(C)\fR. The following extentions are currently supported:
  2979. \&\f(CW\*(C`full\*(C'\fR (all known instructions),
  2980. \&\f(CW\*(C`adl\*(C'\fR (\s-1ADL CPU\s0 mode by default, eZ80 only),
  2981. \&\f(CW\*(C`sli\*(C'\fR (instruction known as \fI\s-1SLI\s0\fR, \fI\s-1SLL\s0\fR or \fI\s-1SL1\s0\fR),
  2982. \&\f(CW\*(C`xyhl\*(C'\fR (instructions with halves of index registers: \fI\s-1IXL\s0\fR, \fI\s-1IXH\s0\fR,
  2983. \&\fI\s-1IYL\s0\fR, \fI\s-1IYH\s0\fR),
  2984. \&\f(CW\*(C`xdcb\*(C'\fR (instructions like \fIRotOp (II+d),R\fR and \fIBitOp n,(II+d),R\fR),
  2985. \&\f(CW\*(C`infc\*(C'\fR (instruction \fI\s-1IN F,\s0(C)\fR or \fI\s-1IN\s0 (C)\fR),
  2986. \&\f(CW\*(C`outc0\*(C'\fR (instruction \fI\s-1OUT\s0 (C),0\fR).
  2987. Note that rather than extending a basic instruction set, the extention
  2988. mnemonics starting with \f(CW\*(C`\-\*(C'\fR revoke the respective functionality:
  2989. \&\f(CW\*(C`\-march=z80\-full+xyhl\*(C'\fR first removes all default extentions and adds
  2990. support for index registers halves only.
  2991. .Sp
  2992. If this option is not specified then \f(CW\*(C`\-march=z80+xyhl+infc\*(C'\fR is assumed.
  2993. .IP "\fB\-local\-prefix=\fR\fIprefix\fR" 4
  2994. .IX Item "-local-prefix=prefix"
  2995. Mark all labels with specified prefix as local. But such label can be
  2996. marked global explicitly in the code. This option do not change default
  2997. local label prefix \f(CW\*(C`.L\*(C'\fR, it is just adds new one.
  2998. .IP "\fB\-colonless\fR" 4
  2999. .IX Item "-colonless"
  3000. Accept colonless labels. All symbols at line begin are treated as labels.
  3001. .IP "\fB\-sdcc\fR" 4
  3002. .IX Item "-sdcc"
  3003. Accept assembler code produced by \s-1SDCC.\s0
  3004. .IP "\fB\-fp\-s=\fR\fI\s-1FORMAT\s0\fR" 4
  3005. .IX Item "-fp-s=FORMAT"
  3006. Single precision floating point numbers format. Default: ieee754 (32 bit).
  3007. .IP "\fB\-fp\-d=\fR\fI\s-1FORMAT\s0\fR" 4
  3008. .IX Item "-fp-d=FORMAT"
  3009. Double precision floating point numbers format. Default: ieee754 (64 bit).
  3010. .SH "SEE ALSO"
  3011. .IX Header "SEE ALSO"
  3012. \&\fBgcc\fR\|(1), \fBld\fR\|(1), and the Info entries for \fIbinutils\fR and \fIld\fR.
  3013. .SH "COPYRIGHT"
  3014. .IX Header "COPYRIGHT"
  3015. Copyright (c) 1991\-2022 Free Software Foundation, Inc.
  3016. .PP
  3017. Permission is granted to copy, distribute and/or modify this document
  3018. under the terms of the \s-1GNU\s0 Free Documentation License, Version 1.3
  3019. or any later version published by the Free Software Foundation;
  3020. with no Invariant Sections, with no Front-Cover Texts, and with no
  3021. Back-Cover Texts.  A copy of the license is included in the
  3022. section entitled \*(L"\s-1GNU\s0 Free Documentation License\*(R".