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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

v4l2-dv-timings.h (31123B)


  1. /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
  2. /*
  3. * V4L2 DV timings header.
  4. *
  5. * Copyright (C) 2012-2016 Hans Verkuil <hans.verkuil@cisco.com>
  6. */
  7. #ifndef _V4L2_DV_TIMINGS_H
  8. #define _V4L2_DV_TIMINGS_H
  9. #if __GNUC__ < 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ < 6))
  10. /* Sadly gcc versions older than 4.6 have a bug in how they initialize
  11. anonymous unions where they require additional curly brackets.
  12. This violates the C1x standard. This workaround adds the curly brackets
  13. if needed. */
  14. #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  15. { .bt = { _width , ## args } }
  16. #else
  17. #define V4L2_INIT_BT_TIMINGS(_width, args...) \
  18. .bt = { _width , ## args }
  19. #endif
  20. /* CEA-861-F timings (i.e. standard HDTV timings) */
  21. #define V4L2_DV_BT_CEA_640X480P59_94 { \
  22. .type = V4L2_DV_BT_656_1120, \
  23. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  24. 25175000, 16, 96, 48, 10, 2, 33, 0, 0, 0, \
  25. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  26. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 1) \
  27. }
  28. /* Note: these are the nominal timings, for HDMI links this format is typically
  29. * double-clocked to meet the minimum pixelclock requirements. */
  30. #define V4L2_DV_BT_CEA_720X480I59_94 { \
  31. .type = V4L2_DV_BT_656_1120, \
  32. V4L2_INIT_BT_TIMINGS(720, 480, 1, 0, \
  33. 13500000, 19, 62, 57, 4, 3, 15, 4, 3, 16, \
  34. V4L2_DV_BT_STD_CEA861, \
  35. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  36. V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
  37. { 4, 3 }, 6) \
  38. }
  39. #define V4L2_DV_BT_CEA_720X480P59_94 { \
  40. .type = V4L2_DV_BT_656_1120, \
  41. V4L2_INIT_BT_TIMINGS(720, 480, 0, 0, \
  42. 27000000, 16, 62, 60, 9, 6, 30, 0, 0, 0, \
  43. V4L2_DV_BT_STD_CEA861, \
  44. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
  45. V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 2) \
  46. }
  47. /* Note: these are the nominal timings, for HDMI links this format is typically
  48. * double-clocked to meet the minimum pixelclock requirements. */
  49. #define V4L2_DV_BT_CEA_720X576I50 { \
  50. .type = V4L2_DV_BT_656_1120, \
  51. V4L2_INIT_BT_TIMINGS(720, 576, 1, 0, \
  52. 13500000, 12, 63, 69, 2, 3, 19, 2, 3, 20, \
  53. V4L2_DV_BT_STD_CEA861, \
  54. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  55. V4L2_DV_FL_HAS_PICTURE_ASPECT | V4L2_DV_FL_HAS_CEA861_VIC, \
  56. { 4, 3 }, 21) \
  57. }
  58. #define V4L2_DV_BT_CEA_720X576P50 { \
  59. .type = V4L2_DV_BT_656_1120, \
  60. V4L2_INIT_BT_TIMINGS(720, 576, 0, 0, \
  61. 27000000, 12, 64, 68, 5, 5, 39, 0, 0, 0, \
  62. V4L2_DV_BT_STD_CEA861, \
  63. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_PICTURE_ASPECT | \
  64. V4L2_DV_FL_HAS_CEA861_VIC, { 4, 3 }, 17) \
  65. }
  66. #define V4L2_DV_BT_CEA_1280X720P24 { \
  67. .type = V4L2_DV_BT_656_1120, \
  68. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  69. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  70. 59400000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  71. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  72. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 60) \
  73. }
  74. #define V4L2_DV_BT_CEA_1280X720P25 { \
  75. .type = V4L2_DV_BT_656_1120, \
  76. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  77. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  78. 74250000, 2420, 40, 220, 5, 5, 20, 0, 0, 0, \
  79. V4L2_DV_BT_STD_CEA861, \
  80. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 61) \
  81. }
  82. #define V4L2_DV_BT_CEA_1280X720P30 { \
  83. .type = V4L2_DV_BT_656_1120, \
  84. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  85. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  86. 74250000, 1760, 40, 220, 5, 5, 20, 0, 0, 0, \
  87. V4L2_DV_BT_STD_CEA861, \
  88. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  89. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 62) \
  90. }
  91. #define V4L2_DV_BT_CEA_1280X720P50 { \
  92. .type = V4L2_DV_BT_656_1120, \
  93. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  94. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  95. 74250000, 440, 40, 220, 5, 5, 20, 0, 0, 0, \
  96. V4L2_DV_BT_STD_CEA861, \
  97. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 19) \
  98. }
  99. #define V4L2_DV_BT_CEA_1280X720P60 { \
  100. .type = V4L2_DV_BT_656_1120, \
  101. V4L2_INIT_BT_TIMINGS(1280, 720, 0, \
  102. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  103. 74250000, 110, 40, 220, 5, 5, 20, 0, 0, 0, \
  104. V4L2_DV_BT_STD_CEA861, \
  105. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  106. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 4) \
  107. }
  108. #define V4L2_DV_BT_CEA_1920X1080P24 { \
  109. .type = V4L2_DV_BT_656_1120, \
  110. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  111. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  112. 74250000, 638, 44, 148, 4, 5, 36, 0, 0, 0, \
  113. V4L2_DV_BT_STD_CEA861, \
  114. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  115. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 32) \
  116. }
  117. #define V4L2_DV_BT_CEA_1920X1080P25 { \
  118. .type = V4L2_DV_BT_656_1120, \
  119. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  120. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  121. 74250000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
  122. V4L2_DV_BT_STD_CEA861, \
  123. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 33) \
  124. }
  125. #define V4L2_DV_BT_CEA_1920X1080P30 { \
  126. .type = V4L2_DV_BT_656_1120, \
  127. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  128. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  129. 74250000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
  130. V4L2_DV_BT_STD_CEA861, \
  131. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  132. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 34) \
  133. }
  134. #define V4L2_DV_BT_CEA_1920X1080I50 { \
  135. .type = V4L2_DV_BT_656_1120, \
  136. V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
  137. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  138. 74250000, 528, 44, 148, 2, 5, 15, 2, 5, 16, \
  139. V4L2_DV_BT_STD_CEA861, \
  140. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  141. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 20) \
  142. }
  143. #define V4L2_DV_BT_CEA_1920X1080P50 { \
  144. .type = V4L2_DV_BT_656_1120, \
  145. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  146. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  147. 148500000, 528, 44, 148, 4, 5, 36, 0, 0, 0, \
  148. V4L2_DV_BT_STD_CEA861, \
  149. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 31) \
  150. }
  151. #define V4L2_DV_BT_CEA_1920X1080I60 { \
  152. .type = V4L2_DV_BT_656_1120, \
  153. V4L2_INIT_BT_TIMINGS(1920, 1080, 1, \
  154. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  155. 74250000, 88, 44, 148, 2, 5, 15, 2, 5, 16, \
  156. V4L2_DV_BT_STD_CEA861, \
  157. V4L2_DV_FL_CAN_REDUCE_FPS | \
  158. V4L2_DV_FL_HALF_LINE | V4L2_DV_FL_IS_CE_VIDEO | \
  159. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 5) \
  160. }
  161. #define V4L2_DV_BT_CEA_1920X1080P60 { \
  162. .type = V4L2_DV_BT_656_1120, \
  163. V4L2_INIT_BT_TIMINGS(1920, 1080, 0, \
  164. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  165. 148500000, 88, 44, 148, 4, 5, 36, 0, 0, 0, \
  166. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CEA861, \
  167. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  168. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 16) \
  169. }
  170. #define V4L2_DV_BT_CEA_3840X2160P24 { \
  171. .type = V4L2_DV_BT_656_1120, \
  172. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  173. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  174. 297000000, 1276, 88, 296, 8, 10, 72, 0, 0, 0, \
  175. V4L2_DV_BT_STD_CEA861, \
  176. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  177. V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
  178. { 0, 0 }, 93, 3) \
  179. }
  180. #define V4L2_DV_BT_CEA_3840X2160P25 { \
  181. .type = V4L2_DV_BT_656_1120, \
  182. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  183. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  184. 297000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
  185. V4L2_DV_BT_STD_CEA861, \
  186. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC | \
  187. V4L2_DV_FL_HAS_HDMI_VIC, { 0, 0 }, 94, 2) \
  188. }
  189. #define V4L2_DV_BT_CEA_3840X2160P30 { \
  190. .type = V4L2_DV_BT_656_1120, \
  191. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  192. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  193. 297000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
  194. V4L2_DV_BT_STD_CEA861, \
  195. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  196. V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
  197. { 0, 0 }, 95, 1) \
  198. }
  199. #define V4L2_DV_BT_CEA_3840X2160P50 { \
  200. .type = V4L2_DV_BT_656_1120, \
  201. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  202. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  203. 594000000, 1056, 88, 296, 8, 10, 72, 0, 0, 0, \
  204. V4L2_DV_BT_STD_CEA861, \
  205. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 96) \
  206. }
  207. #define V4L2_DV_BT_CEA_3840X2160P60 { \
  208. .type = V4L2_DV_BT_656_1120, \
  209. V4L2_INIT_BT_TIMINGS(3840, 2160, 0, \
  210. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  211. 594000000, 176, 88, 296, 8, 10, 72, 0, 0, 0, \
  212. V4L2_DV_BT_STD_CEA861, \
  213. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  214. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 97) \
  215. }
  216. #define V4L2_DV_BT_CEA_4096X2160P24 { \
  217. .type = V4L2_DV_BT_656_1120, \
  218. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  219. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  220. 297000000, 1020, 88, 296, 8, 10, 72, 0, 0, 0, \
  221. V4L2_DV_BT_STD_CEA861, \
  222. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  223. V4L2_DV_FL_HAS_CEA861_VIC | V4L2_DV_FL_HAS_HDMI_VIC, \
  224. { 0, 0 }, 98, 4) \
  225. }
  226. #define V4L2_DV_BT_CEA_4096X2160P25 { \
  227. .type = V4L2_DV_BT_656_1120, \
  228. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  229. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  230. 297000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
  231. V4L2_DV_BT_STD_CEA861, \
  232. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 99) \
  233. }
  234. #define V4L2_DV_BT_CEA_4096X2160P30 { \
  235. .type = V4L2_DV_BT_656_1120, \
  236. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  237. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  238. 297000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
  239. V4L2_DV_BT_STD_CEA861, \
  240. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  241. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 100) \
  242. }
  243. #define V4L2_DV_BT_CEA_4096X2160P50 { \
  244. .type = V4L2_DV_BT_656_1120, \
  245. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  246. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  247. 594000000, 968, 88, 128, 8, 10, 72, 0, 0, 0, \
  248. V4L2_DV_BT_STD_CEA861, \
  249. V4L2_DV_FL_IS_CE_VIDEO | V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 101) \
  250. }
  251. #define V4L2_DV_BT_CEA_4096X2160P60 { \
  252. .type = V4L2_DV_BT_656_1120, \
  253. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, \
  254. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  255. 594000000, 88, 88, 128, 8, 10, 72, 0, 0, 0, \
  256. V4L2_DV_BT_STD_CEA861, \
  257. V4L2_DV_FL_CAN_REDUCE_FPS | V4L2_DV_FL_IS_CE_VIDEO | \
  258. V4L2_DV_FL_HAS_CEA861_VIC, { 0, 0 }, 102) \
  259. }
  260. /* VESA Discrete Monitor Timings as per version 1.0, revision 12 */
  261. #define V4L2_DV_BT_DMT_640X350P85 { \
  262. .type = V4L2_DV_BT_656_1120, \
  263. V4L2_INIT_BT_TIMINGS(640, 350, 0, V4L2_DV_HSYNC_POS_POL, \
  264. 31500000, 32, 64, 96, 32, 3, 60, 0, 0, 0, \
  265. V4L2_DV_BT_STD_DMT, 0) \
  266. }
  267. #define V4L2_DV_BT_DMT_640X400P85 { \
  268. .type = V4L2_DV_BT_656_1120, \
  269. V4L2_INIT_BT_TIMINGS(640, 400, 0, V4L2_DV_VSYNC_POS_POL, \
  270. 31500000, 32, 64, 96, 1, 3, 41, 0, 0, 0, \
  271. V4L2_DV_BT_STD_DMT, 0) \
  272. }
  273. #define V4L2_DV_BT_DMT_720X400P85 { \
  274. .type = V4L2_DV_BT_656_1120, \
  275. V4L2_INIT_BT_TIMINGS(720, 400, 0, V4L2_DV_VSYNC_POS_POL, \
  276. 35500000, 36, 72, 108, 1, 3, 42, 0, 0, 0, \
  277. V4L2_DV_BT_STD_DMT, 0) \
  278. }
  279. /* VGA resolutions */
  280. #define V4L2_DV_BT_DMT_640X480P60 V4L2_DV_BT_CEA_640X480P59_94
  281. #define V4L2_DV_BT_DMT_640X480P72 { \
  282. .type = V4L2_DV_BT_656_1120, \
  283. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  284. 31500000, 24, 40, 128, 9, 3, 28, 0, 0, 0, \
  285. V4L2_DV_BT_STD_DMT, 0) \
  286. }
  287. #define V4L2_DV_BT_DMT_640X480P75 { \
  288. .type = V4L2_DV_BT_656_1120, \
  289. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  290. 31500000, 16, 64, 120, 1, 3, 16, 0, 0, 0, \
  291. V4L2_DV_BT_STD_DMT, 0) \
  292. }
  293. #define V4L2_DV_BT_DMT_640X480P85 { \
  294. .type = V4L2_DV_BT_656_1120, \
  295. V4L2_INIT_BT_TIMINGS(640, 480, 0, 0, \
  296. 36000000, 56, 56, 80, 1, 3, 25, 0, 0, 0, \
  297. V4L2_DV_BT_STD_DMT, 0) \
  298. }
  299. /* SVGA resolutions */
  300. #define V4L2_DV_BT_DMT_800X600P56 { \
  301. .type = V4L2_DV_BT_656_1120, \
  302. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  303. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  304. 36000000, 24, 72, 128, 1, 2, 22, 0, 0, 0, \
  305. V4L2_DV_BT_STD_DMT, 0) \
  306. }
  307. #define V4L2_DV_BT_DMT_800X600P60 { \
  308. .type = V4L2_DV_BT_656_1120, \
  309. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  310. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  311. 40000000, 40, 128, 88, 1, 4, 23, 0, 0, 0, \
  312. V4L2_DV_BT_STD_DMT, 0) \
  313. }
  314. #define V4L2_DV_BT_DMT_800X600P72 { \
  315. .type = V4L2_DV_BT_656_1120, \
  316. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  317. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  318. 50000000, 56, 120, 64, 37, 6, 23, 0, 0, 0, \
  319. V4L2_DV_BT_STD_DMT, 0) \
  320. }
  321. #define V4L2_DV_BT_DMT_800X600P75 { \
  322. .type = V4L2_DV_BT_656_1120, \
  323. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  324. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  325. 49500000, 16, 80, 160, 1, 3, 21, 0, 0, 0, \
  326. V4L2_DV_BT_STD_DMT, 0) \
  327. }
  328. #define V4L2_DV_BT_DMT_800X600P85 { \
  329. .type = V4L2_DV_BT_656_1120, \
  330. V4L2_INIT_BT_TIMINGS(800, 600, 0, \
  331. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  332. 56250000, 32, 64, 152, 1, 3, 27, 0, 0, 0, \
  333. V4L2_DV_BT_STD_DMT, 0) \
  334. }
  335. #define V4L2_DV_BT_DMT_800X600P120_RB { \
  336. .type = V4L2_DV_BT_656_1120, \
  337. V4L2_INIT_BT_TIMINGS(800, 600, 0, V4L2_DV_HSYNC_POS_POL, \
  338. 73250000, 48, 32, 80, 3, 4, 29, 0, 0, 0, \
  339. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  340. V4L2_DV_FL_REDUCED_BLANKING) \
  341. }
  342. #define V4L2_DV_BT_DMT_848X480P60 { \
  343. .type = V4L2_DV_BT_656_1120, \
  344. V4L2_INIT_BT_TIMINGS(848, 480, 0, \
  345. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  346. 33750000, 16, 112, 112, 6, 8, 23, 0, 0, 0, \
  347. V4L2_DV_BT_STD_DMT, 0) \
  348. }
  349. #define V4L2_DV_BT_DMT_1024X768I43 { \
  350. .type = V4L2_DV_BT_656_1120, \
  351. V4L2_INIT_BT_TIMINGS(1024, 768, 1, \
  352. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  353. 44900000, 8, 176, 56, 0, 4, 20, 0, 4, 21, \
  354. V4L2_DV_BT_STD_DMT, 0) \
  355. }
  356. /* XGA resolutions */
  357. #define V4L2_DV_BT_DMT_1024X768P60 { \
  358. .type = V4L2_DV_BT_656_1120, \
  359. V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
  360. 65000000, 24, 136, 160, 3, 6, 29, 0, 0, 0, \
  361. V4L2_DV_BT_STD_DMT, 0) \
  362. }
  363. #define V4L2_DV_BT_DMT_1024X768P70 { \
  364. .type = V4L2_DV_BT_656_1120, \
  365. V4L2_INIT_BT_TIMINGS(1024, 768, 0, 0, \
  366. 75000000, 24, 136, 144, 3, 6, 29, 0, 0, 0, \
  367. V4L2_DV_BT_STD_DMT, 0) \
  368. }
  369. #define V4L2_DV_BT_DMT_1024X768P75 { \
  370. .type = V4L2_DV_BT_656_1120, \
  371. V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
  372. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  373. 78750000, 16, 96, 176, 1, 3, 28, 0, 0, 0, \
  374. V4L2_DV_BT_STD_DMT, 0) \
  375. }
  376. #define V4L2_DV_BT_DMT_1024X768P85 { \
  377. .type = V4L2_DV_BT_656_1120, \
  378. V4L2_INIT_BT_TIMINGS(1024, 768, 0, \
  379. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  380. 94500000, 48, 96, 208, 1, 3, 36, 0, 0, 0, \
  381. V4L2_DV_BT_STD_DMT, 0) \
  382. }
  383. #define V4L2_DV_BT_DMT_1024X768P120_RB { \
  384. .type = V4L2_DV_BT_656_1120, \
  385. V4L2_INIT_BT_TIMINGS(1024, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  386. 115500000, 48, 32, 80, 3, 4, 38, 0, 0, 0, \
  387. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  388. V4L2_DV_FL_REDUCED_BLANKING) \
  389. }
  390. /* XGA+ resolution */
  391. #define V4L2_DV_BT_DMT_1152X864P75 { \
  392. .type = V4L2_DV_BT_656_1120, \
  393. V4L2_INIT_BT_TIMINGS(1152, 864, 0, \
  394. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  395. 108000000, 64, 128, 256, 1, 3, 32, 0, 0, 0, \
  396. V4L2_DV_BT_STD_DMT, 0) \
  397. }
  398. #define V4L2_DV_BT_DMT_1280X720P60 V4L2_DV_BT_CEA_1280X720P60
  399. /* WXGA resolutions */
  400. #define V4L2_DV_BT_DMT_1280X768P60_RB { \
  401. .type = V4L2_DV_BT_656_1120, \
  402. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  403. 68250000, 48, 32, 80, 3, 7, 12, 0, 0, 0, \
  404. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  405. V4L2_DV_FL_REDUCED_BLANKING) \
  406. }
  407. #define V4L2_DV_BT_DMT_1280X768P60 { \
  408. .type = V4L2_DV_BT_656_1120, \
  409. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
  410. 79500000, 64, 128, 192, 3, 7, 20, 0, 0, 0, \
  411. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  412. }
  413. #define V4L2_DV_BT_DMT_1280X768P75 { \
  414. .type = V4L2_DV_BT_656_1120, \
  415. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
  416. 102250000, 80, 128, 208, 3, 7, 27, 0, 0, 0, \
  417. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  418. }
  419. #define V4L2_DV_BT_DMT_1280X768P85 { \
  420. .type = V4L2_DV_BT_656_1120, \
  421. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_VSYNC_POS_POL, \
  422. 117500000, 80, 136, 216, 3, 7, 31, 0, 0, 0, \
  423. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  424. }
  425. #define V4L2_DV_BT_DMT_1280X768P120_RB { \
  426. .type = V4L2_DV_BT_656_1120, \
  427. V4L2_INIT_BT_TIMINGS(1280, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  428. 140250000, 48, 32, 80, 3, 7, 35, 0, 0, 0, \
  429. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  430. V4L2_DV_FL_REDUCED_BLANKING) \
  431. }
  432. #define V4L2_DV_BT_DMT_1280X800P60_RB { \
  433. .type = V4L2_DV_BT_656_1120, \
  434. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
  435. 71000000, 48, 32, 80, 3, 6, 14, 0, 0, 0, \
  436. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  437. V4L2_DV_FL_REDUCED_BLANKING) \
  438. }
  439. #define V4L2_DV_BT_DMT_1280X800P60 { \
  440. .type = V4L2_DV_BT_656_1120, \
  441. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
  442. 83500000, 72, 128, 200, 3, 6, 22, 0, 0, 0, \
  443. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  444. }
  445. #define V4L2_DV_BT_DMT_1280X800P75 { \
  446. .type = V4L2_DV_BT_656_1120, \
  447. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
  448. 106500000, 80, 128, 208, 3, 6, 29, 0, 0, 0, \
  449. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  450. }
  451. #define V4L2_DV_BT_DMT_1280X800P85 { \
  452. .type = V4L2_DV_BT_656_1120, \
  453. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_VSYNC_POS_POL, \
  454. 122500000, 80, 136, 216, 3, 6, 34, 0, 0, 0, \
  455. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  456. }
  457. #define V4L2_DV_BT_DMT_1280X800P120_RB { \
  458. .type = V4L2_DV_BT_656_1120, \
  459. V4L2_INIT_BT_TIMINGS(1280, 800, 0, V4L2_DV_HSYNC_POS_POL, \
  460. 146250000, 48, 32, 80, 3, 6, 38, 0, 0, 0, \
  461. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  462. V4L2_DV_FL_REDUCED_BLANKING) \
  463. }
  464. #define V4L2_DV_BT_DMT_1280X960P60 { \
  465. .type = V4L2_DV_BT_656_1120, \
  466. V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
  467. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  468. 108000000, 96, 112, 312, 1, 3, 36, 0, 0, 0, \
  469. V4L2_DV_BT_STD_DMT, 0) \
  470. }
  471. #define V4L2_DV_BT_DMT_1280X960P85 { \
  472. .type = V4L2_DV_BT_656_1120, \
  473. V4L2_INIT_BT_TIMINGS(1280, 960, 0, \
  474. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  475. 148500000, 64, 160, 224, 1, 3, 47, 0, 0, 0, \
  476. V4L2_DV_BT_STD_DMT, 0) \
  477. }
  478. #define V4L2_DV_BT_DMT_1280X960P120_RB { \
  479. .type = V4L2_DV_BT_656_1120, \
  480. V4L2_INIT_BT_TIMINGS(1280, 960, 0, V4L2_DV_HSYNC_POS_POL, \
  481. 175500000, 48, 32, 80, 3, 4, 50, 0, 0, 0, \
  482. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  483. V4L2_DV_FL_REDUCED_BLANKING) \
  484. }
  485. /* SXGA resolutions */
  486. #define V4L2_DV_BT_DMT_1280X1024P60 { \
  487. .type = V4L2_DV_BT_656_1120, \
  488. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
  489. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  490. 108000000, 48, 112, 248, 1, 3, 38, 0, 0, 0, \
  491. V4L2_DV_BT_STD_DMT, 0) \
  492. }
  493. #define V4L2_DV_BT_DMT_1280X1024P75 { \
  494. .type = V4L2_DV_BT_656_1120, \
  495. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
  496. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  497. 135000000, 16, 144, 248, 1, 3, 38, 0, 0, 0, \
  498. V4L2_DV_BT_STD_DMT, 0) \
  499. }
  500. #define V4L2_DV_BT_DMT_1280X1024P85 { \
  501. .type = V4L2_DV_BT_656_1120, \
  502. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, \
  503. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  504. 157500000, 64, 160, 224, 1, 3, 44, 0, 0, 0, \
  505. V4L2_DV_BT_STD_DMT, 0) \
  506. }
  507. #define V4L2_DV_BT_DMT_1280X1024P120_RB { \
  508. .type = V4L2_DV_BT_656_1120, \
  509. V4L2_INIT_BT_TIMINGS(1280, 1024, 0, V4L2_DV_HSYNC_POS_POL, \
  510. 187250000, 48, 32, 80, 3, 7, 50, 0, 0, 0, \
  511. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  512. V4L2_DV_FL_REDUCED_BLANKING) \
  513. }
  514. #define V4L2_DV_BT_DMT_1360X768P60 { \
  515. .type = V4L2_DV_BT_656_1120, \
  516. V4L2_INIT_BT_TIMINGS(1360, 768, 0, \
  517. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  518. 85500000, 64, 112, 256, 3, 6, 18, 0, 0, 0, \
  519. V4L2_DV_BT_STD_DMT, 0) \
  520. }
  521. #define V4L2_DV_BT_DMT_1360X768P120_RB { \
  522. .type = V4L2_DV_BT_656_1120, \
  523. V4L2_INIT_BT_TIMINGS(1360, 768, 0, V4L2_DV_HSYNC_POS_POL, \
  524. 148250000, 48, 32, 80, 3, 5, 37, 0, 0, 0, \
  525. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  526. V4L2_DV_FL_REDUCED_BLANKING) \
  527. }
  528. #define V4L2_DV_BT_DMT_1366X768P60 { \
  529. .type = V4L2_DV_BT_656_1120, \
  530. V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
  531. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  532. 85500000, 70, 143, 213, 3, 3, 24, 0, 0, 0, \
  533. V4L2_DV_BT_STD_DMT, 0) \
  534. }
  535. #define V4L2_DV_BT_DMT_1366X768P60_RB { \
  536. .type = V4L2_DV_BT_656_1120, \
  537. V4L2_INIT_BT_TIMINGS(1366, 768, 0, \
  538. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  539. 72000000, 14, 56, 64, 1, 3, 28, 0, 0, 0, \
  540. V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
  541. }
  542. /* SXGA+ resolutions */
  543. #define V4L2_DV_BT_DMT_1400X1050P60_RB { \
  544. .type = V4L2_DV_BT_656_1120, \
  545. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  546. 101000000, 48, 32, 80, 3, 4, 23, 0, 0, 0, \
  547. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  548. V4L2_DV_FL_REDUCED_BLANKING) \
  549. }
  550. #define V4L2_DV_BT_DMT_1400X1050P60 { \
  551. .type = V4L2_DV_BT_656_1120, \
  552. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  553. 121750000, 88, 144, 232, 3, 4, 32, 0, 0, 0, \
  554. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  555. }
  556. #define V4L2_DV_BT_DMT_1400X1050P75 { \
  557. .type = V4L2_DV_BT_656_1120, \
  558. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  559. 156000000, 104, 144, 248, 3, 4, 42, 0, 0, 0, \
  560. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  561. }
  562. #define V4L2_DV_BT_DMT_1400X1050P85 { \
  563. .type = V4L2_DV_BT_656_1120, \
  564. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  565. 179500000, 104, 152, 256, 3, 4, 48, 0, 0, 0, \
  566. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  567. }
  568. #define V4L2_DV_BT_DMT_1400X1050P120_RB { \
  569. .type = V4L2_DV_BT_656_1120, \
  570. V4L2_INIT_BT_TIMINGS(1400, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  571. 208000000, 48, 32, 80, 3, 4, 55, 0, 0, 0, \
  572. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  573. V4L2_DV_FL_REDUCED_BLANKING) \
  574. }
  575. /* WXGA+ resolutions */
  576. #define V4L2_DV_BT_DMT_1440X900P60_RB { \
  577. .type = V4L2_DV_BT_656_1120, \
  578. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
  579. 88750000, 48, 32, 80, 3, 6, 17, 0, 0, 0, \
  580. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  581. V4L2_DV_FL_REDUCED_BLANKING) \
  582. }
  583. #define V4L2_DV_BT_DMT_1440X900P60 { \
  584. .type = V4L2_DV_BT_656_1120, \
  585. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
  586. 106500000, 80, 152, 232, 3, 6, 25, 0, 0, 0, \
  587. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  588. }
  589. #define V4L2_DV_BT_DMT_1440X900P75 { \
  590. .type = V4L2_DV_BT_656_1120, \
  591. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
  592. 136750000, 96, 152, 248, 3, 6, 33, 0, 0, 0, \
  593. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  594. }
  595. #define V4L2_DV_BT_DMT_1440X900P85 { \
  596. .type = V4L2_DV_BT_656_1120, \
  597. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_VSYNC_POS_POL, \
  598. 157000000, 104, 152, 256, 3, 6, 39, 0, 0, 0, \
  599. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  600. }
  601. #define V4L2_DV_BT_DMT_1440X900P120_RB { \
  602. .type = V4L2_DV_BT_656_1120, \
  603. V4L2_INIT_BT_TIMINGS(1440, 900, 0, V4L2_DV_HSYNC_POS_POL, \
  604. 182750000, 48, 32, 80, 3, 6, 44, 0, 0, 0, \
  605. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  606. V4L2_DV_FL_REDUCED_BLANKING) \
  607. }
  608. #define V4L2_DV_BT_DMT_1600X900P60_RB { \
  609. .type = V4L2_DV_BT_656_1120, \
  610. V4L2_INIT_BT_TIMINGS(1600, 900, 0, \
  611. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  612. 108000000, 24, 80, 96, 1, 3, 96, 0, 0, 0, \
  613. V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
  614. }
  615. /* UXGA resolutions */
  616. #define V4L2_DV_BT_DMT_1600X1200P60 { \
  617. .type = V4L2_DV_BT_656_1120, \
  618. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  619. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  620. 162000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  621. V4L2_DV_BT_STD_DMT, 0) \
  622. }
  623. #define V4L2_DV_BT_DMT_1600X1200P65 { \
  624. .type = V4L2_DV_BT_656_1120, \
  625. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  626. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  627. 175500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  628. V4L2_DV_BT_STD_DMT, 0) \
  629. }
  630. #define V4L2_DV_BT_DMT_1600X1200P70 { \
  631. .type = V4L2_DV_BT_656_1120, \
  632. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  633. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  634. 189000000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  635. V4L2_DV_BT_STD_DMT, 0) \
  636. }
  637. #define V4L2_DV_BT_DMT_1600X1200P75 { \
  638. .type = V4L2_DV_BT_656_1120, \
  639. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  640. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  641. 202500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  642. V4L2_DV_BT_STD_DMT, 0) \
  643. }
  644. #define V4L2_DV_BT_DMT_1600X1200P85 { \
  645. .type = V4L2_DV_BT_656_1120, \
  646. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, \
  647. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  648. 229500000, 64, 192, 304, 1, 3, 46, 0, 0, 0, \
  649. V4L2_DV_BT_STD_DMT, 0) \
  650. }
  651. #define V4L2_DV_BT_DMT_1600X1200P120_RB { \
  652. .type = V4L2_DV_BT_656_1120, \
  653. V4L2_INIT_BT_TIMINGS(1600, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
  654. 268250000, 48, 32, 80, 3, 4, 64, 0, 0, 0, \
  655. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  656. V4L2_DV_FL_REDUCED_BLANKING) \
  657. }
  658. /* WSXGA+ resolutions */
  659. #define V4L2_DV_BT_DMT_1680X1050P60_RB { \
  660. .type = V4L2_DV_BT_656_1120, \
  661. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  662. 119000000, 48, 32, 80, 3, 6, 21, 0, 0, 0, \
  663. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  664. V4L2_DV_FL_REDUCED_BLANKING) \
  665. }
  666. #define V4L2_DV_BT_DMT_1680X1050P60 { \
  667. .type = V4L2_DV_BT_656_1120, \
  668. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  669. 146250000, 104, 176, 280, 3, 6, 30, 0, 0, 0, \
  670. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  671. }
  672. #define V4L2_DV_BT_DMT_1680X1050P75 { \
  673. .type = V4L2_DV_BT_656_1120, \
  674. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  675. 187000000, 120, 176, 296, 3, 6, 40, 0, 0, 0, \
  676. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  677. }
  678. #define V4L2_DV_BT_DMT_1680X1050P85 { \
  679. .type = V4L2_DV_BT_656_1120, \
  680. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_VSYNC_POS_POL, \
  681. 214750000, 128, 176, 304, 3, 6, 46, 0, 0, 0, \
  682. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  683. }
  684. #define V4L2_DV_BT_DMT_1680X1050P120_RB { \
  685. .type = V4L2_DV_BT_656_1120, \
  686. V4L2_INIT_BT_TIMINGS(1680, 1050, 0, V4L2_DV_HSYNC_POS_POL, \
  687. 245500000, 48, 32, 80, 3, 6, 53, 0, 0, 0, \
  688. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  689. V4L2_DV_FL_REDUCED_BLANKING) \
  690. }
  691. #define V4L2_DV_BT_DMT_1792X1344P60 { \
  692. .type = V4L2_DV_BT_656_1120, \
  693. V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
  694. 204750000, 128, 200, 328, 1, 3, 46, 0, 0, 0, \
  695. V4L2_DV_BT_STD_DMT, 0) \
  696. }
  697. #define V4L2_DV_BT_DMT_1792X1344P75 { \
  698. .type = V4L2_DV_BT_656_1120, \
  699. V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_VSYNC_POS_POL, \
  700. 261000000, 96, 216, 352, 1, 3, 69, 0, 0, 0, \
  701. V4L2_DV_BT_STD_DMT, 0) \
  702. }
  703. #define V4L2_DV_BT_DMT_1792X1344P120_RB { \
  704. .type = V4L2_DV_BT_656_1120, \
  705. V4L2_INIT_BT_TIMINGS(1792, 1344, 0, V4L2_DV_HSYNC_POS_POL, \
  706. 333250000, 48, 32, 80, 3, 4, 72, 0, 0, 0, \
  707. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  708. V4L2_DV_FL_REDUCED_BLANKING) \
  709. }
  710. #define V4L2_DV_BT_DMT_1856X1392P60 { \
  711. .type = V4L2_DV_BT_656_1120, \
  712. V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
  713. 218250000, 96, 224, 352, 1, 3, 43, 0, 0, 0, \
  714. V4L2_DV_BT_STD_DMT, 0) \
  715. }
  716. #define V4L2_DV_BT_DMT_1856X1392P75 { \
  717. .type = V4L2_DV_BT_656_1120, \
  718. V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_VSYNC_POS_POL, \
  719. 288000000, 128, 224, 352, 1, 3, 104, 0, 0, 0, \
  720. V4L2_DV_BT_STD_DMT, 0) \
  721. }
  722. #define V4L2_DV_BT_DMT_1856X1392P120_RB { \
  723. .type = V4L2_DV_BT_656_1120, \
  724. V4L2_INIT_BT_TIMINGS(1856, 1392, 0, V4L2_DV_HSYNC_POS_POL, \
  725. 356500000, 48, 32, 80, 3, 4, 75, 0, 0, 0, \
  726. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  727. V4L2_DV_FL_REDUCED_BLANKING) \
  728. }
  729. #define V4L2_DV_BT_DMT_1920X1080P60 V4L2_DV_BT_CEA_1920X1080P60
  730. /* WUXGA resolutions */
  731. #define V4L2_DV_BT_DMT_1920X1200P60_RB { \
  732. .type = V4L2_DV_BT_656_1120, \
  733. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
  734. 154000000, 48, 32, 80, 3, 6, 26, 0, 0, 0, \
  735. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  736. V4L2_DV_FL_REDUCED_BLANKING) \
  737. }
  738. #define V4L2_DV_BT_DMT_1920X1200P60 { \
  739. .type = V4L2_DV_BT_656_1120, \
  740. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
  741. 193250000, 136, 200, 336, 3, 6, 36, 0, 0, 0, \
  742. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  743. }
  744. #define V4L2_DV_BT_DMT_1920X1200P75 { \
  745. .type = V4L2_DV_BT_656_1120, \
  746. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
  747. 245250000, 136, 208, 344, 3, 6, 46, 0, 0, 0, \
  748. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  749. }
  750. #define V4L2_DV_BT_DMT_1920X1200P85 { \
  751. .type = V4L2_DV_BT_656_1120, \
  752. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_VSYNC_POS_POL, \
  753. 281250000, 144, 208, 352, 3, 6, 53, 0, 0, 0, \
  754. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  755. }
  756. #define V4L2_DV_BT_DMT_1920X1200P120_RB { \
  757. .type = V4L2_DV_BT_656_1120, \
  758. V4L2_INIT_BT_TIMINGS(1920, 1200, 0, V4L2_DV_HSYNC_POS_POL, \
  759. 317000000, 48, 32, 80, 3, 6, 62, 0, 0, 0, \
  760. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  761. V4L2_DV_FL_REDUCED_BLANKING) \
  762. }
  763. #define V4L2_DV_BT_DMT_1920X1440P60 { \
  764. .type = V4L2_DV_BT_656_1120, \
  765. V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
  766. 234000000, 128, 208, 344, 1, 3, 56, 0, 0, 0, \
  767. V4L2_DV_BT_STD_DMT, 0) \
  768. }
  769. #define V4L2_DV_BT_DMT_1920X1440P75 { \
  770. .type = V4L2_DV_BT_656_1120, \
  771. V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_VSYNC_POS_POL, \
  772. 297000000, 144, 224, 352, 1, 3, 56, 0, 0, 0, \
  773. V4L2_DV_BT_STD_DMT, 0) \
  774. }
  775. #define V4L2_DV_BT_DMT_1920X1440P120_RB { \
  776. .type = V4L2_DV_BT_656_1120, \
  777. V4L2_INIT_BT_TIMINGS(1920, 1440, 0, V4L2_DV_HSYNC_POS_POL, \
  778. 380500000, 48, 32, 80, 3, 4, 78, 0, 0, 0, \
  779. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  780. V4L2_DV_FL_REDUCED_BLANKING) \
  781. }
  782. #define V4L2_DV_BT_DMT_2048X1152P60_RB { \
  783. .type = V4L2_DV_BT_656_1120, \
  784. V4L2_INIT_BT_TIMINGS(2048, 1152, 0, \
  785. V4L2_DV_HSYNC_POS_POL | V4L2_DV_VSYNC_POS_POL, \
  786. 162000000, 26, 80, 96, 1, 3, 44, 0, 0, 0, \
  787. V4L2_DV_BT_STD_DMT, V4L2_DV_FL_REDUCED_BLANKING) \
  788. }
  789. /* WQXGA resolutions */
  790. #define V4L2_DV_BT_DMT_2560X1600P60_RB { \
  791. .type = V4L2_DV_BT_656_1120, \
  792. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
  793. 268500000, 48, 32, 80, 3, 6, 37, 0, 0, 0, \
  794. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  795. V4L2_DV_FL_REDUCED_BLANKING) \
  796. }
  797. #define V4L2_DV_BT_DMT_2560X1600P60 { \
  798. .type = V4L2_DV_BT_656_1120, \
  799. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
  800. 348500000, 192, 280, 472, 3, 6, 49, 0, 0, 0, \
  801. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  802. }
  803. #define V4L2_DV_BT_DMT_2560X1600P75 { \
  804. .type = V4L2_DV_BT_656_1120, \
  805. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
  806. 443250000, 208, 280, 488, 3, 6, 63, 0, 0, 0, \
  807. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  808. }
  809. #define V4L2_DV_BT_DMT_2560X1600P85 { \
  810. .type = V4L2_DV_BT_656_1120, \
  811. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_VSYNC_POS_POL, \
  812. 505250000, 208, 280, 488, 3, 6, 73, 0, 0, 0, \
  813. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, 0) \
  814. }
  815. #define V4L2_DV_BT_DMT_2560X1600P120_RB { \
  816. .type = V4L2_DV_BT_656_1120, \
  817. V4L2_INIT_BT_TIMINGS(2560, 1600, 0, V4L2_DV_HSYNC_POS_POL, \
  818. 552750000, 48, 32, 80, 3, 6, 85, 0, 0, 0, \
  819. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  820. V4L2_DV_FL_REDUCED_BLANKING) \
  821. }
  822. /* 4K resolutions */
  823. #define V4L2_DV_BT_DMT_4096X2160P60_RB { \
  824. .type = V4L2_DV_BT_656_1120, \
  825. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
  826. 556744000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
  827. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  828. V4L2_DV_FL_REDUCED_BLANKING) \
  829. }
  830. #define V4L2_DV_BT_DMT_4096X2160P59_94_RB { \
  831. .type = V4L2_DV_BT_656_1120, \
  832. V4L2_INIT_BT_TIMINGS(4096, 2160, 0, V4L2_DV_HSYNC_POS_POL, \
  833. 556188000, 8, 32, 40, 48, 8, 6, 0, 0, 0, \
  834. V4L2_DV_BT_STD_DMT | V4L2_DV_BT_STD_CVT, \
  835. V4L2_DV_FL_REDUCED_BLANKING) \
  836. }
  837. /* SDI timings definitions */
  838. /* SMPTE-125M */
  839. #define V4L2_DV_BT_SDI_720X487I60 { \
  840. .type = V4L2_DV_BT_656_1120, \
  841. V4L2_INIT_BT_TIMINGS(720, 487, 1, \
  842. V4L2_DV_HSYNC_POS_POL, \
  843. 13500000, 16, 121, 0, 0, 19, 0, 0, 19, 0, \
  844. V4L2_DV_BT_STD_SDI, \
  845. V4L2_DV_FL_FIRST_FIELD_EXTRA_LINE) \
  846. }
  847. #endif