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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

fpga-dfl.h (8728B)


  1. /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
  2. /*
  3. * Header File for FPGA DFL User API
  4. *
  5. * Copyright (C) 2017-2018 Intel Corporation, Inc.
  6. *
  7. * Authors:
  8. * Kang Luwei <luwei.kang@intel.com>
  9. * Zhang Yi <yi.z.zhang@intel.com>
  10. * Wu Hao <hao.wu@intel.com>
  11. * Xiao Guangrong <guangrong.xiao@linux.intel.com>
  12. */
  13. #ifndef _LINUX_FPGA_DFL_H
  14. #define _LINUX_FPGA_DFL_H
  15. #include <linux/types.h>
  16. #include <linux/ioctl.h>
  17. #define DFL_FPGA_API_VERSION 0
  18. /*
  19. * The IOCTL interface for DFL based FPGA is designed for extensibility by
  20. * embedding the structure length (argsz) and flags into structures passed
  21. * between kernel and userspace. This design referenced the VFIO IOCTL
  22. * interface (include/uapi/linux/vfio.h).
  23. */
  24. #define DFL_FPGA_MAGIC 0xB6
  25. #define DFL_FPGA_BASE 0
  26. #define DFL_PORT_BASE 0x40
  27. #define DFL_FME_BASE 0x80
  28. /* Common IOCTLs for both FME and AFU file descriptor */
  29. /**
  30. * DFL_FPGA_GET_API_VERSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
  31. *
  32. * Report the version of the driver API.
  33. * Return: Driver API Version.
  34. */
  35. #define DFL_FPGA_GET_API_VERSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 0)
  36. /**
  37. * DFL_FPGA_CHECK_EXTENSION - _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
  38. *
  39. * Check whether an extension is supported.
  40. * Return: 0 if not supported, otherwise the extension is supported.
  41. */
  42. #define DFL_FPGA_CHECK_EXTENSION _IO(DFL_FPGA_MAGIC, DFL_FPGA_BASE + 1)
  43. /* IOCTLs for AFU file descriptor */
  44. /**
  45. * DFL_FPGA_PORT_RESET - _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
  46. *
  47. * Reset the FPGA Port and its AFU. No parameters are supported.
  48. * Userspace can do Port reset at any time, e.g. during DMA or PR. But
  49. * it should never cause any system level issue, only functional failure
  50. * (e.g. DMA or PR operation failure) and be recoverable from the failure.
  51. * Return: 0 on success, -errno of failure
  52. */
  53. #define DFL_FPGA_PORT_RESET _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 0)
  54. /**
  55. * DFL_FPGA_PORT_GET_INFO - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1,
  56. * struct dfl_fpga_port_info)
  57. *
  58. * Retrieve information about the fpga port.
  59. * Driver fills the info in provided struct dfl_fpga_port_info.
  60. * Return: 0 on success, -errno on failure.
  61. */
  62. struct dfl_fpga_port_info {
  63. /* Input */
  64. __u32 argsz; /* Structure length */
  65. /* Output */
  66. __u32 flags; /* Zero for now */
  67. __u32 num_regions; /* The number of supported regions */
  68. __u32 num_umsgs; /* The number of allocated umsgs */
  69. };
  70. #define DFL_FPGA_PORT_GET_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 1)
  71. /**
  72. * FPGA_PORT_GET_REGION_INFO - _IOWR(FPGA_MAGIC, PORT_BASE + 2,
  73. * struct dfl_fpga_port_region_info)
  74. *
  75. * Retrieve information about a device memory region.
  76. * Caller provides struct dfl_fpga_port_region_info with index value set.
  77. * Driver returns the region info in other fields.
  78. * Return: 0 on success, -errno on failure.
  79. */
  80. struct dfl_fpga_port_region_info {
  81. /* input */
  82. __u32 argsz; /* Structure length */
  83. /* Output */
  84. __u32 flags; /* Access permission */
  85. #define DFL_PORT_REGION_READ (1 << 0) /* Region is readable */
  86. #define DFL_PORT_REGION_WRITE (1 << 1) /* Region is writable */
  87. #define DFL_PORT_REGION_MMAP (1 << 2) /* Can be mmaped to userspace */
  88. /* Input */
  89. __u32 index; /* Region index */
  90. #define DFL_PORT_REGION_INDEX_AFU 0 /* AFU */
  91. #define DFL_PORT_REGION_INDEX_STP 1 /* Signal Tap */
  92. __u32 padding;
  93. /* Output */
  94. __u64 size; /* Region size (bytes) */
  95. __u64 offset; /* Region offset from start of device fd */
  96. };
  97. #define DFL_FPGA_PORT_GET_REGION_INFO _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 2)
  98. /**
  99. * DFL_FPGA_PORT_DMA_MAP - _IOWR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3,
  100. * struct dfl_fpga_port_dma_map)
  101. *
  102. * Map the dma memory per user_addr and length which are provided by caller.
  103. * Driver fills the iova in provided struct afu_port_dma_map.
  104. * This interface only accepts page-size aligned user memory for dma mapping.
  105. * Return: 0 on success, -errno on failure.
  106. */
  107. struct dfl_fpga_port_dma_map {
  108. /* Input */
  109. __u32 argsz; /* Structure length */
  110. __u32 flags; /* Zero for now */
  111. __u64 user_addr; /* Process virtual address */
  112. __u64 length; /* Length of mapping (bytes)*/
  113. /* Output */
  114. __u64 iova; /* IO virtual address */
  115. };
  116. #define DFL_FPGA_PORT_DMA_MAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 3)
  117. /**
  118. * DFL_FPGA_PORT_DMA_UNMAP - _IOW(FPGA_MAGIC, PORT_BASE + 4,
  119. * struct dfl_fpga_port_dma_unmap)
  120. *
  121. * Unmap the dma memory per iova provided by caller.
  122. * Return: 0 on success, -errno on failure.
  123. */
  124. struct dfl_fpga_port_dma_unmap {
  125. /* Input */
  126. __u32 argsz; /* Structure length */
  127. __u32 flags; /* Zero for now */
  128. __u64 iova; /* IO virtual address */
  129. };
  130. #define DFL_FPGA_PORT_DMA_UNMAP _IO(DFL_FPGA_MAGIC, DFL_PORT_BASE + 4)
  131. /**
  132. * struct dfl_fpga_irq_set - the argument for DFL_FPGA_XXX_SET_IRQ ioctl.
  133. *
  134. * @start: Index of the first irq.
  135. * @count: The number of eventfd handler.
  136. * @evtfds: Eventfd handlers.
  137. */
  138. struct dfl_fpga_irq_set {
  139. __u32 start;
  140. __u32 count;
  141. __s32 evtfds[];
  142. };
  143. /**
  144. * DFL_FPGA_PORT_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 5,
  145. * __u32 num_irqs)
  146. *
  147. * Get the number of irqs supported by the fpga port error reporting private
  148. * feature. Currently hardware supports up to 1 irq.
  149. * Return: 0 on success, -errno on failure.
  150. */
  151. #define DFL_FPGA_PORT_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \
  152. DFL_PORT_BASE + 5, __u32)
  153. /**
  154. * DFL_FPGA_PORT_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 6,
  155. * struct dfl_fpga_irq_set)
  156. *
  157. * Set fpga port error reporting interrupt trigger if evtfds[n] is valid.
  158. * Unset related interrupt trigger if evtfds[n] is a negative value.
  159. * Return: 0 on success, -errno on failure.
  160. */
  161. #define DFL_FPGA_PORT_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \
  162. DFL_PORT_BASE + 6, \
  163. struct dfl_fpga_irq_set)
  164. /**
  165. * DFL_FPGA_PORT_UINT_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_PORT_BASE + 7,
  166. * __u32 num_irqs)
  167. *
  168. * Get the number of irqs supported by the fpga AFU interrupt private
  169. * feature.
  170. * Return: 0 on success, -errno on failure.
  171. */
  172. #define DFL_FPGA_PORT_UINT_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \
  173. DFL_PORT_BASE + 7, __u32)
  174. /**
  175. * DFL_FPGA_PORT_UINT_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_PORT_BASE + 8,
  176. * struct dfl_fpga_irq_set)
  177. *
  178. * Set fpga AFU interrupt trigger if evtfds[n] is valid.
  179. * Unset related interrupt trigger if evtfds[n] is a negative value.
  180. * Return: 0 on success, -errno on failure.
  181. */
  182. #define DFL_FPGA_PORT_UINT_SET_IRQ _IOW(DFL_FPGA_MAGIC, \
  183. DFL_PORT_BASE + 8, \
  184. struct dfl_fpga_irq_set)
  185. /* IOCTLs for FME file descriptor */
  186. /**
  187. * DFL_FPGA_FME_PORT_PR - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 0,
  188. * struct dfl_fpga_fme_port_pr)
  189. *
  190. * Driver does Partial Reconfiguration based on Port ID and Buffer (Image)
  191. * provided by caller.
  192. * Return: 0 on success, -errno on failure.
  193. * If DFL_FPGA_FME_PORT_PR returns -EIO, that indicates the HW has detected
  194. * some errors during PR, under this case, the user can fetch HW error info
  195. * from the status of FME's fpga manager.
  196. */
  197. struct dfl_fpga_fme_port_pr {
  198. /* Input */
  199. __u32 argsz; /* Structure length */
  200. __u32 flags; /* Zero for now */
  201. __u32 port_id;
  202. __u32 buffer_size;
  203. __u64 buffer_address; /* Userspace address to the buffer for PR */
  204. };
  205. #define DFL_FPGA_FME_PORT_PR _IO(DFL_FPGA_MAGIC, DFL_FME_BASE + 0)
  206. /**
  207. * DFL_FPGA_FME_PORT_RELEASE - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1,
  208. * int port_id)
  209. *
  210. * Driver releases the port per Port ID provided by caller.
  211. * Return: 0 on success, -errno on failure.
  212. */
  213. #define DFL_FPGA_FME_PORT_RELEASE _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 1, int)
  214. /**
  215. * DFL_FPGA_FME_PORT_ASSIGN - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2,
  216. * int port_id)
  217. *
  218. * Driver assigns the port back per Port ID provided by caller.
  219. * Return: 0 on success, -errno on failure.
  220. */
  221. #define DFL_FPGA_FME_PORT_ASSIGN _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 2, int)
  222. /**
  223. * DFL_FPGA_FME_ERR_GET_IRQ_NUM - _IOR(DFL_FPGA_MAGIC, DFL_FME_BASE + 3,
  224. * __u32 num_irqs)
  225. *
  226. * Get the number of irqs supported by the fpga fme error reporting private
  227. * feature. Currently hardware supports up to 1 irq.
  228. * Return: 0 on success, -errno on failure.
  229. */
  230. #define DFL_FPGA_FME_ERR_GET_IRQ_NUM _IOR(DFL_FPGA_MAGIC, \
  231. DFL_FME_BASE + 3, __u32)
  232. /**
  233. * DFL_FPGA_FME_ERR_SET_IRQ - _IOW(DFL_FPGA_MAGIC, DFL_FME_BASE + 4,
  234. * struct dfl_fpga_irq_set)
  235. *
  236. * Set fpga fme error reporting interrupt trigger if evtfds[n] is valid.
  237. * Unset related interrupt trigger if evtfds[n] is a negative value.
  238. * Return: 0 on success, -errno on failure.
  239. */
  240. #define DFL_FPGA_FME_ERR_SET_IRQ _IOW(DFL_FPGA_MAGIC, \
  241. DFL_FME_BASE + 4, \
  242. struct dfl_fpga_irq_set)
  243. #endif /* _LINUX_FPGA_DFL_H */