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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

dpll.h (7359B)


  1. /* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
  2. /* Do not edit directly, auto-generated from: */
  3. /* Documentation/netlink/specs/dpll.yaml */
  4. /* YNL-GEN uapi header */
  5. #ifndef _LINUX_DPLL_H
  6. #define _LINUX_DPLL_H
  7. #define DPLL_FAMILY_NAME "dpll"
  8. #define DPLL_FAMILY_VERSION 1
  9. /**
  10. * enum dpll_mode - working modes a dpll can support, differentiates if and how
  11. * dpll selects one of its inputs to syntonize with it, valid values for
  12. * DPLL_A_MODE attribute
  13. * @DPLL_MODE_MANUAL: input can be only selected by sending a request to dpll
  14. * @DPLL_MODE_AUTOMATIC: highest prio input pin auto selected by dpll
  15. */
  16. enum dpll_mode {
  17. DPLL_MODE_MANUAL = 1,
  18. DPLL_MODE_AUTOMATIC,
  19. /* private: */
  20. __DPLL_MODE_MAX,
  21. DPLL_MODE_MAX = (__DPLL_MODE_MAX - 1)
  22. };
  23. /**
  24. * enum dpll_lock_status - provides information of dpll device lock status,
  25. * valid values for DPLL_A_LOCK_STATUS attribute
  26. * @DPLL_LOCK_STATUS_UNLOCKED: dpll was not yet locked to any valid input (or
  27. * forced by setting DPLL_A_MODE to DPLL_MODE_DETACHED)
  28. * @DPLL_LOCK_STATUS_LOCKED: dpll is locked to a valid signal, but no holdover
  29. * available
  30. * @DPLL_LOCK_STATUS_LOCKED_HO_ACQ: dpll is locked and holdover acquired
  31. * @DPLL_LOCK_STATUS_HOLDOVER: dpll is in holdover state - lost a valid lock or
  32. * was forced by disconnecting all the pins (latter possible only when dpll
  33. * lock-state was already DPLL_LOCK_STATUS_LOCKED_HO_ACQ, if dpll lock-state
  34. * was not DPLL_LOCK_STATUS_LOCKED_HO_ACQ, the dpll's lock-state shall remain
  35. * DPLL_LOCK_STATUS_UNLOCKED)
  36. */
  37. enum dpll_lock_status {
  38. DPLL_LOCK_STATUS_UNLOCKED = 1,
  39. DPLL_LOCK_STATUS_LOCKED,
  40. DPLL_LOCK_STATUS_LOCKED_HO_ACQ,
  41. DPLL_LOCK_STATUS_HOLDOVER,
  42. /* private: */
  43. __DPLL_LOCK_STATUS_MAX,
  44. DPLL_LOCK_STATUS_MAX = (__DPLL_LOCK_STATUS_MAX - 1)
  45. };
  46. /**
  47. * enum dpll_lock_status_error - if previous status change was done due to a
  48. * failure, this provides information of dpll device lock status error. Valid
  49. * values for DPLL_A_LOCK_STATUS_ERROR attribute
  50. * @DPLL_LOCK_STATUS_ERROR_NONE: dpll device lock status was changed without
  51. * any error
  52. * @DPLL_LOCK_STATUS_ERROR_UNDEFINED: dpll device lock status was changed due
  53. * to undefined error. Driver fills this value up in case it is not able to
  54. * obtain suitable exact error type.
  55. * @DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN: dpll device lock status was changed
  56. * because of associated media got down. This may happen for example if dpll
  57. * device was previously locked on an input pin of type
  58. * PIN_TYPE_SYNCE_ETH_PORT.
  59. * @DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH: the FFO
  60. * (Fractional Frequency Offset) between the RX and TX symbol rate on the
  61. * media got too high. This may happen for example if dpll device was
  62. * previously locked on an input pin of type PIN_TYPE_SYNCE_ETH_PORT.
  63. */
  64. enum dpll_lock_status_error {
  65. DPLL_LOCK_STATUS_ERROR_NONE = 1,
  66. DPLL_LOCK_STATUS_ERROR_UNDEFINED,
  67. DPLL_LOCK_STATUS_ERROR_MEDIA_DOWN,
  68. DPLL_LOCK_STATUS_ERROR_FRACTIONAL_FREQUENCY_OFFSET_TOO_HIGH,
  69. /* private: */
  70. __DPLL_LOCK_STATUS_ERROR_MAX,
  71. DPLL_LOCK_STATUS_ERROR_MAX = (__DPLL_LOCK_STATUS_ERROR_MAX - 1)
  72. };
  73. #define DPLL_TEMP_DIVIDER 1000
  74. /**
  75. * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute
  76. * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal
  77. * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock
  78. */
  79. enum dpll_type {
  80. DPLL_TYPE_PPS = 1,
  81. DPLL_TYPE_EEC,
  82. /* private: */
  83. __DPLL_TYPE_MAX,
  84. DPLL_TYPE_MAX = (__DPLL_TYPE_MAX - 1)
  85. };
  86. /**
  87. * enum dpll_pin_type - defines possible types of a pin, valid values for
  88. * DPLL_A_PIN_TYPE attribute
  89. * @DPLL_PIN_TYPE_MUX: aggregates another layer of selectable pins
  90. * @DPLL_PIN_TYPE_EXT: external input
  91. * @DPLL_PIN_TYPE_SYNCE_ETH_PORT: ethernet port PHY's recovered clock
  92. * @DPLL_PIN_TYPE_INT_OSCILLATOR: device internal oscillator
  93. * @DPLL_PIN_TYPE_GNSS: GNSS recovered clock
  94. */
  95. enum dpll_pin_type {
  96. DPLL_PIN_TYPE_MUX = 1,
  97. DPLL_PIN_TYPE_EXT,
  98. DPLL_PIN_TYPE_SYNCE_ETH_PORT,
  99. DPLL_PIN_TYPE_INT_OSCILLATOR,
  100. DPLL_PIN_TYPE_GNSS,
  101. /* private: */
  102. __DPLL_PIN_TYPE_MAX,
  103. DPLL_PIN_TYPE_MAX = (__DPLL_PIN_TYPE_MAX - 1)
  104. };
  105. /**
  106. * enum dpll_pin_direction - defines possible direction of a pin, valid values
  107. * for DPLL_A_PIN_DIRECTION attribute
  108. * @DPLL_PIN_DIRECTION_INPUT: pin used as a input of a signal
  109. * @DPLL_PIN_DIRECTION_OUTPUT: pin used to output the signal
  110. */
  111. enum dpll_pin_direction {
  112. DPLL_PIN_DIRECTION_INPUT = 1,
  113. DPLL_PIN_DIRECTION_OUTPUT,
  114. /* private: */
  115. __DPLL_PIN_DIRECTION_MAX,
  116. DPLL_PIN_DIRECTION_MAX = (__DPLL_PIN_DIRECTION_MAX - 1)
  117. };
  118. #define DPLL_PIN_FREQUENCY_1_HZ 1
  119. #define DPLL_PIN_FREQUENCY_10_KHZ 10000
  120. #define DPLL_PIN_FREQUENCY_77_5_KHZ 77500
  121. #define DPLL_PIN_FREQUENCY_10_MHZ 10000000
  122. /**
  123. * enum dpll_pin_state - defines possible states of a pin, valid values for
  124. * DPLL_A_PIN_STATE attribute
  125. * @DPLL_PIN_STATE_CONNECTED: pin connected, active input of phase locked loop
  126. * @DPLL_PIN_STATE_DISCONNECTED: pin disconnected, not considered as a valid
  127. * input
  128. * @DPLL_PIN_STATE_SELECTABLE: pin enabled for automatic input selection
  129. */
  130. enum dpll_pin_state {
  131. DPLL_PIN_STATE_CONNECTED = 1,
  132. DPLL_PIN_STATE_DISCONNECTED,
  133. DPLL_PIN_STATE_SELECTABLE,
  134. /* private: */
  135. __DPLL_PIN_STATE_MAX,
  136. DPLL_PIN_STATE_MAX = (__DPLL_PIN_STATE_MAX - 1)
  137. };
  138. /**
  139. * enum dpll_pin_capabilities - defines possible capabilities of a pin, valid
  140. * flags on DPLL_A_PIN_CAPABILITIES attribute
  141. * @DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE: pin direction can be changed
  142. * @DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE: pin priority can be changed
  143. * @DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE: pin state can be changed
  144. */
  145. enum dpll_pin_capabilities {
  146. DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE = 1,
  147. DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE = 2,
  148. DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE = 4,
  149. };
  150. #define DPLL_PHASE_OFFSET_DIVIDER 1000
  151. enum dpll_a {
  152. DPLL_A_ID = 1,
  153. DPLL_A_MODULE_NAME,
  154. DPLL_A_PAD,
  155. DPLL_A_CLOCK_ID,
  156. DPLL_A_MODE,
  157. DPLL_A_MODE_SUPPORTED,
  158. DPLL_A_LOCK_STATUS,
  159. DPLL_A_TEMP,
  160. DPLL_A_TYPE,
  161. DPLL_A_LOCK_STATUS_ERROR,
  162. __DPLL_A_MAX,
  163. DPLL_A_MAX = (__DPLL_A_MAX - 1)
  164. };
  165. enum dpll_a_pin {
  166. DPLL_A_PIN_ID = 1,
  167. DPLL_A_PIN_PARENT_ID,
  168. DPLL_A_PIN_MODULE_NAME,
  169. DPLL_A_PIN_PAD,
  170. DPLL_A_PIN_CLOCK_ID,
  171. DPLL_A_PIN_BOARD_LABEL,
  172. DPLL_A_PIN_PANEL_LABEL,
  173. DPLL_A_PIN_PACKAGE_LABEL,
  174. DPLL_A_PIN_TYPE,
  175. DPLL_A_PIN_DIRECTION,
  176. DPLL_A_PIN_FREQUENCY,
  177. DPLL_A_PIN_FREQUENCY_SUPPORTED,
  178. DPLL_A_PIN_FREQUENCY_MIN,
  179. DPLL_A_PIN_FREQUENCY_MAX,
  180. DPLL_A_PIN_PRIO,
  181. DPLL_A_PIN_STATE,
  182. DPLL_A_PIN_CAPABILITIES,
  183. DPLL_A_PIN_PARENT_DEVICE,
  184. DPLL_A_PIN_PARENT_PIN,
  185. DPLL_A_PIN_PHASE_ADJUST_MIN,
  186. DPLL_A_PIN_PHASE_ADJUST_MAX,
  187. DPLL_A_PIN_PHASE_ADJUST,
  188. DPLL_A_PIN_PHASE_OFFSET,
  189. DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET,
  190. DPLL_A_PIN_ESYNC_FREQUENCY,
  191. DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
  192. DPLL_A_PIN_ESYNC_PULSE,
  193. __DPLL_A_PIN_MAX,
  194. DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)
  195. };
  196. enum dpll_cmd {
  197. DPLL_CMD_DEVICE_ID_GET = 1,
  198. DPLL_CMD_DEVICE_GET,
  199. DPLL_CMD_DEVICE_SET,
  200. DPLL_CMD_DEVICE_CREATE_NTF,
  201. DPLL_CMD_DEVICE_DELETE_NTF,
  202. DPLL_CMD_DEVICE_CHANGE_NTF,
  203. DPLL_CMD_PIN_ID_GET,
  204. DPLL_CMD_PIN_GET,
  205. DPLL_CMD_PIN_SET,
  206. DPLL_CMD_PIN_CREATE_NTF,
  207. DPLL_CMD_PIN_DELETE_NTF,
  208. DPLL_CMD_PIN_CHANGE_NTF,
  209. __DPLL_CMD_MAX,
  210. DPLL_CMD_MAX = (__DPLL_CMD_MAX - 1)
  211. };
  212. #define DPLL_MCGRP_MONITOR "monitor"
  213. #endif /* _LINUX_DPLL_H */