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oasis-root

Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

xe_drm.h (57595B)


  1. /* SPDX-License-Identifier: MIT */
  2. /*
  3. * Copyright © 2023 Intel Corporation
  4. */
  5. #ifndef _XE_DRM_H_
  6. #define _XE_DRM_H_
  7. #include "drm.h"
  8. #if defined(__cplusplus)
  9. extern "C" {
  10. #endif
  11. /*
  12. * Please note that modifications to all structs defined here are
  13. * subject to backwards-compatibility constraints.
  14. * Sections in this file are organized as follows:
  15. * 1. IOCTL definition
  16. * 2. Extension definition and helper structs
  17. * 3. IOCTL's Query structs in the order of the Query's entries.
  18. * 4. The rest of IOCTL structs in the order of IOCTL declaration.
  19. */
  20. /**
  21. * DOC: Xe Device Block Diagram
  22. *
  23. * The diagram below represents a high-level simplification of a discrete
  24. * GPU supported by the Xe driver. It shows some device components which
  25. * are necessary to understand this API, as well as how their relations
  26. * to each other. This diagram does not represent real hardware::
  27. *
  28. * ┌──────────────────────────────────────────────────────────────────┐
  29. * │ ┌──────────────────────────────────────────────────┐ ┌─────────┐ │
  30. * │ │ ┌───────────────────────┐ ┌─────┐ │ │ ┌─────┐ │ │
  31. * │ │ │ VRAM0 ├───┤ ... │ │ │ │VRAM1│ │ │
  32. * │ │ └───────────┬───────────┘ └─GT1─┘ │ │ └──┬──┘ │ │
  33. * │ │ ┌──────────────────┴───────────────────────────┐ │ │ ┌──┴──┐ │ │
  34. * │ │ │ ┌─────────────────────┐ ┌─────────────────┐ │ │ │ │ │ │ │
  35. * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
  36. * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │RCS0 │ │BCS0 │ │ │ │ │ │ │ │ │
  37. * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
  38. * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
  39. * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VCS0 │ │VCS1 │ │ │ │ │ │ │ │ │
  40. * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
  41. * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
  42. * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │VECS0│ │VECS1│ │ │ │ │ │ ... │ │ │
  43. * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
  44. * │ │ │ │ ┌──┐ ┌──┐ ┌──┐ ┌──┐ │ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
  45. * │ │ │ │ │EU│ │EU│ │EU│ │EU│ │ │ │CCS0 │ │CCS1 │ │ │ │ │ │ │ │ │
  46. * │ │ │ │ └──┘ └──┘ └──┘ └──┘ │ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
  47. * │ │ │ └─────────DSS─────────┘ │ ┌─────┐ ┌─────┐ │ │ │ │ │ │ │ │
  48. * │ │ │ │ │CCS2 │ │CCS3 │ │ │ │ │ │ │ │ │
  49. * │ │ │ ┌─────┐ ┌─────┐ ┌─────┐ │ └─────┘ └─────┘ │ │ │ │ │ │ │ │
  50. * │ │ │ │ ... │ │ ... │ │ ... │ │ │ │ │ │ │ │ │ │
  51. * │ │ │ └─DSS─┘ └─DSS─┘ └─DSS─┘ └─────Engines─────┘ │ │ │ │ │ │ │
  52. * │ │ └───────────────────────────GT0────────────────┘ │ │ └─GT2─┘ │ │
  53. * │ └────────────────────────────Tile0─────────────────┘ └─ Tile1──┘ │
  54. * └─────────────────────────────Device0───────┬──────────────────────┘
  55. * │
  56. * ───────────────────────┴────────── PCI bus
  57. */
  58. /**
  59. * DOC: Xe uAPI Overview
  60. *
  61. * This section aims to describe the Xe's IOCTL entries, its structs, and other
  62. * Xe related uAPI such as uevents and PMU (Platform Monitoring Unit) related
  63. * entries and usage.
  64. *
  65. * List of supported IOCTLs:
  66. * - &DRM_IOCTL_XE_DEVICE_QUERY
  67. * - &DRM_IOCTL_XE_GEM_CREATE
  68. * - &DRM_IOCTL_XE_GEM_MMAP_OFFSET
  69. * - &DRM_IOCTL_XE_VM_CREATE
  70. * - &DRM_IOCTL_XE_VM_DESTROY
  71. * - &DRM_IOCTL_XE_VM_BIND
  72. * - &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
  73. * - &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
  74. * - &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
  75. * - &DRM_IOCTL_XE_EXEC
  76. * - &DRM_IOCTL_XE_WAIT_USER_FENCE
  77. * - &DRM_IOCTL_XE_OBSERVATION
  78. */
  79. /*
  80. * xe specific ioctls.
  81. *
  82. * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
  83. * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
  84. * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
  85. */
  86. #define DRM_XE_DEVICE_QUERY 0x00
  87. #define DRM_XE_GEM_CREATE 0x01
  88. #define DRM_XE_GEM_MMAP_OFFSET 0x02
  89. #define DRM_XE_VM_CREATE 0x03
  90. #define DRM_XE_VM_DESTROY 0x04
  91. #define DRM_XE_VM_BIND 0x05
  92. #define DRM_XE_EXEC_QUEUE_CREATE 0x06
  93. #define DRM_XE_EXEC_QUEUE_DESTROY 0x07
  94. #define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x08
  95. #define DRM_XE_EXEC 0x09
  96. #define DRM_XE_WAIT_USER_FENCE 0x0a
  97. #define DRM_XE_OBSERVATION 0x0b
  98. /* Must be kept compact -- no holes */
  99. #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query)
  100. #define DRM_IOCTL_XE_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_CREATE, struct drm_xe_gem_create)
  101. #define DRM_IOCTL_XE_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_GEM_MMAP_OFFSET, struct drm_xe_gem_mmap_offset)
  102. #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create)
  103. #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy)
  104. #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind)
  105. #define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create)
  106. #define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy)
  107. #define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property)
  108. #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec)
  109. #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence)
  110. #define DRM_IOCTL_XE_OBSERVATION DRM_IOW(DRM_COMMAND_BASE + DRM_XE_OBSERVATION, struct drm_xe_observation_param)
  111. /**
  112. * DOC: Xe IOCTL Extensions
  113. *
  114. * Before detailing the IOCTLs and its structs, it is important to highlight
  115. * that every IOCTL in Xe is extensible.
  116. *
  117. * Many interfaces need to grow over time. In most cases we can simply
  118. * extend the struct and have userspace pass in more data. Another option,
  119. * as demonstrated by Vulkan's approach to providing extensions for forward
  120. * and backward compatibility, is to use a list of optional structs to
  121. * provide those extra details.
  122. *
  123. * The key advantage to using an extension chain is that it allows us to
  124. * redefine the interface more easily than an ever growing struct of
  125. * increasing complexity, and for large parts of that interface to be
  126. * entirely optional. The downside is more pointer chasing; chasing across
  127. * the boundary with pointers encapsulated inside u64.
  128. *
  129. * Example chaining:
  130. *
  131. * .. code-block:: C
  132. *
  133. * struct drm_xe_user_extension ext3 {
  134. * .next_extension = 0, // end
  135. * .name = ...,
  136. * };
  137. * struct drm_xe_user_extension ext2 {
  138. * .next_extension = (uintptr_t)&ext3,
  139. * .name = ...,
  140. * };
  141. * struct drm_xe_user_extension ext1 {
  142. * .next_extension = (uintptr_t)&ext2,
  143. * .name = ...,
  144. * };
  145. *
  146. * Typically the struct drm_xe_user_extension would be embedded in some uAPI
  147. * struct, and in this case we would feed it the head of the chain(i.e ext1),
  148. * which would then apply all of the above extensions.
  149. */
  150. /**
  151. * struct drm_xe_user_extension - Base class for defining a chain of extensions
  152. */
  153. struct drm_xe_user_extension {
  154. /**
  155. * @next_extension:
  156. *
  157. * Pointer to the next struct drm_xe_user_extension, or zero if the end.
  158. */
  159. __u64 next_extension;
  160. /**
  161. * @name: Name of the extension.
  162. *
  163. * Note that the name here is just some integer.
  164. *
  165. * Also note that the name space for this is not global for the whole
  166. * driver, but rather its scope/meaning is limited to the specific piece
  167. * of uAPI which has embedded the struct drm_xe_user_extension.
  168. */
  169. __u32 name;
  170. /**
  171. * @pad: MBZ
  172. *
  173. * All undefined bits must be zero.
  174. */
  175. __u32 pad;
  176. };
  177. /**
  178. * struct drm_xe_ext_set_property - Generic set property extension
  179. *
  180. * A generic struct that allows any of the Xe's IOCTL to be extended
  181. * with a set_property operation.
  182. */
  183. struct drm_xe_ext_set_property {
  184. /** @base: base user extension */
  185. struct drm_xe_user_extension base;
  186. /** @property: property to set */
  187. __u32 property;
  188. /** @pad: MBZ */
  189. __u32 pad;
  190. /** @value: property value */
  191. __u64 value;
  192. /** @reserved: Reserved */
  193. __u64 reserved[2];
  194. };
  195. /**
  196. * struct drm_xe_engine_class_instance - instance of an engine class
  197. *
  198. * It is returned as part of the @drm_xe_engine, but it also is used as
  199. * the input of engine selection for both @drm_xe_exec_queue_create and
  200. * @drm_xe_query_engine_cycles
  201. *
  202. * The @engine_class can be:
  203. * - %DRM_XE_ENGINE_CLASS_RENDER
  204. * - %DRM_XE_ENGINE_CLASS_COPY
  205. * - %DRM_XE_ENGINE_CLASS_VIDEO_DECODE
  206. * - %DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE
  207. * - %DRM_XE_ENGINE_CLASS_COMPUTE
  208. * - %DRM_XE_ENGINE_CLASS_VM_BIND - Kernel only classes (not actual
  209. * hardware engine class). Used for creating ordered queues of VM
  210. * bind operations.
  211. */
  212. struct drm_xe_engine_class_instance {
  213. #define DRM_XE_ENGINE_CLASS_RENDER 0
  214. #define DRM_XE_ENGINE_CLASS_COPY 1
  215. #define DRM_XE_ENGINE_CLASS_VIDEO_DECODE 2
  216. #define DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE 3
  217. #define DRM_XE_ENGINE_CLASS_COMPUTE 4
  218. #define DRM_XE_ENGINE_CLASS_VM_BIND 5
  219. /** @engine_class: engine class id */
  220. __u16 engine_class;
  221. /** @engine_instance: engine instance id */
  222. __u16 engine_instance;
  223. /** @gt_id: Unique ID of this GT within the PCI Device */
  224. __u16 gt_id;
  225. /** @pad: MBZ */
  226. __u16 pad;
  227. };
  228. /**
  229. * struct drm_xe_engine - describe hardware engine
  230. */
  231. struct drm_xe_engine {
  232. /** @instance: The @drm_xe_engine_class_instance */
  233. struct drm_xe_engine_class_instance instance;
  234. /** @reserved: Reserved */
  235. __u64 reserved[3];
  236. };
  237. /**
  238. * struct drm_xe_query_engines - describe engines
  239. *
  240. * If a query is made with a struct @drm_xe_device_query where .query
  241. * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of
  242. * struct @drm_xe_query_engines in .data.
  243. */
  244. struct drm_xe_query_engines {
  245. /** @num_engines: number of engines returned in @engines */
  246. __u32 num_engines;
  247. /** @pad: MBZ */
  248. __u32 pad;
  249. /** @engines: The returned engines for this device */
  250. struct drm_xe_engine engines[];
  251. };
  252. /**
  253. * enum drm_xe_memory_class - Supported memory classes.
  254. */
  255. enum drm_xe_memory_class {
  256. /** @DRM_XE_MEM_REGION_CLASS_SYSMEM: Represents system memory. */
  257. DRM_XE_MEM_REGION_CLASS_SYSMEM = 0,
  258. /**
  259. * @DRM_XE_MEM_REGION_CLASS_VRAM: On discrete platforms, this
  260. * represents the memory that is local to the device, which we
  261. * call VRAM. Not valid on integrated platforms.
  262. */
  263. DRM_XE_MEM_REGION_CLASS_VRAM
  264. };
  265. /**
  266. * struct drm_xe_mem_region - Describes some region as known to
  267. * the driver.
  268. */
  269. struct drm_xe_mem_region {
  270. /**
  271. * @mem_class: The memory class describing this region.
  272. *
  273. * See enum drm_xe_memory_class for supported values.
  274. */
  275. __u16 mem_class;
  276. /**
  277. * @instance: The unique ID for this region, which serves as the
  278. * index in the placement bitmask used as argument for
  279. * &DRM_IOCTL_XE_GEM_CREATE
  280. */
  281. __u16 instance;
  282. /**
  283. * @min_page_size: Min page-size in bytes for this region.
  284. *
  285. * When the kernel allocates memory for this region, the
  286. * underlying pages will be at least @min_page_size in size.
  287. * Buffer objects with an allowable placement in this region must be
  288. * created with a size aligned to this value.
  289. * GPU virtual address mappings of (parts of) buffer objects that
  290. * may be placed in this region must also have their GPU virtual
  291. * address and range aligned to this value.
  292. * Affected IOCTLS will return %-EINVAL if alignment restrictions are
  293. * not met.
  294. */
  295. __u32 min_page_size;
  296. /**
  297. * @total_size: The usable size in bytes for this region.
  298. */
  299. __u64 total_size;
  300. /**
  301. * @used: Estimate of the memory used in bytes for this region.
  302. *
  303. * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
  304. * accounting. Without this the value here will always equal
  305. * zero.
  306. */
  307. __u64 used;
  308. /**
  309. * @cpu_visible_size: How much of this region can be CPU
  310. * accessed, in bytes.
  311. *
  312. * This will always be <= @total_size, and the remainder (if
  313. * any) will not be CPU accessible. If the CPU accessible part
  314. * is smaller than @total_size then this is referred to as a
  315. * small BAR system.
  316. *
  317. * On systems without small BAR (full BAR), the probed_size will
  318. * always equal the @total_size, since all of it will be CPU
  319. * accessible.
  320. *
  321. * Note this is only tracked for DRM_XE_MEM_REGION_CLASS_VRAM
  322. * regions (for other types the value here will always equal
  323. * zero).
  324. */
  325. __u64 cpu_visible_size;
  326. /**
  327. * @cpu_visible_used: Estimate of CPU visible memory used, in
  328. * bytes.
  329. *
  330. * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
  331. * accounting. Without this the value here will always equal
  332. * zero. Note this is only currently tracked for
  333. * DRM_XE_MEM_REGION_CLASS_VRAM regions (for other types the value
  334. * here will always be zero).
  335. */
  336. __u64 cpu_visible_used;
  337. /** @reserved: Reserved */
  338. __u64 reserved[6];
  339. };
  340. /**
  341. * struct drm_xe_query_mem_regions - describe memory regions
  342. *
  343. * If a query is made with a struct drm_xe_device_query where .query
  344. * is equal to DRM_XE_DEVICE_QUERY_MEM_REGIONS, then the reply uses
  345. * struct drm_xe_query_mem_regions in .data.
  346. */
  347. struct drm_xe_query_mem_regions {
  348. /** @num_mem_regions: number of memory regions returned in @mem_regions */
  349. __u32 num_mem_regions;
  350. /** @pad: MBZ */
  351. __u32 pad;
  352. /** @mem_regions: The returned memory regions for this device */
  353. struct drm_xe_mem_region mem_regions[];
  354. };
  355. /**
  356. * struct drm_xe_query_config - describe the device configuration
  357. *
  358. * If a query is made with a struct drm_xe_device_query where .query
  359. * is equal to DRM_XE_DEVICE_QUERY_CONFIG, then the reply uses
  360. * struct drm_xe_query_config in .data.
  361. *
  362. * The index in @info can be:
  363. * - %DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID - Device ID (lower 16 bits)
  364. * and the device revision (next 8 bits)
  365. * - %DRM_XE_QUERY_CONFIG_FLAGS - Flags describing the device
  366. * configuration, see list below
  367. *
  368. * - %DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM - Flag is set if the device
  369. * has usable VRAM
  370. * - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
  371. * required by this device, typically SZ_4K or SZ_64K
  372. * - %DRM_XE_QUERY_CONFIG_VA_BITS - Maximum bits of a virtual address
  373. * - %DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY - Value of the highest
  374. * available exec queue priority
  375. */
  376. struct drm_xe_query_config {
  377. /** @num_params: number of parameters returned in info */
  378. __u32 num_params;
  379. /** @pad: MBZ */
  380. __u32 pad;
  381. #define DRM_XE_QUERY_CONFIG_REV_AND_DEVICE_ID 0
  382. #define DRM_XE_QUERY_CONFIG_FLAGS 1
  383. #define DRM_XE_QUERY_CONFIG_FLAG_HAS_VRAM (1 << 0)
  384. #define DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT 2
  385. #define DRM_XE_QUERY_CONFIG_VA_BITS 3
  386. #define DRM_XE_QUERY_CONFIG_MAX_EXEC_QUEUE_PRIORITY 4
  387. /** @info: array of elements containing the config info */
  388. __u64 info[];
  389. };
  390. /**
  391. * struct drm_xe_gt - describe an individual GT.
  392. *
  393. * To be used with drm_xe_query_gt_list, which will return a list with all the
  394. * existing GT individual descriptions.
  395. * Graphics Technology (GT) is a subset of a GPU/tile that is responsible for
  396. * implementing graphics and/or media operations.
  397. *
  398. * The index in @type can be:
  399. * - %DRM_XE_QUERY_GT_TYPE_MAIN
  400. * - %DRM_XE_QUERY_GT_TYPE_MEDIA
  401. */
  402. struct drm_xe_gt {
  403. #define DRM_XE_QUERY_GT_TYPE_MAIN 0
  404. #define DRM_XE_QUERY_GT_TYPE_MEDIA 1
  405. /** @type: GT type: Main or Media */
  406. __u16 type;
  407. /** @tile_id: Tile ID where this GT lives (Information only) */
  408. __u16 tile_id;
  409. /** @gt_id: Unique ID of this GT within the PCI Device */
  410. __u16 gt_id;
  411. /** @pad: MBZ */
  412. __u16 pad[3];
  413. /** @reference_clock: A clock frequency for timestamp */
  414. __u32 reference_clock;
  415. /**
  416. * @near_mem_regions: Bit mask of instances from
  417. * drm_xe_query_mem_regions that are nearest to the current engines
  418. * of this GT.
  419. * Each index in this mask refers directly to the struct
  420. * drm_xe_query_mem_regions' instance, no assumptions should
  421. * be made about order. The type of each region is described
  422. * by struct drm_xe_query_mem_regions' mem_class.
  423. */
  424. __u64 near_mem_regions;
  425. /**
  426. * @far_mem_regions: Bit mask of instances from
  427. * drm_xe_query_mem_regions that are far from the engines of this GT.
  428. * In general, they have extra indirections when compared to the
  429. * @near_mem_regions. For a discrete device this could mean system
  430. * memory and memory living in a different tile.
  431. * Each index in this mask refers directly to the struct
  432. * drm_xe_query_mem_regions' instance, no assumptions should
  433. * be made about order. The type of each region is described
  434. * by struct drm_xe_query_mem_regions' mem_class.
  435. */
  436. __u64 far_mem_regions;
  437. /** @ip_ver_major: Graphics/media IP major version on GMD_ID platforms */
  438. __u16 ip_ver_major;
  439. /** @ip_ver_minor: Graphics/media IP minor version on GMD_ID platforms */
  440. __u16 ip_ver_minor;
  441. /** @ip_ver_rev: Graphics/media IP revision version on GMD_ID platforms */
  442. __u16 ip_ver_rev;
  443. /** @pad2: MBZ */
  444. __u16 pad2;
  445. /** @reserved: Reserved */
  446. __u64 reserved[7];
  447. };
  448. /**
  449. * struct drm_xe_query_gt_list - A list with GT description items.
  450. *
  451. * If a query is made with a struct drm_xe_device_query where .query
  452. * is equal to DRM_XE_DEVICE_QUERY_GT_LIST, then the reply uses struct
  453. * drm_xe_query_gt_list in .data.
  454. */
  455. struct drm_xe_query_gt_list {
  456. /** @num_gt: number of GT items returned in gt_list */
  457. __u32 num_gt;
  458. /** @pad: MBZ */
  459. __u32 pad;
  460. /** @gt_list: The GT list returned for this device */
  461. struct drm_xe_gt gt_list[];
  462. };
  463. /**
  464. * struct drm_xe_query_topology_mask - describe the topology mask of a GT
  465. *
  466. * This is the hardware topology which reflects the internal physical
  467. * structure of the GPU.
  468. *
  469. * If a query is made with a struct drm_xe_device_query where .query
  470. * is equal to DRM_XE_DEVICE_QUERY_GT_TOPOLOGY, then the reply uses
  471. * struct drm_xe_query_topology_mask in .data.
  472. *
  473. * The @type can be:
  474. * - %DRM_XE_TOPO_DSS_GEOMETRY - To query the mask of Dual Sub Slices
  475. * (DSS) available for geometry operations. For example a query response
  476. * containing the following in mask:
  477. * ``DSS_GEOMETRY ff ff ff ff 00 00 00 00``
  478. * means 32 DSS are available for geometry.
  479. * - %DRM_XE_TOPO_DSS_COMPUTE - To query the mask of Dual Sub Slices
  480. * (DSS) available for compute operations. For example a query response
  481. * containing the following in mask:
  482. * ``DSS_COMPUTE ff ff ff ff 00 00 00 00``
  483. * means 32 DSS are available for compute.
  484. * - %DRM_XE_TOPO_L3_BANK - To query the mask of enabled L3 banks
  485. * - %DRM_XE_TOPO_EU_PER_DSS - To query the mask of Execution Units (EU)
  486. * available per Dual Sub Slices (DSS). For example a query response
  487. * containing the following in mask:
  488. * ``EU_PER_DSS ff ff 00 00 00 00 00 00``
  489. * means each DSS has 16 SIMD8 EUs. This type may be omitted if device
  490. * doesn't have SIMD8 EUs.
  491. * - %DRM_XE_TOPO_SIMD16_EU_PER_DSS - To query the mask of SIMD16 Execution
  492. * Units (EU) available per Dual Sub Slices (DSS). For example a query
  493. * response containing the following in mask:
  494. * ``SIMD16_EU_PER_DSS ff ff 00 00 00 00 00 00``
  495. * means each DSS has 16 SIMD16 EUs. This type may be omitted if device
  496. * doesn't have SIMD16 EUs.
  497. */
  498. struct drm_xe_query_topology_mask {
  499. /** @gt_id: GT ID the mask is associated with */
  500. __u16 gt_id;
  501. #define DRM_XE_TOPO_DSS_GEOMETRY 1
  502. #define DRM_XE_TOPO_DSS_COMPUTE 2
  503. #define DRM_XE_TOPO_L3_BANK 3
  504. #define DRM_XE_TOPO_EU_PER_DSS 4
  505. #define DRM_XE_TOPO_SIMD16_EU_PER_DSS 5
  506. /** @type: type of mask */
  507. __u16 type;
  508. /** @num_bytes: number of bytes in requested mask */
  509. __u32 num_bytes;
  510. /** @mask: little-endian mask of @num_bytes */
  511. __u8 mask[];
  512. };
  513. /**
  514. * struct drm_xe_query_engine_cycles - correlate CPU and GPU timestamps
  515. *
  516. * If a query is made with a struct drm_xe_device_query where .query is equal to
  517. * DRM_XE_DEVICE_QUERY_ENGINE_CYCLES, then the reply uses struct drm_xe_query_engine_cycles
  518. * in .data. struct drm_xe_query_engine_cycles is allocated by the user and
  519. * .data points to this allocated structure.
  520. *
  521. * The query returns the engine cycles, which along with GT's @reference_clock,
  522. * can be used to calculate the engine timestamp. In addition the
  523. * query returns a set of cpu timestamps that indicate when the command
  524. * streamer cycle count was captured.
  525. */
  526. struct drm_xe_query_engine_cycles {
  527. /**
  528. * @eci: This is input by the user and is the engine for which command
  529. * streamer cycles is queried.
  530. */
  531. struct drm_xe_engine_class_instance eci;
  532. /**
  533. * @clockid: This is input by the user and is the reference clock id for
  534. * CPU timestamp. For definition, see clock_gettime(2) and
  535. * perf_event_open(2). Supported clock ids are CLOCK_MONOTONIC,
  536. * CLOCK_MONOTONIC_RAW, CLOCK_REALTIME, CLOCK_BOOTTIME, CLOCK_TAI.
  537. */
  538. __s32 clockid;
  539. /** @width: Width of the engine cycle counter in bits. */
  540. __u32 width;
  541. /**
  542. * @engine_cycles: Engine cycles as read from its register
  543. * at 0x358 offset.
  544. */
  545. __u64 engine_cycles;
  546. /**
  547. * @cpu_timestamp: CPU timestamp in ns. The timestamp is captured before
  548. * reading the engine_cycles register using the reference clockid set by the
  549. * user.
  550. */
  551. __u64 cpu_timestamp;
  552. /**
  553. * @cpu_delta: Time delta in ns captured around reading the lower dword
  554. * of the engine_cycles register.
  555. */
  556. __u64 cpu_delta;
  557. };
  558. /**
  559. * struct drm_xe_query_uc_fw_version - query a micro-controller firmware version
  560. *
  561. * Given a uc_type this will return the branch, major, minor and patch version
  562. * of the micro-controller firmware.
  563. */
  564. struct drm_xe_query_uc_fw_version {
  565. /** @uc_type: The micro-controller type to query firmware version */
  566. #define XE_QUERY_UC_TYPE_GUC_SUBMISSION 0
  567. #define XE_QUERY_UC_TYPE_HUC 1
  568. __u16 uc_type;
  569. /** @pad: MBZ */
  570. __u16 pad;
  571. /** @branch_ver: branch uc fw version */
  572. __u32 branch_ver;
  573. /** @major_ver: major uc fw version */
  574. __u32 major_ver;
  575. /** @minor_ver: minor uc fw version */
  576. __u32 minor_ver;
  577. /** @patch_ver: patch uc fw version */
  578. __u32 patch_ver;
  579. /** @pad2: MBZ */
  580. __u32 pad2;
  581. /** @reserved: Reserved */
  582. __u64 reserved;
  583. };
  584. /**
  585. * struct drm_xe_device_query - Input of &DRM_IOCTL_XE_DEVICE_QUERY - main
  586. * structure to query device information
  587. *
  588. * The user selects the type of data to query among DRM_XE_DEVICE_QUERY_*
  589. * and sets the value in the query member. This determines the type of
  590. * the structure provided by the driver in data, among struct drm_xe_query_*.
  591. *
  592. * The @query can be:
  593. * - %DRM_XE_DEVICE_QUERY_ENGINES
  594. * - %DRM_XE_DEVICE_QUERY_MEM_REGIONS
  595. * - %DRM_XE_DEVICE_QUERY_CONFIG
  596. * - %DRM_XE_DEVICE_QUERY_GT_LIST
  597. * - %DRM_XE_DEVICE_QUERY_HWCONFIG - Query type to retrieve the hardware
  598. * configuration of the device such as information on slices, memory,
  599. * caches, and so on. It is provided as a table of key / value
  600. * attributes.
  601. * - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
  602. * - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
  603. *
  604. * If size is set to 0, the driver fills it with the required size for
  605. * the requested type of data to query. If size is equal to the required
  606. * size, the queried information is copied into data. If size is set to
  607. * a value different from 0 and different from the required size, the
  608. * IOCTL call returns -EINVAL.
  609. *
  610. * For example the following code snippet allows retrieving and printing
  611. * information about the device engines with DRM_XE_DEVICE_QUERY_ENGINES:
  612. *
  613. * .. code-block:: C
  614. *
  615. * struct drm_xe_query_engines *engines;
  616. * struct drm_xe_device_query query = {
  617. * .extensions = 0,
  618. * .query = DRM_XE_DEVICE_QUERY_ENGINES,
  619. * .size = 0,
  620. * .data = 0,
  621. * };
  622. * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
  623. * engines = malloc(query.size);
  624. * query.data = (uintptr_t)engines;
  625. * ioctl(fd, DRM_IOCTL_XE_DEVICE_QUERY, &query);
  626. * for (int i = 0; i < engines->num_engines; i++) {
  627. * printf("Engine %d: %s\n", i,
  628. * engines->engines[i].instance.engine_class ==
  629. * DRM_XE_ENGINE_CLASS_RENDER ? "RENDER":
  630. * engines->engines[i].instance.engine_class ==
  631. * DRM_XE_ENGINE_CLASS_COPY ? "COPY":
  632. * engines->engines[i].instance.engine_class ==
  633. * DRM_XE_ENGINE_CLASS_VIDEO_DECODE ? "VIDEO_DECODE":
  634. * engines->engines[i].instance.engine_class ==
  635. * DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE ? "VIDEO_ENHANCE":
  636. * engines->engines[i].instance.engine_class ==
  637. * DRM_XE_ENGINE_CLASS_COMPUTE ? "COMPUTE":
  638. * "UNKNOWN");
  639. * }
  640. * free(engines);
  641. */
  642. struct drm_xe_device_query {
  643. /** @extensions: Pointer to the first extension struct, if any */
  644. __u64 extensions;
  645. #define DRM_XE_DEVICE_QUERY_ENGINES 0
  646. #define DRM_XE_DEVICE_QUERY_MEM_REGIONS 1
  647. #define DRM_XE_DEVICE_QUERY_CONFIG 2
  648. #define DRM_XE_DEVICE_QUERY_GT_LIST 3
  649. #define DRM_XE_DEVICE_QUERY_HWCONFIG 4
  650. #define DRM_XE_DEVICE_QUERY_GT_TOPOLOGY 5
  651. #define DRM_XE_DEVICE_QUERY_ENGINE_CYCLES 6
  652. #define DRM_XE_DEVICE_QUERY_UC_FW_VERSION 7
  653. #define DRM_XE_DEVICE_QUERY_OA_UNITS 8
  654. /** @query: The type of data to query */
  655. __u32 query;
  656. /** @size: Size of the queried data */
  657. __u32 size;
  658. /** @data: Queried data is placed here */
  659. __u64 data;
  660. /** @reserved: Reserved */
  661. __u64 reserved[2];
  662. };
  663. /**
  664. * struct drm_xe_gem_create - Input of &DRM_IOCTL_XE_GEM_CREATE - A structure for
  665. * gem creation
  666. *
  667. * The @flags can be:
  668. * - %DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING
  669. * - %DRM_XE_GEM_CREATE_FLAG_SCANOUT
  670. * - %DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM - When using VRAM as a
  671. * possible placement, ensure that the corresponding VRAM allocation
  672. * will always use the CPU accessible part of VRAM. This is important
  673. * for small-bar systems (on full-bar systems this gets turned into a
  674. * noop).
  675. * Note1: System memory can be used as an extra placement if the kernel
  676. * should spill the allocation to system memory, if space can't be made
  677. * available in the CPU accessible part of VRAM (giving the same
  678. * behaviour as the i915 interface, see
  679. * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS).
  680. * Note2: For clear-color CCS surfaces the kernel needs to read the
  681. * clear-color value stored in the buffer, and on discrete platforms we
  682. * need to use VRAM for display surfaces, therefore the kernel requires
  683. * setting this flag for such objects, otherwise an error is thrown on
  684. * small-bar systems.
  685. *
  686. * @cpu_caching supports the following values:
  687. * - %DRM_XE_GEM_CPU_CACHING_WB - Allocate the pages with write-back
  688. * caching. On iGPU this can't be used for scanout surfaces. Currently
  689. * not allowed for objects placed in VRAM.
  690. * - %DRM_XE_GEM_CPU_CACHING_WC - Allocate the pages as write-combined. This
  691. * is uncached. Scanout surfaces should likely use this. All objects
  692. * that can be placed in VRAM must use this.
  693. */
  694. struct drm_xe_gem_create {
  695. /** @extensions: Pointer to the first extension struct, if any */
  696. __u64 extensions;
  697. /**
  698. * @size: Size of the object to be created, must match region
  699. * (system or vram) minimum alignment (&min_page_size).
  700. */
  701. __u64 size;
  702. /**
  703. * @placement: A mask of memory instances of where BO can be placed.
  704. * Each index in this mask refers directly to the struct
  705. * drm_xe_query_mem_regions' instance, no assumptions should
  706. * be made about order. The type of each region is described
  707. * by struct drm_xe_query_mem_regions' mem_class.
  708. */
  709. __u32 placement;
  710. #define DRM_XE_GEM_CREATE_FLAG_DEFER_BACKING (1 << 0)
  711. #define DRM_XE_GEM_CREATE_FLAG_SCANOUT (1 << 1)
  712. #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM (1 << 2)
  713. /**
  714. * @flags: Flags, currently a mask of memory instances of where BO can
  715. * be placed
  716. */
  717. __u32 flags;
  718. /**
  719. * @vm_id: Attached VM, if any
  720. *
  721. * If a VM is specified, this BO must:
  722. *
  723. * 1. Only ever be bound to that VM.
  724. * 2. Cannot be exported as a PRIME fd.
  725. */
  726. __u32 vm_id;
  727. /**
  728. * @handle: Returned handle for the object.
  729. *
  730. * Object handles are nonzero.
  731. */
  732. __u32 handle;
  733. #define DRM_XE_GEM_CPU_CACHING_WB 1
  734. #define DRM_XE_GEM_CPU_CACHING_WC 2
  735. /**
  736. * @cpu_caching: The CPU caching mode to select for this object. If
  737. * mmaping the object the mode selected here will also be used. The
  738. * exception is when mapping system memory (including data evicted
  739. * to system) on discrete GPUs. The caching mode selected will
  740. * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
  741. * between GPU- and CPU is guaranteed. The caching mode of
  742. * existing CPU-mappings will be updated transparently to
  743. * user-space clients.
  744. */
  745. __u16 cpu_caching;
  746. /** @pad: MBZ */
  747. __u16 pad[3];
  748. /** @reserved: Reserved */
  749. __u64 reserved[2];
  750. };
  751. /**
  752. * struct drm_xe_gem_mmap_offset - Input of &DRM_IOCTL_XE_GEM_MMAP_OFFSET
  753. */
  754. struct drm_xe_gem_mmap_offset {
  755. /** @extensions: Pointer to the first extension struct, if any */
  756. __u64 extensions;
  757. /** @handle: Handle for the object being mapped. */
  758. __u32 handle;
  759. /** @flags: Must be zero */
  760. __u32 flags;
  761. /** @offset: The fake offset to use for subsequent mmap call */
  762. __u64 offset;
  763. /** @reserved: Reserved */
  764. __u64 reserved[2];
  765. };
  766. /**
  767. * struct drm_xe_vm_create - Input of &DRM_IOCTL_XE_VM_CREATE
  768. *
  769. * The @flags can be:
  770. * - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE
  771. * - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
  772. * exec submissions to its exec_queues that don't have an upper time
  773. * limit on the job execution time. But exec submissions to these
  774. * don't allow any of the flags DRM_XE_SYNC_FLAG_SYNCOBJ,
  775. * DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ, DRM_XE_SYNC_FLAG_DMA_BUF,
  776. * used as out-syncobjs, that is, together with DRM_XE_SYNC_FLAG_SIGNAL.
  777. * LR VMs can be created in recoverable page-fault mode using
  778. * DRM_XE_VM_CREATE_FLAG_FAULT_MODE, if the device supports it.
  779. * If that flag is omitted, the UMD can not rely on the slightly
  780. * different per-VM overcommit semantics that are enabled by
  781. * DRM_XE_VM_CREATE_FLAG_FAULT_MODE (see below), but KMD may
  782. * still enable recoverable pagefaults if supported by the device.
  783. * - %DRM_XE_VM_CREATE_FLAG_FAULT_MODE - Requires also
  784. * DRM_XE_VM_CREATE_FLAG_LR_MODE. It allows memory to be allocated on
  785. * demand when accessed, and also allows per-VM overcommit of memory.
  786. * The xe driver internally uses recoverable pagefaults to implement
  787. * this.
  788. */
  789. struct drm_xe_vm_create {
  790. /** @extensions: Pointer to the first extension struct, if any */
  791. __u64 extensions;
  792. #define DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE (1 << 0)
  793. #define DRM_XE_VM_CREATE_FLAG_LR_MODE (1 << 1)
  794. #define DRM_XE_VM_CREATE_FLAG_FAULT_MODE (1 << 2)
  795. /** @flags: Flags */
  796. __u32 flags;
  797. /** @vm_id: Returned VM ID */
  798. __u32 vm_id;
  799. /** @reserved: Reserved */
  800. __u64 reserved[2];
  801. };
  802. /**
  803. * struct drm_xe_vm_destroy - Input of &DRM_IOCTL_XE_VM_DESTROY
  804. */
  805. struct drm_xe_vm_destroy {
  806. /** @vm_id: VM ID */
  807. __u32 vm_id;
  808. /** @pad: MBZ */
  809. __u32 pad;
  810. /** @reserved: Reserved */
  811. __u64 reserved[2];
  812. };
  813. /**
  814. * struct drm_xe_vm_bind_op - run bind operations
  815. *
  816. * The @op can be:
  817. * - %DRM_XE_VM_BIND_OP_MAP
  818. * - %DRM_XE_VM_BIND_OP_UNMAP
  819. * - %DRM_XE_VM_BIND_OP_MAP_USERPTR
  820. * - %DRM_XE_VM_BIND_OP_UNMAP_ALL
  821. * - %DRM_XE_VM_BIND_OP_PREFETCH
  822. *
  823. * and the @flags can be:
  824. * - %DRM_XE_VM_BIND_FLAG_READONLY - Setup the page tables as read-only
  825. * to ensure write protection
  826. * - %DRM_XE_VM_BIND_FLAG_IMMEDIATE - On a faulting VM, do the
  827. * MAP operation immediately rather than deferring the MAP to the page
  828. * fault handler. This is implied on a non-faulting VM as there is no
  829. * fault handler to defer to.
  830. * - %DRM_XE_VM_BIND_FLAG_NULL - When the NULL flag is set, the page
  831. * tables are setup with a special bit which indicates writes are
  832. * dropped and all reads return zero. In the future, the NULL flags
  833. * will only be valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
  834. * handle MBZ, and the BO offset MBZ. This flag is intended to
  835. * implement VK sparse bindings.
  836. */
  837. struct drm_xe_vm_bind_op {
  838. /** @extensions: Pointer to the first extension struct, if any */
  839. __u64 extensions;
  840. /**
  841. * @obj: GEM object to operate on, MBZ for MAP_USERPTR, MBZ for UNMAP
  842. */
  843. __u32 obj;
  844. /**
  845. * @pat_index: The platform defined @pat_index to use for this mapping.
  846. * The index basically maps to some predefined memory attributes,
  847. * including things like caching, coherency, compression etc. The exact
  848. * meaning of the pat_index is platform specific and defined in the
  849. * Bspec and PRMs. When the KMD sets up the binding the index here is
  850. * encoded into the ppGTT PTE.
  851. *
  852. * For coherency the @pat_index needs to be at least 1way coherent when
  853. * drm_xe_gem_create.cpu_caching is DRM_XE_GEM_CPU_CACHING_WB. The KMD
  854. * will extract the coherency mode from the @pat_index and reject if
  855. * there is a mismatch (see note below for pre-MTL platforms).
  856. *
  857. * Note: On pre-MTL platforms there is only a caching mode and no
  858. * explicit coherency mode, but on such hardware there is always a
  859. * shared-LLC (or is dgpu) so all GT memory accesses are coherent with
  860. * CPU caches even with the caching mode set as uncached. It's only the
  861. * display engine that is incoherent (on dgpu it must be in VRAM which
  862. * is always mapped as WC on the CPU). However to keep the uapi somewhat
  863. * consistent with newer platforms the KMD groups the different cache
  864. * levels into the following coherency buckets on all pre-MTL platforms:
  865. *
  866. * ppGTT UC -> COH_NONE
  867. * ppGTT WC -> COH_NONE
  868. * ppGTT WT -> COH_NONE
  869. * ppGTT WB -> COH_AT_LEAST_1WAY
  870. *
  871. * In practice UC/WC/WT should only ever used for scanout surfaces on
  872. * such platforms (or perhaps in general for dma-buf if shared with
  873. * another device) since it is only the display engine that is actually
  874. * incoherent. Everything else should typically use WB given that we
  875. * have a shared-LLC. On MTL+ this completely changes and the HW
  876. * defines the coherency mode as part of the @pat_index, where
  877. * incoherent GT access is possible.
  878. *
  879. * Note: For userptr and externally imported dma-buf the kernel expects
  880. * either 1WAY or 2WAY for the @pat_index.
  881. *
  882. * For DRM_XE_VM_BIND_FLAG_NULL bindings there are no KMD restrictions
  883. * on the @pat_index. For such mappings there is no actual memory being
  884. * mapped (the address in the PTE is invalid), so the various PAT memory
  885. * attributes likely do not apply. Simply leaving as zero is one
  886. * option (still a valid pat_index).
  887. */
  888. __u16 pat_index;
  889. /** @pad: MBZ */
  890. __u16 pad;
  891. union {
  892. /**
  893. * @obj_offset: Offset into the object, MBZ for CLEAR_RANGE,
  894. * ignored for unbind
  895. */
  896. __u64 obj_offset;
  897. /** @userptr: user pointer to bind on */
  898. __u64 userptr;
  899. };
  900. /**
  901. * @range: Number of bytes from the object to bind to addr, MBZ for UNMAP_ALL
  902. */
  903. __u64 range;
  904. /** @addr: Address to operate on, MBZ for UNMAP_ALL */
  905. __u64 addr;
  906. #define DRM_XE_VM_BIND_OP_MAP 0x0
  907. #define DRM_XE_VM_BIND_OP_UNMAP 0x1
  908. #define DRM_XE_VM_BIND_OP_MAP_USERPTR 0x2
  909. #define DRM_XE_VM_BIND_OP_UNMAP_ALL 0x3
  910. #define DRM_XE_VM_BIND_OP_PREFETCH 0x4
  911. /** @op: Bind operation to perform */
  912. __u32 op;
  913. #define DRM_XE_VM_BIND_FLAG_READONLY (1 << 0)
  914. #define DRM_XE_VM_BIND_FLAG_IMMEDIATE (1 << 1)
  915. #define DRM_XE_VM_BIND_FLAG_NULL (1 << 2)
  916. #define DRM_XE_VM_BIND_FLAG_DUMPABLE (1 << 3)
  917. /** @flags: Bind flags */
  918. __u32 flags;
  919. /**
  920. * @prefetch_mem_region_instance: Memory region to prefetch VMA to.
  921. * It is a region instance, not a mask.
  922. * To be used only with %DRM_XE_VM_BIND_OP_PREFETCH operation.
  923. */
  924. __u32 prefetch_mem_region_instance;
  925. /** @pad2: MBZ */
  926. __u32 pad2;
  927. /** @reserved: Reserved */
  928. __u64 reserved[3];
  929. };
  930. /**
  931. * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
  932. *
  933. * Below is an example of a minimal use of @drm_xe_vm_bind to
  934. * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to
  935. * illustrate `userptr`. It can be synchronized by using the example
  936. * provided for @drm_xe_sync.
  937. *
  938. * .. code-block:: C
  939. *
  940. * data = aligned_alloc(ALIGNMENT, BO_SIZE);
  941. * struct drm_xe_vm_bind bind = {
  942. * .vm_id = vm,
  943. * .num_binds = 1,
  944. * .bind.obj = 0,
  945. * .bind.obj_offset = to_user_pointer(data),
  946. * .bind.range = BO_SIZE,
  947. * .bind.addr = BIND_ADDRESS,
  948. * .bind.op = DRM_XE_VM_BIND_OP_MAP_USERPTR,
  949. * .bind.flags = 0,
  950. * .num_syncs = 1,
  951. * .syncs = &sync,
  952. * .exec_queue_id = 0,
  953. * };
  954. * ioctl(fd, DRM_IOCTL_XE_VM_BIND, &bind);
  955. *
  956. */
  957. struct drm_xe_vm_bind {
  958. /** @extensions: Pointer to the first extension struct, if any */
  959. __u64 extensions;
  960. /** @vm_id: The ID of the VM to bind to */
  961. __u32 vm_id;
  962. /**
  963. * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND
  964. * and exec queue must have same vm_id. If zero, the default VM bind engine
  965. * is used.
  966. */
  967. __u32 exec_queue_id;
  968. /** @pad: MBZ */
  969. __u32 pad;
  970. /** @num_binds: number of binds in this IOCTL */
  971. __u32 num_binds;
  972. union {
  973. /** @bind: used if num_binds == 1 */
  974. struct drm_xe_vm_bind_op bind;
  975. /**
  976. * @vector_of_binds: userptr to array of struct
  977. * drm_xe_vm_bind_op if num_binds > 1
  978. */
  979. __u64 vector_of_binds;
  980. };
  981. /** @pad2: MBZ */
  982. __u32 pad2;
  983. /** @num_syncs: amount of syncs to wait on */
  984. __u32 num_syncs;
  985. /** @syncs: pointer to struct drm_xe_sync array */
  986. __u64 syncs;
  987. /** @reserved: Reserved */
  988. __u64 reserved[2];
  989. };
  990. /**
  991. * struct drm_xe_exec_queue_create - Input of &DRM_IOCTL_XE_EXEC_QUEUE_CREATE
  992. *
  993. * The example below shows how to use @drm_xe_exec_queue_create to create
  994. * a simple exec_queue (no parallel submission) of class
  995. * &DRM_XE_ENGINE_CLASS_RENDER.
  996. *
  997. * .. code-block:: C
  998. *
  999. * struct drm_xe_engine_class_instance instance = {
  1000. * .engine_class = DRM_XE_ENGINE_CLASS_RENDER,
  1001. * };
  1002. * struct drm_xe_exec_queue_create exec_queue_create = {
  1003. * .extensions = 0,
  1004. * .vm_id = vm,
  1005. * .num_bb_per_exec = 1,
  1006. * .num_eng_per_bb = 1,
  1007. * .instances = to_user_pointer(&instance),
  1008. * };
  1009. * ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
  1010. *
  1011. */
  1012. struct drm_xe_exec_queue_create {
  1013. #define DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0
  1014. #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0
  1015. #define DRM_XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1
  1016. /** @extensions: Pointer to the first extension struct, if any */
  1017. __u64 extensions;
  1018. /** @width: submission width (number BB per exec) for this exec queue */
  1019. __u16 width;
  1020. /** @num_placements: number of valid placements for this exec queue */
  1021. __u16 num_placements;
  1022. /** @vm_id: VM to use for this exec queue */
  1023. __u32 vm_id;
  1024. /** @flags: MBZ */
  1025. __u32 flags;
  1026. /** @exec_queue_id: Returned exec queue ID */
  1027. __u32 exec_queue_id;
  1028. /**
  1029. * @instances: user pointer to a 2-d array of struct
  1030. * drm_xe_engine_class_instance
  1031. *
  1032. * length = width (i) * num_placements (j)
  1033. * index = j + i * width
  1034. */
  1035. __u64 instances;
  1036. /** @reserved: Reserved */
  1037. __u64 reserved[2];
  1038. };
  1039. /**
  1040. * struct drm_xe_exec_queue_destroy - Input of &DRM_IOCTL_XE_EXEC_QUEUE_DESTROY
  1041. */
  1042. struct drm_xe_exec_queue_destroy {
  1043. /** @exec_queue_id: Exec queue ID */
  1044. __u32 exec_queue_id;
  1045. /** @pad: MBZ */
  1046. __u32 pad;
  1047. /** @reserved: Reserved */
  1048. __u64 reserved[2];
  1049. };
  1050. /**
  1051. * struct drm_xe_exec_queue_get_property - Input of &DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY
  1052. *
  1053. * The @property can be:
  1054. * - %DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN
  1055. */
  1056. struct drm_xe_exec_queue_get_property {
  1057. /** @extensions: Pointer to the first extension struct, if any */
  1058. __u64 extensions;
  1059. /** @exec_queue_id: Exec queue ID */
  1060. __u32 exec_queue_id;
  1061. #define DRM_XE_EXEC_QUEUE_GET_PROPERTY_BAN 0
  1062. /** @property: property to get */
  1063. __u32 property;
  1064. /** @value: property value */
  1065. __u64 value;
  1066. /** @reserved: Reserved */
  1067. __u64 reserved[2];
  1068. };
  1069. /**
  1070. * struct drm_xe_sync - sync object
  1071. *
  1072. * The @type can be:
  1073. * - %DRM_XE_SYNC_TYPE_SYNCOBJ
  1074. * - %DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ
  1075. * - %DRM_XE_SYNC_TYPE_USER_FENCE
  1076. *
  1077. * and the @flags can be:
  1078. * - %DRM_XE_SYNC_FLAG_SIGNAL
  1079. *
  1080. * A minimal use of @drm_xe_sync looks like this:
  1081. *
  1082. * .. code-block:: C
  1083. *
  1084. * struct drm_xe_sync sync = {
  1085. * .flags = DRM_XE_SYNC_FLAG_SIGNAL,
  1086. * .type = DRM_XE_SYNC_TYPE_SYNCOBJ,
  1087. * };
  1088. * struct drm_syncobj_create syncobj_create = { 0 };
  1089. * ioctl(fd, DRM_IOCTL_SYNCOBJ_CREATE, &syncobj_create);
  1090. * sync.handle = syncobj_create.handle;
  1091. * ...
  1092. * use of &sync in drm_xe_exec or drm_xe_vm_bind
  1093. * ...
  1094. * struct drm_syncobj_wait wait = {
  1095. * .handles = &sync.handle,
  1096. * .timeout_nsec = INT64_MAX,
  1097. * .count_handles = 1,
  1098. * .flags = 0,
  1099. * .first_signaled = 0,
  1100. * .pad = 0,
  1101. * };
  1102. * ioctl(fd, DRM_IOCTL_SYNCOBJ_WAIT, &wait);
  1103. */
  1104. struct drm_xe_sync {
  1105. /** @extensions: Pointer to the first extension struct, if any */
  1106. __u64 extensions;
  1107. #define DRM_XE_SYNC_TYPE_SYNCOBJ 0x0
  1108. #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ 0x1
  1109. #define DRM_XE_SYNC_TYPE_USER_FENCE 0x2
  1110. /** @type: Type of the this sync object */
  1111. __u32 type;
  1112. #define DRM_XE_SYNC_FLAG_SIGNAL (1 << 0)
  1113. /** @flags: Sync Flags */
  1114. __u32 flags;
  1115. union {
  1116. /** @handle: Handle for the object */
  1117. __u32 handle;
  1118. /**
  1119. * @addr: Address of user fence. When sync is passed in via exec
  1120. * IOCTL this is a GPU address in the VM. When sync passed in via
  1121. * VM bind IOCTL this is a user pointer. In either case, it is
  1122. * the users responsibility that this address is present and
  1123. * mapped when the user fence is signalled. Must be qword
  1124. * aligned.
  1125. */
  1126. __u64 addr;
  1127. };
  1128. /**
  1129. * @timeline_value: Input for the timeline sync object. Needs to be
  1130. * different than 0 when used with %DRM_XE_SYNC_FLAG_TIMELINE_SYNCOBJ.
  1131. */
  1132. __u64 timeline_value;
  1133. /** @reserved: Reserved */
  1134. __u64 reserved[2];
  1135. };
  1136. /**
  1137. * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
  1138. *
  1139. * This is an example to use @drm_xe_exec for execution of the object
  1140. * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue
  1141. * (see example in @drm_xe_exec_queue_create). It can be synchronized
  1142. * by using the example provided for @drm_xe_sync.
  1143. *
  1144. * .. code-block:: C
  1145. *
  1146. * struct drm_xe_exec exec = {
  1147. * .exec_queue_id = exec_queue,
  1148. * .syncs = &sync,
  1149. * .num_syncs = 1,
  1150. * .address = BIND_ADDRESS,
  1151. * .num_batch_buffer = 1,
  1152. * };
  1153. * ioctl(fd, DRM_IOCTL_XE_EXEC, &exec);
  1154. *
  1155. */
  1156. struct drm_xe_exec {
  1157. /** @extensions: Pointer to the first extension struct, if any */
  1158. __u64 extensions;
  1159. /** @exec_queue_id: Exec queue ID for the batch buffer */
  1160. __u32 exec_queue_id;
  1161. /** @num_syncs: Amount of struct drm_xe_sync in array. */
  1162. __u32 num_syncs;
  1163. /** @syncs: Pointer to struct drm_xe_sync array. */
  1164. __u64 syncs;
  1165. /**
  1166. * @address: address of batch buffer if num_batch_buffer == 1 or an
  1167. * array of batch buffer addresses
  1168. */
  1169. __u64 address;
  1170. /**
  1171. * @num_batch_buffer: number of batch buffer in this exec, must match
  1172. * the width of the engine
  1173. */
  1174. __u16 num_batch_buffer;
  1175. /** @pad: MBZ */
  1176. __u16 pad[3];
  1177. /** @reserved: Reserved */
  1178. __u64 reserved[2];
  1179. };
  1180. /**
  1181. * struct drm_xe_wait_user_fence - Input of &DRM_IOCTL_XE_WAIT_USER_FENCE
  1182. *
  1183. * Wait on user fence, XE will wake-up on every HW engine interrupt in the
  1184. * instances list and check if user fence is complete::
  1185. *
  1186. * (*addr & MASK) OP (VALUE & MASK)
  1187. *
  1188. * Returns to user on user fence completion or timeout.
  1189. *
  1190. * The @op can be:
  1191. * - %DRM_XE_UFENCE_WAIT_OP_EQ
  1192. * - %DRM_XE_UFENCE_WAIT_OP_NEQ
  1193. * - %DRM_XE_UFENCE_WAIT_OP_GT
  1194. * - %DRM_XE_UFENCE_WAIT_OP_GTE
  1195. * - %DRM_XE_UFENCE_WAIT_OP_LT
  1196. * - %DRM_XE_UFENCE_WAIT_OP_LTE
  1197. *
  1198. * and the @flags can be:
  1199. * - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
  1200. * - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP
  1201. *
  1202. * The @mask values can be for example:
  1203. * - 0xffu for u8
  1204. * - 0xffffu for u16
  1205. * - 0xffffffffu for u32
  1206. * - 0xffffffffffffffffu for u64
  1207. */
  1208. struct drm_xe_wait_user_fence {
  1209. /** @extensions: Pointer to the first extension struct, if any */
  1210. __u64 extensions;
  1211. /**
  1212. * @addr: user pointer address to wait on, must qword aligned
  1213. */
  1214. __u64 addr;
  1215. #define DRM_XE_UFENCE_WAIT_OP_EQ 0x0
  1216. #define DRM_XE_UFENCE_WAIT_OP_NEQ 0x1
  1217. #define DRM_XE_UFENCE_WAIT_OP_GT 0x2
  1218. #define DRM_XE_UFENCE_WAIT_OP_GTE 0x3
  1219. #define DRM_XE_UFENCE_WAIT_OP_LT 0x4
  1220. #define DRM_XE_UFENCE_WAIT_OP_LTE 0x5
  1221. /** @op: wait operation (type of comparison) */
  1222. __u16 op;
  1223. #define DRM_XE_UFENCE_WAIT_FLAG_ABSTIME (1 << 0)
  1224. /** @flags: wait flags */
  1225. __u16 flags;
  1226. /** @pad: MBZ */
  1227. __u32 pad;
  1228. /** @value: compare value */
  1229. __u64 value;
  1230. /** @mask: comparison mask */
  1231. __u64 mask;
  1232. /**
  1233. * @timeout: how long to wait before bailing, value in nanoseconds.
  1234. * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout)
  1235. * it contains timeout expressed in nanoseconds to wait (fence will
  1236. * expire at now() + timeout).
  1237. * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait
  1238. * will end at timeout (uses system MONOTONIC_CLOCK).
  1239. * Passing negative timeout leads to neverending wait.
  1240. *
  1241. * On relative timeout this value is updated with timeout left
  1242. * (for restarting the call in case of signal delivery).
  1243. * On absolute timeout this value stays intact (restarted call still
  1244. * expire at the same point of time).
  1245. */
  1246. __s64 timeout;
  1247. /** @exec_queue_id: exec_queue_id returned from xe_exec_queue_create_ioctl */
  1248. __u32 exec_queue_id;
  1249. /** @pad2: MBZ */
  1250. __u32 pad2;
  1251. /** @reserved: Reserved */
  1252. __u64 reserved[2];
  1253. };
  1254. /**
  1255. * enum drm_xe_observation_type - Observation stream types
  1256. */
  1257. enum drm_xe_observation_type {
  1258. /** @DRM_XE_OBSERVATION_TYPE_OA: OA observation stream type */
  1259. DRM_XE_OBSERVATION_TYPE_OA,
  1260. };
  1261. /**
  1262. * enum drm_xe_observation_op - Observation stream ops
  1263. */
  1264. enum drm_xe_observation_op {
  1265. /** @DRM_XE_OBSERVATION_OP_STREAM_OPEN: Open an observation stream */
  1266. DRM_XE_OBSERVATION_OP_STREAM_OPEN,
  1267. /** @DRM_XE_OBSERVATION_OP_ADD_CONFIG: Add observation stream config */
  1268. DRM_XE_OBSERVATION_OP_ADD_CONFIG,
  1269. /** @DRM_XE_OBSERVATION_OP_REMOVE_CONFIG: Remove observation stream config */
  1270. DRM_XE_OBSERVATION_OP_REMOVE_CONFIG,
  1271. };
  1272. /**
  1273. * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION
  1274. *
  1275. * The observation layer enables multiplexing observation streams of
  1276. * multiple types. The actual params for a particular stream operation are
  1277. * supplied via the @param pointer (use __copy_from_user to get these
  1278. * params).
  1279. */
  1280. struct drm_xe_observation_param {
  1281. /** @extensions: Pointer to the first extension struct, if any */
  1282. __u64 extensions;
  1283. /** @observation_type: observation stream type, of enum @drm_xe_observation_type */
  1284. __u64 observation_type;
  1285. /** @observation_op: observation stream op, of enum @drm_xe_observation_op */
  1286. __u64 observation_op;
  1287. /** @param: Pointer to actual stream params */
  1288. __u64 param;
  1289. };
  1290. /**
  1291. * enum drm_xe_observation_ioctls - Observation stream fd ioctl's
  1292. *
  1293. * Information exchanged between userspace and kernel for observation fd
  1294. * ioctl's is stream type specific
  1295. */
  1296. enum drm_xe_observation_ioctls {
  1297. /** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */
  1298. DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0),
  1299. /** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */
  1300. DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1),
  1301. /** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */
  1302. DRM_XE_OBSERVATION_IOCTL_CONFIG = _IO('i', 0x2),
  1303. /** @DRM_XE_OBSERVATION_IOCTL_STATUS: Return observation stream status */
  1304. DRM_XE_OBSERVATION_IOCTL_STATUS = _IO('i', 0x3),
  1305. /** @DRM_XE_OBSERVATION_IOCTL_INFO: Return observation stream info */
  1306. DRM_XE_OBSERVATION_IOCTL_INFO = _IO('i', 0x4),
  1307. };
  1308. /**
  1309. * enum drm_xe_oa_unit_type - OA unit types
  1310. */
  1311. enum drm_xe_oa_unit_type {
  1312. /**
  1313. * @DRM_XE_OA_UNIT_TYPE_OAG: OAG OA unit. OAR/OAC are considered
  1314. * sub-types of OAG. For OAR/OAC, use OAG.
  1315. */
  1316. DRM_XE_OA_UNIT_TYPE_OAG,
  1317. /** @DRM_XE_OA_UNIT_TYPE_OAM: OAM OA unit */
  1318. DRM_XE_OA_UNIT_TYPE_OAM,
  1319. };
  1320. /**
  1321. * struct drm_xe_oa_unit - describe OA unit
  1322. */
  1323. struct drm_xe_oa_unit {
  1324. /** @extensions: Pointer to the first extension struct, if any */
  1325. __u64 extensions;
  1326. /** @oa_unit_id: OA unit ID */
  1327. __u32 oa_unit_id;
  1328. /** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */
  1329. __u32 oa_unit_type;
  1330. /** @capabilities: OA capabilities bit-mask */
  1331. __u64 capabilities;
  1332. #define DRM_XE_OA_CAPS_BASE (1 << 0)
  1333. /** @oa_timestamp_freq: OA timestamp freq */
  1334. __u64 oa_timestamp_freq;
  1335. /** @reserved: MBZ */
  1336. __u64 reserved[4];
  1337. /** @num_engines: number of engines in @eci array */
  1338. __u64 num_engines;
  1339. /** @eci: engines attached to this OA unit */
  1340. struct drm_xe_engine_class_instance eci[];
  1341. };
  1342. /**
  1343. * struct drm_xe_query_oa_units - describe OA units
  1344. *
  1345. * If a query is made with a struct drm_xe_device_query where .query
  1346. * is equal to DRM_XE_DEVICE_QUERY_OA_UNITS, then the reply uses struct
  1347. * drm_xe_query_oa_units in .data.
  1348. *
  1349. * OA unit properties for all OA units can be accessed using a code block
  1350. * such as the one below:
  1351. *
  1352. * .. code-block:: C
  1353. *
  1354. * struct drm_xe_query_oa_units *qoa;
  1355. * struct drm_xe_oa_unit *oau;
  1356. * u8 *poau;
  1357. *
  1358. * // malloc qoa and issue DRM_XE_DEVICE_QUERY_OA_UNITS. Then:
  1359. * poau = (u8 *)&qoa->oa_units[0];
  1360. * for (int i = 0; i < qoa->num_oa_units; i++) {
  1361. * oau = (struct drm_xe_oa_unit *)poau;
  1362. * // Access 'struct drm_xe_oa_unit' fields here
  1363. * poau += sizeof(*oau) + oau->num_engines * sizeof(oau->eci[0]);
  1364. * }
  1365. */
  1366. struct drm_xe_query_oa_units {
  1367. /** @extensions: Pointer to the first extension struct, if any */
  1368. __u64 extensions;
  1369. /** @num_oa_units: number of OA units returned in oau[] */
  1370. __u32 num_oa_units;
  1371. /** @pad: MBZ */
  1372. __u32 pad;
  1373. /**
  1374. * @oa_units: struct @drm_xe_oa_unit array returned for this device.
  1375. * Written below as a u64 array to avoid problems with nested flexible
  1376. * arrays with some compilers
  1377. */
  1378. __u64 oa_units[];
  1379. };
  1380. /**
  1381. * enum drm_xe_oa_format_type - OA format types as specified in PRM/Bspec
  1382. * 52198/60942
  1383. */
  1384. enum drm_xe_oa_format_type {
  1385. /** @DRM_XE_OA_FMT_TYPE_OAG: OAG report format */
  1386. DRM_XE_OA_FMT_TYPE_OAG,
  1387. /** @DRM_XE_OA_FMT_TYPE_OAR: OAR report format */
  1388. DRM_XE_OA_FMT_TYPE_OAR,
  1389. /** @DRM_XE_OA_FMT_TYPE_OAM: OAM report format */
  1390. DRM_XE_OA_FMT_TYPE_OAM,
  1391. /** @DRM_XE_OA_FMT_TYPE_OAC: OAC report format */
  1392. DRM_XE_OA_FMT_TYPE_OAC,
  1393. /** @DRM_XE_OA_FMT_TYPE_OAM_MPEC: OAM SAMEDIA or OAM MPEC report format */
  1394. DRM_XE_OA_FMT_TYPE_OAM_MPEC,
  1395. /** @DRM_XE_OA_FMT_TYPE_PEC: PEC report format */
  1396. DRM_XE_OA_FMT_TYPE_PEC,
  1397. };
  1398. /**
  1399. * enum drm_xe_oa_property_id - OA stream property id's
  1400. *
  1401. * Stream params are specified as a chain of @drm_xe_ext_set_property
  1402. * struct's, with @property values from enum @drm_xe_oa_property_id and
  1403. * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY.
  1404. * @param field in struct @drm_xe_observation_param points to the first
  1405. * @drm_xe_ext_set_property struct.
  1406. *
  1407. * Exactly the same mechanism is also used for stream reconfiguration using the
  1408. * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a
  1409. * subset of properties below can be specified for stream reconfiguration.
  1410. */
  1411. enum drm_xe_oa_property_id {
  1412. #define DRM_XE_OA_EXTENSION_SET_PROPERTY 0
  1413. /**
  1414. * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open
  1415. * the OA stream, see @oa_unit_id in 'struct
  1416. * drm_xe_query_oa_units'. Defaults to 0 if not provided.
  1417. */
  1418. DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1,
  1419. /**
  1420. * @DRM_XE_OA_PROPERTY_SAMPLE_OA: A value of 1 requests inclusion of raw
  1421. * OA unit reports or stream samples in a global buffer attached to an
  1422. * OA unit.
  1423. */
  1424. DRM_XE_OA_PROPERTY_SAMPLE_OA,
  1425. /**
  1426. * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA
  1427. * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG.
  1428. */
  1429. DRM_XE_OA_PROPERTY_OA_METRIC_SET,
  1430. /** @DRM_XE_OA_PROPERTY_OA_FORMAT: OA counter report format */
  1431. DRM_XE_OA_PROPERTY_OA_FORMAT,
  1432. /*
  1433. * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942,
  1434. * in terms of the following quantities: a. enum @drm_xe_oa_format_type
  1435. * b. Counter select c. Counter size and d. BC report. Also refer to the
  1436. * oa_formats array in drivers/gpu/drm/xe/xe_oa.c.
  1437. */
  1438. #define DRM_XE_OA_FORMAT_MASK_FMT_TYPE (0xffu << 0)
  1439. #define DRM_XE_OA_FORMAT_MASK_COUNTER_SEL (0xffu << 8)
  1440. #define DRM_XE_OA_FORMAT_MASK_COUNTER_SIZE (0xffu << 16)
  1441. #define DRM_XE_OA_FORMAT_MASK_BC_REPORT (0xffu << 24)
  1442. /**
  1443. * @DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT: Requests periodic OA unit
  1444. * sampling with sampling frequency proportional to 2^(period_exponent + 1)
  1445. */
  1446. DRM_XE_OA_PROPERTY_OA_PERIOD_EXPONENT,
  1447. /**
  1448. * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA
  1449. * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE).
  1450. */
  1451. DRM_XE_OA_PROPERTY_OA_DISABLED,
  1452. /**
  1453. * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific
  1454. * @exec_queue_id. OA queries can be executed on this exec queue.
  1455. */
  1456. DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID,
  1457. /**
  1458. * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to
  1459. * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0.
  1460. */
  1461. DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE,
  1462. /**
  1463. * @DRM_XE_OA_PROPERTY_NO_PREEMPT: Allow preemption and timeslicing
  1464. * to be disabled for the stream exec queue.
  1465. */
  1466. DRM_XE_OA_PROPERTY_NO_PREEMPT,
  1467. };
  1468. /**
  1469. * struct drm_xe_oa_config - OA metric configuration
  1470. *
  1471. * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A
  1472. * particular config can be specified when opening an OA stream using
  1473. * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property.
  1474. */
  1475. struct drm_xe_oa_config {
  1476. /** @extensions: Pointer to the first extension struct, if any */
  1477. __u64 extensions;
  1478. /** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */
  1479. char uuid[36];
  1480. /** @n_regs: Number of regs in @regs_ptr */
  1481. __u32 n_regs;
  1482. /**
  1483. * @regs_ptr: Pointer to (register address, value) pairs for OA config
  1484. * registers. Expected length of buffer is: (2 * sizeof(u32) * @n_regs).
  1485. */
  1486. __u64 regs_ptr;
  1487. };
  1488. /**
  1489. * struct drm_xe_oa_stream_status - OA stream status returned from
  1490. * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can
  1491. * call the ioctl to query stream status in response to EIO errno from
  1492. * observation fd read().
  1493. */
  1494. struct drm_xe_oa_stream_status {
  1495. /** @extensions: Pointer to the first extension struct, if any */
  1496. __u64 extensions;
  1497. /** @oa_status: OA stream status (see Bspec 46717/61226) */
  1498. __u64 oa_status;
  1499. #define DRM_XE_OASTATUS_MMIO_TRG_Q_FULL (1 << 3)
  1500. #define DRM_XE_OASTATUS_COUNTER_OVERFLOW (1 << 2)
  1501. #define DRM_XE_OASTATUS_BUFFER_OVERFLOW (1 << 1)
  1502. #define DRM_XE_OASTATUS_REPORT_LOST (1 << 0)
  1503. /** @reserved: reserved for future use */
  1504. __u64 reserved[3];
  1505. };
  1506. /**
  1507. * struct drm_xe_oa_stream_info - OA stream info returned from
  1508. * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl
  1509. */
  1510. struct drm_xe_oa_stream_info {
  1511. /** @extensions: Pointer to the first extension struct, if any */
  1512. __u64 extensions;
  1513. /** @oa_buf_size: OA buffer size */
  1514. __u64 oa_buf_size;
  1515. /** @reserved: reserved for future use */
  1516. __u64 reserved[3];
  1517. };
  1518. #if defined(__cplusplus)
  1519. }
  1520. #endif
  1521. #endif /* _XE_DRM_H_ */