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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

qaic_accel.h (12067B)


  1. /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
  2. *
  3. * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
  4. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  5. */
  6. #ifndef QAIC_ACCEL_H_
  7. #define QAIC_ACCEL_H_
  8. #include "drm.h"
  9. #if defined(__cplusplus)
  10. extern "C" {
  11. #endif
  12. /* The length(4K) includes len and count fields of qaic_manage_msg */
  13. #define QAIC_MANAGE_MAX_MSG_LENGTH SZ_4K
  14. /* semaphore flags */
  15. #define QAIC_SEM_INSYNCFENCE 2
  16. #define QAIC_SEM_OUTSYNCFENCE 1
  17. /* Semaphore commands */
  18. #define QAIC_SEM_NOP 0
  19. #define QAIC_SEM_INIT 1
  20. #define QAIC_SEM_INC 2
  21. #define QAIC_SEM_DEC 3
  22. #define QAIC_SEM_WAIT_EQUAL 4
  23. #define QAIC_SEM_WAIT_GT_EQ 5 /* Greater than or equal */
  24. #define QAIC_SEM_WAIT_GT_0 6 /* Greater than 0 */
  25. #define QAIC_TRANS_UNDEFINED 0
  26. #define QAIC_TRANS_PASSTHROUGH_FROM_USR 1
  27. #define QAIC_TRANS_PASSTHROUGH_TO_USR 2
  28. #define QAIC_TRANS_PASSTHROUGH_FROM_DEV 3
  29. #define QAIC_TRANS_PASSTHROUGH_TO_DEV 4
  30. #define QAIC_TRANS_DMA_XFER_FROM_USR 5
  31. #define QAIC_TRANS_DMA_XFER_TO_DEV 6
  32. #define QAIC_TRANS_ACTIVATE_FROM_USR 7
  33. #define QAIC_TRANS_ACTIVATE_FROM_DEV 8
  34. #define QAIC_TRANS_ACTIVATE_TO_DEV 9
  35. #define QAIC_TRANS_DEACTIVATE_FROM_USR 10
  36. #define QAIC_TRANS_DEACTIVATE_FROM_DEV 11
  37. #define QAIC_TRANS_STATUS_FROM_USR 12
  38. #define QAIC_TRANS_STATUS_TO_USR 13
  39. #define QAIC_TRANS_STATUS_FROM_DEV 14
  40. #define QAIC_TRANS_STATUS_TO_DEV 15
  41. #define QAIC_TRANS_TERMINATE_FROM_DEV 16
  42. #define QAIC_TRANS_TERMINATE_TO_DEV 17
  43. #define QAIC_TRANS_DMA_XFER_CONT 18
  44. #define QAIC_TRANS_VALIDATE_PARTITION_FROM_DEV 19
  45. #define QAIC_TRANS_VALIDATE_PARTITION_TO_DEV 20
  46. /**
  47. * struct qaic_manage_trans_hdr - Header for a transaction in a manage message.
  48. * @type: In. Identifies this transaction. See QAIC_TRANS_* defines.
  49. * @len: In. Length of this transaction, including this header.
  50. */
  51. struct qaic_manage_trans_hdr {
  52. __u32 type;
  53. __u32 len;
  54. };
  55. /**
  56. * struct qaic_manage_trans_passthrough - Defines a passthrough transaction.
  57. * @hdr: In. Header to identify this transaction.
  58. * @data: In. Payload of this ransaction. Opaque to the driver. Userspace must
  59. * encode in little endian and align/pad to 64-bit.
  60. */
  61. struct qaic_manage_trans_passthrough {
  62. struct qaic_manage_trans_hdr hdr;
  63. __u8 data[];
  64. };
  65. /**
  66. * struct qaic_manage_trans_dma_xfer - Defines a DMA transfer transaction.
  67. * @hdr: In. Header to identify this transaction.
  68. * @tag: In. Identified this transfer in other transactions. Opaque to the
  69. * driver.
  70. * @pad: Structure padding.
  71. * @addr: In. Address of the data to DMA to the device.
  72. * @size: In. Length of the data to DMA to the device.
  73. */
  74. struct qaic_manage_trans_dma_xfer {
  75. struct qaic_manage_trans_hdr hdr;
  76. __u32 tag;
  77. __u32 pad;
  78. __u64 addr;
  79. __u64 size;
  80. };
  81. /**
  82. * struct qaic_manage_trans_activate_to_dev - Defines an activate request.
  83. * @hdr: In. Header to identify this transaction.
  84. * @queue_size: In. Number of elements for DBC request and response queues.
  85. * @eventfd: Unused.
  86. * @options: In. Device specific options for this activate.
  87. * @pad: Structure padding. Must be 0.
  88. */
  89. struct qaic_manage_trans_activate_to_dev {
  90. struct qaic_manage_trans_hdr hdr;
  91. __u32 queue_size;
  92. __u32 eventfd;
  93. __u32 options;
  94. __u32 pad;
  95. };
  96. /**
  97. * struct qaic_manage_trans_activate_from_dev - Defines an activate response.
  98. * @hdr: Out. Header to identify this transaction.
  99. * @status: Out. Return code of the request from the device.
  100. * @dbc_id: Out. Id of the assigned DBC for successful request.
  101. * @options: Out. Device specific options for this activate.
  102. */
  103. struct qaic_manage_trans_activate_from_dev {
  104. struct qaic_manage_trans_hdr hdr;
  105. __u32 status;
  106. __u32 dbc_id;
  107. __u64 options;
  108. };
  109. /**
  110. * struct qaic_manage_trans_deactivate - Defines a deactivate request.
  111. * @hdr: In. Header to identify this transaction.
  112. * @dbc_id: In. Id of assigned DBC.
  113. * @pad: Structure padding. Must be 0.
  114. */
  115. struct qaic_manage_trans_deactivate {
  116. struct qaic_manage_trans_hdr hdr;
  117. __u32 dbc_id;
  118. __u32 pad;
  119. };
  120. /**
  121. * struct qaic_manage_trans_status_to_dev - Defines a status request.
  122. * @hdr: In. Header to identify this transaction.
  123. */
  124. struct qaic_manage_trans_status_to_dev {
  125. struct qaic_manage_trans_hdr hdr;
  126. };
  127. /**
  128. * struct qaic_manage_trans_status_from_dev - Defines a status response.
  129. * @hdr: Out. Header to identify this transaction.
  130. * @major: Out. NNC protocol version major number.
  131. * @minor: Out. NNC protocol version minor number.
  132. * @status: Out. Return code from device.
  133. * @status_flags: Out. Flags from device. Bit 0 indicates if CRCs are required.
  134. */
  135. struct qaic_manage_trans_status_from_dev {
  136. struct qaic_manage_trans_hdr hdr;
  137. __u16 major;
  138. __u16 minor;
  139. __u32 status;
  140. __u64 status_flags;
  141. };
  142. /**
  143. * struct qaic_manage_msg - Defines a message to the device.
  144. * @len: In. Length of all the transactions contained within this message.
  145. * @count: In. Number of transactions in this message.
  146. * @data: In. Address to an array where the transactions can be found.
  147. */
  148. struct qaic_manage_msg {
  149. __u32 len;
  150. __u32 count;
  151. __u64 data;
  152. };
  153. /**
  154. * struct qaic_create_bo - Defines a request to create a buffer object.
  155. * @size: In. Size of the buffer in bytes.
  156. * @handle: Out. GEM handle for the BO.
  157. * @pad: Structure padding. Must be 0.
  158. */
  159. struct qaic_create_bo {
  160. __u64 size;
  161. __u32 handle;
  162. __u32 pad;
  163. };
  164. /**
  165. * struct qaic_mmap_bo - Defines a request to prepare a BO for mmap().
  166. * @handle: In. Handle of the GEM BO to prepare for mmap().
  167. * @pad: Structure padding. Must be 0.
  168. * @offset: Out. Offset value to provide to mmap().
  169. */
  170. struct qaic_mmap_bo {
  171. __u32 handle;
  172. __u32 pad;
  173. __u64 offset;
  174. };
  175. /**
  176. * struct qaic_sem - Defines a semaphore command for a BO slice.
  177. * @val: In. Only lower 12 bits are valid.
  178. * @index: In. Only lower 5 bits are valid.
  179. * @presync: In. 1 if presync operation, 0 if postsync.
  180. * @cmd: In. One of QAIC_SEM_*.
  181. * @flags: In. Bitfield. See QAIC_SEM_INSYNCFENCE and QAIC_SEM_OUTSYNCFENCE
  182. * @pad: Structure padding. Must be 0.
  183. */
  184. struct qaic_sem {
  185. __u16 val;
  186. __u8 index;
  187. __u8 presync;
  188. __u8 cmd;
  189. __u8 flags;
  190. __u16 pad;
  191. };
  192. /**
  193. * struct qaic_attach_slice_entry - Defines a single BO slice.
  194. * @size: In. Size of this slice in bytes.
  195. * @sem0: In. Semaphore command 0. Must be 0 is not valid.
  196. * @sem1: In. Semaphore command 1. Must be 0 is not valid.
  197. * @sem2: In. Semaphore command 2. Must be 0 is not valid.
  198. * @sem3: In. Semaphore command 3. Must be 0 is not valid.
  199. * @dev_addr: In. Device address this slice pushes to or pulls from.
  200. * @db_addr: In. Address of the doorbell to ring.
  201. * @db_data: In. Data to write to the doorbell.
  202. * @db_len: In. Size of the doorbell data in bits - 32, 16, or 8. 0 is for
  203. * inactive doorbells.
  204. * @offset: In. Start of this slice as an offset from the start of the BO.
  205. */
  206. struct qaic_attach_slice_entry {
  207. __u64 size;
  208. struct qaic_sem sem0;
  209. struct qaic_sem sem1;
  210. struct qaic_sem sem2;
  211. struct qaic_sem sem3;
  212. __u64 dev_addr;
  213. __u64 db_addr;
  214. __u32 db_data;
  215. __u32 db_len;
  216. __u64 offset;
  217. };
  218. /**
  219. * struct qaic_attach_slice_hdr - Defines metadata for a set of BO slices.
  220. * @count: In. Number of slices for this BO.
  221. * @dbc_id: In. Associate the sliced BO with this DBC.
  222. * @handle: In. GEM handle of the BO to slice.
  223. * @dir: In. Direction of data flow. 1 = DMA_TO_DEVICE, 2 = DMA_FROM_DEVICE
  224. * @size: Deprecated. This value is ignored and size of @handle is used instead.
  225. */
  226. struct qaic_attach_slice_hdr {
  227. __u32 count;
  228. __u32 dbc_id;
  229. __u32 handle;
  230. __u32 dir;
  231. __u64 size;
  232. };
  233. /**
  234. * struct qaic_attach_slice - Defines a set of BO slices.
  235. * @hdr: In. Metadata of the set of slices.
  236. * @data: In. Pointer to an array containing the slice definitions.
  237. */
  238. struct qaic_attach_slice {
  239. struct qaic_attach_slice_hdr hdr;
  240. __u64 data;
  241. };
  242. /**
  243. * struct qaic_execute_entry - Defines a BO to submit to the device.
  244. * @handle: In. GEM handle of the BO to commit to the device.
  245. * @dir: In. Direction of data. 1 = to device, 2 = from device.
  246. */
  247. struct qaic_execute_entry {
  248. __u32 handle;
  249. __u32 dir;
  250. };
  251. /**
  252. * struct qaic_partial_execute_entry - Defines a BO to resize and submit.
  253. * @handle: In. GEM handle of the BO to commit to the device.
  254. * @dir: In. Direction of data. 1 = to device, 2 = from device.
  255. * @resize: In. New size of the BO. Must be <= the original BO size.
  256. * @resize as 0 would be interpreted as no DMA transfer is
  257. * involved.
  258. */
  259. struct qaic_partial_execute_entry {
  260. __u32 handle;
  261. __u32 dir;
  262. __u64 resize;
  263. };
  264. /**
  265. * struct qaic_execute_hdr - Defines metadata for BO submission.
  266. * @count: In. Number of BOs to submit.
  267. * @dbc_id: In. DBC to submit the BOs on.
  268. */
  269. struct qaic_execute_hdr {
  270. __u32 count;
  271. __u32 dbc_id;
  272. };
  273. /**
  274. * struct qaic_execute - Defines a list of BOs to submit to the device.
  275. * @hdr: In. BO list metadata.
  276. * @data: In. Pointer to an array of BOs to submit.
  277. */
  278. struct qaic_execute {
  279. struct qaic_execute_hdr hdr;
  280. __u64 data;
  281. };
  282. /**
  283. * struct qaic_wait - Defines a blocking wait for BO execution.
  284. * @handle: In. GEM handle of the BO to wait on.
  285. * @timeout: In. Maximum time in ms to wait for the BO.
  286. * @dbc_id: In. DBC the BO is submitted to.
  287. * @pad: Structure padding. Must be 0.
  288. */
  289. struct qaic_wait {
  290. __u32 handle;
  291. __u32 timeout;
  292. __u32 dbc_id;
  293. __u32 pad;
  294. };
  295. /**
  296. * struct qaic_perf_stats_hdr - Defines metadata for getting BO perf info.
  297. * @count: In. Number of BOs requested.
  298. * @pad: Structure padding. Must be 0.
  299. * @dbc_id: In. DBC the BO are associated with.
  300. */
  301. struct qaic_perf_stats_hdr {
  302. __u16 count;
  303. __u16 pad;
  304. __u32 dbc_id;
  305. };
  306. /**
  307. * struct qaic_perf_stats - Defines a request for getting BO perf info.
  308. * @hdr: In. Request metadata
  309. * @data: In. Pointer to array of stats structures that will receive the data.
  310. */
  311. struct qaic_perf_stats {
  312. struct qaic_perf_stats_hdr hdr;
  313. __u64 data;
  314. };
  315. /**
  316. * struct qaic_perf_stats_entry - Defines a BO perf info.
  317. * @handle: In. GEM handle of the BO to get perf stats for.
  318. * @queue_level_before: Out. Number of elements in the queue before this BO
  319. * was submitted.
  320. * @num_queue_element: Out. Number of elements added to the queue to submit
  321. * this BO.
  322. * @submit_latency_us: Out. Time taken by the driver to submit this BO.
  323. * @device_latency_us: Out. Time taken by the device to execute this BO.
  324. * @pad: Structure padding. Must be 0.
  325. */
  326. struct qaic_perf_stats_entry {
  327. __u32 handle;
  328. __u32 queue_level_before;
  329. __u32 num_queue_element;
  330. __u32 submit_latency_us;
  331. __u32 device_latency_us;
  332. __u32 pad;
  333. };
  334. /**
  335. * struct qaic_detach_slice - Detaches slicing configuration from BO.
  336. * @handle: In. GEM handle of the BO to detach slicing configuration.
  337. * @pad: Structure padding. Must be 0.
  338. */
  339. struct qaic_detach_slice {
  340. __u32 handle;
  341. __u32 pad;
  342. };
  343. #define DRM_QAIC_MANAGE 0x00
  344. #define DRM_QAIC_CREATE_BO 0x01
  345. #define DRM_QAIC_MMAP_BO 0x02
  346. #define DRM_QAIC_ATTACH_SLICE_BO 0x03
  347. #define DRM_QAIC_EXECUTE_BO 0x04
  348. #define DRM_QAIC_PARTIAL_EXECUTE_BO 0x05
  349. #define DRM_QAIC_WAIT_BO 0x06
  350. #define DRM_QAIC_PERF_STATS_BO 0x07
  351. #define DRM_QAIC_DETACH_SLICE_BO 0x08
  352. #define DRM_IOCTL_QAIC_MANAGE DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MANAGE, struct qaic_manage_msg)
  353. #define DRM_IOCTL_QAIC_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_CREATE_BO, struct qaic_create_bo)
  354. #define DRM_IOCTL_QAIC_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_MMAP_BO, struct qaic_mmap_bo)
  355. #define DRM_IOCTL_QAIC_ATTACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_ATTACH_SLICE_BO, struct qaic_attach_slice)
  356. #define DRM_IOCTL_QAIC_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_EXECUTE_BO, struct qaic_execute)
  357. #define DRM_IOCTL_QAIC_PARTIAL_EXECUTE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_PARTIAL_EXECUTE_BO, struct qaic_execute)
  358. #define DRM_IOCTL_QAIC_WAIT_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_WAIT_BO, struct qaic_wait)
  359. #define DRM_IOCTL_QAIC_PERF_STATS_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_QAIC_PERF_STATS_BO, struct qaic_perf_stats)
  360. #define DRM_IOCTL_QAIC_DETACH_SLICE_BO DRM_IOW(DRM_COMMAND_BASE + DRM_QAIC_DETACH_SLICE_BO, struct qaic_detach_slice)
  361. #if defined(__cplusplus)
  362. }
  363. #endif
  364. #endif /* QAIC_ACCEL_H_ */