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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

nouveau_drm.h (15078B)


  1. /*
  2. * Copyright 2005 Stephane Marchesin.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. */
  24. #ifndef __NOUVEAU_DRM_H__
  25. #define __NOUVEAU_DRM_H__
  26. #define DRM_NOUVEAU_EVENT_NVIF 0x80000000
  27. #include "drm.h"
  28. #if defined(__cplusplus)
  29. extern "C" {
  30. #endif
  31. #define NOUVEAU_GETPARAM_PCI_VENDOR 3
  32. #define NOUVEAU_GETPARAM_PCI_DEVICE 4
  33. #define NOUVEAU_GETPARAM_BUS_TYPE 5
  34. #define NOUVEAU_GETPARAM_FB_SIZE 8
  35. #define NOUVEAU_GETPARAM_AGP_SIZE 9
  36. #define NOUVEAU_GETPARAM_CHIPSET_ID 11
  37. #define NOUVEAU_GETPARAM_VM_VRAM_BASE 12
  38. #define NOUVEAU_GETPARAM_GRAPH_UNITS 13
  39. #define NOUVEAU_GETPARAM_PTIMER_TIME 14
  40. #define NOUVEAU_GETPARAM_HAS_BO_USAGE 15
  41. #define NOUVEAU_GETPARAM_HAS_PAGEFLIP 16
  42. /*
  43. * NOUVEAU_GETPARAM_EXEC_PUSH_MAX - query max pushes through getparam
  44. *
  45. * Query the maximum amount of IBs that can be pushed through a single
  46. * &drm_nouveau_exec structure and hence a single &DRM_IOCTL_NOUVEAU_EXEC
  47. * ioctl().
  48. */
  49. #define NOUVEAU_GETPARAM_EXEC_PUSH_MAX 17
  50. /*
  51. * NOUVEAU_GETPARAM_VRAM_BAR_SIZE - query bar size
  52. *
  53. * Query the VRAM BAR size.
  54. */
  55. #define NOUVEAU_GETPARAM_VRAM_BAR_SIZE 18
  56. /*
  57. * NOUVEAU_GETPARAM_VRAM_USED
  58. *
  59. * Get remaining VRAM size.
  60. */
  61. #define NOUVEAU_GETPARAM_VRAM_USED 19
  62. /*
  63. * NOUVEAU_GETPARAM_HAS_VMA_TILEMODE
  64. *
  65. * Query whether tile mode and PTE kind are accepted with VM allocs or not.
  66. */
  67. #define NOUVEAU_GETPARAM_HAS_VMA_TILEMODE 20
  68. struct drm_nouveau_getparam {
  69. __u64 param;
  70. __u64 value;
  71. };
  72. /*
  73. * Those are used to support selecting the main engine used on Kepler.
  74. * This goes into drm_nouveau_channel_alloc::tt_ctxdma_handle
  75. */
  76. #define NOUVEAU_FIFO_ENGINE_GR 0x01
  77. #define NOUVEAU_FIFO_ENGINE_VP 0x02
  78. #define NOUVEAU_FIFO_ENGINE_PPP 0x04
  79. #define NOUVEAU_FIFO_ENGINE_BSP 0x08
  80. #define NOUVEAU_FIFO_ENGINE_CE 0x30
  81. struct drm_nouveau_channel_alloc {
  82. __u32 fb_ctxdma_handle;
  83. __u32 tt_ctxdma_handle;
  84. __s32 channel;
  85. __u32 pushbuf_domains;
  86. /* Notifier memory */
  87. __u32 notifier_handle;
  88. /* DRM-enforced subchannel assignments */
  89. struct {
  90. __u32 handle;
  91. __u32 grclass;
  92. } subchan[8];
  93. __u32 nr_subchan;
  94. };
  95. struct drm_nouveau_channel_free {
  96. __s32 channel;
  97. };
  98. struct drm_nouveau_notifierobj_alloc {
  99. __u32 channel;
  100. __u32 handle;
  101. __u32 size;
  102. __u32 offset;
  103. };
  104. struct drm_nouveau_gpuobj_free {
  105. __s32 channel;
  106. __u32 handle;
  107. };
  108. #define NOUVEAU_GEM_DOMAIN_CPU (1 << 0)
  109. #define NOUVEAU_GEM_DOMAIN_VRAM (1 << 1)
  110. #define NOUVEAU_GEM_DOMAIN_GART (1 << 2)
  111. #define NOUVEAU_GEM_DOMAIN_MAPPABLE (1 << 3)
  112. #define NOUVEAU_GEM_DOMAIN_COHERENT (1 << 4)
  113. /* The BO will never be shared via import or export. */
  114. #define NOUVEAU_GEM_DOMAIN_NO_SHARE (1 << 5)
  115. #define NOUVEAU_GEM_TILE_COMP 0x00030000 /* nv50-only */
  116. #define NOUVEAU_GEM_TILE_LAYOUT_MASK 0x0000ff00
  117. #define NOUVEAU_GEM_TILE_16BPP 0x00000001
  118. #define NOUVEAU_GEM_TILE_32BPP 0x00000002
  119. #define NOUVEAU_GEM_TILE_ZETA 0x00000004
  120. #define NOUVEAU_GEM_TILE_NONCONTIG 0x00000008
  121. struct drm_nouveau_gem_info {
  122. __u32 handle;
  123. __u32 domain;
  124. __u64 size;
  125. __u64 offset;
  126. __u64 map_handle;
  127. __u32 tile_mode;
  128. __u32 tile_flags;
  129. };
  130. struct drm_nouveau_gem_new {
  131. struct drm_nouveau_gem_info info;
  132. __u32 channel_hint;
  133. __u32 align;
  134. };
  135. #define NOUVEAU_GEM_MAX_BUFFERS 1024
  136. struct drm_nouveau_gem_pushbuf_bo_presumed {
  137. __u32 valid;
  138. __u32 domain;
  139. __u64 offset;
  140. };
  141. struct drm_nouveau_gem_pushbuf_bo {
  142. __u64 user_priv;
  143. __u32 handle;
  144. __u32 read_domains;
  145. __u32 write_domains;
  146. __u32 valid_domains;
  147. struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
  148. };
  149. #define NOUVEAU_GEM_RELOC_LOW (1 << 0)
  150. #define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
  151. #define NOUVEAU_GEM_RELOC_OR (1 << 2)
  152. #define NOUVEAU_GEM_MAX_RELOCS 1024
  153. struct drm_nouveau_gem_pushbuf_reloc {
  154. __u32 reloc_bo_index;
  155. __u32 reloc_bo_offset;
  156. __u32 bo_index;
  157. __u32 flags;
  158. __u32 data;
  159. __u32 vor;
  160. __u32 tor;
  161. };
  162. #define NOUVEAU_GEM_MAX_PUSH 512
  163. struct drm_nouveau_gem_pushbuf_push {
  164. __u32 bo_index;
  165. __u32 pad;
  166. __u64 offset;
  167. __u64 length;
  168. #define NOUVEAU_GEM_PUSHBUF_NO_PREFETCH (1 << 23)
  169. };
  170. struct drm_nouveau_gem_pushbuf {
  171. __u32 channel;
  172. __u32 nr_buffers;
  173. __u64 buffers;
  174. __u32 nr_relocs;
  175. __u32 nr_push;
  176. __u64 relocs;
  177. __u64 push;
  178. __u32 suffix0;
  179. __u32 suffix1;
  180. #define NOUVEAU_GEM_PUSHBUF_SYNC (1ULL << 0)
  181. __u64 vram_available;
  182. __u64 gart_available;
  183. };
  184. #define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
  185. #define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
  186. struct drm_nouveau_gem_cpu_prep {
  187. __u32 handle;
  188. __u32 flags;
  189. };
  190. struct drm_nouveau_gem_cpu_fini {
  191. __u32 handle;
  192. };
  193. /**
  194. * struct drm_nouveau_sync - sync object
  195. *
  196. * This structure serves as synchronization mechanism for (potentially)
  197. * asynchronous operations such as EXEC or VM_BIND.
  198. */
  199. struct drm_nouveau_sync {
  200. /**
  201. * @flags: the flags for a sync object
  202. *
  203. * The first 8 bits are used to determine the type of the sync object.
  204. */
  205. __u32 flags;
  206. #define DRM_NOUVEAU_SYNC_SYNCOBJ 0x0
  207. #define DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ 0x1
  208. #define DRM_NOUVEAU_SYNC_TYPE_MASK 0xf
  209. /**
  210. * @handle: the handle of the sync object
  211. */
  212. __u32 handle;
  213. /**
  214. * @timeline_value:
  215. *
  216. * The timeline point of the sync object in case the syncobj is of
  217. * type DRM_NOUVEAU_SYNC_TIMELINE_SYNCOBJ.
  218. */
  219. __u64 timeline_value;
  220. };
  221. /**
  222. * struct drm_nouveau_vm_init - GPU VA space init structure
  223. *
  224. * Used to initialize the GPU's VA space for a user client, telling the kernel
  225. * which portion of the VA space is managed by the UMD and kernel respectively.
  226. *
  227. * For the UMD to use the VM_BIND uAPI, this must be called before any BOs or
  228. * channels are created; if called afterwards DRM_IOCTL_NOUVEAU_VM_INIT fails
  229. * with -ENOSYS.
  230. */
  231. struct drm_nouveau_vm_init {
  232. /**
  233. * @kernel_managed_addr: start address of the kernel managed VA space
  234. * region
  235. */
  236. __u64 kernel_managed_addr;
  237. /**
  238. * @kernel_managed_size: size of the kernel managed VA space region in
  239. * bytes
  240. */
  241. __u64 kernel_managed_size;
  242. };
  243. /**
  244. * struct drm_nouveau_vm_bind_op - VM_BIND operation
  245. *
  246. * This structure represents a single VM_BIND operation. UMDs should pass
  247. * an array of this structure via struct drm_nouveau_vm_bind's &op_ptr field.
  248. */
  249. struct drm_nouveau_vm_bind_op {
  250. /**
  251. * @op: the operation type
  252. *
  253. * Supported values:
  254. *
  255. * %DRM_NOUVEAU_VM_BIND_OP_MAP - Map a GEM object to the GPU's VA
  256. * space. Optionally, the &DRM_NOUVEAU_VM_BIND_SPARSE flag can be
  257. * passed to instruct the kernel to create sparse mappings for the
  258. * given range.
  259. *
  260. * %DRM_NOUVEAU_VM_BIND_OP_UNMAP - Unmap an existing mapping in the
  261. * GPU's VA space. If the region the mapping is located in is a
  262. * sparse region, new sparse mappings are created where the unmapped
  263. * (memory backed) mapping was mapped previously. To remove a sparse
  264. * region the &DRM_NOUVEAU_VM_BIND_SPARSE must be set.
  265. */
  266. __u32 op;
  267. #define DRM_NOUVEAU_VM_BIND_OP_MAP 0x0
  268. #define DRM_NOUVEAU_VM_BIND_OP_UNMAP 0x1
  269. /**
  270. * @flags: the flags for a &drm_nouveau_vm_bind_op
  271. *
  272. * Supported values:
  273. *
  274. * %DRM_NOUVEAU_VM_BIND_SPARSE - Indicates that an allocated VA
  275. * space region should be sparse.
  276. */
  277. __u32 flags;
  278. #define DRM_NOUVEAU_VM_BIND_SPARSE (1 << 8)
  279. /**
  280. * @handle: the handle of the DRM GEM object to map
  281. */
  282. __u32 handle;
  283. /**
  284. * @pad: 32 bit padding, should be 0
  285. */
  286. __u32 pad;
  287. /**
  288. * @addr:
  289. *
  290. * the address the VA space region or (memory backed) mapping should be mapped to
  291. */
  292. __u64 addr;
  293. /**
  294. * @bo_offset: the offset within the BO backing the mapping
  295. */
  296. __u64 bo_offset;
  297. /**
  298. * @range: the size of the requested mapping in bytes
  299. */
  300. __u64 range;
  301. };
  302. /**
  303. * struct drm_nouveau_vm_bind - structure for DRM_IOCTL_NOUVEAU_VM_BIND
  304. */
  305. struct drm_nouveau_vm_bind {
  306. /**
  307. * @op_count: the number of &drm_nouveau_vm_bind_op
  308. */
  309. __u32 op_count;
  310. /**
  311. * @flags: the flags for a &drm_nouveau_vm_bind ioctl
  312. *
  313. * Supported values:
  314. *
  315. * %DRM_NOUVEAU_VM_BIND_RUN_ASYNC - Indicates that the given VM_BIND
  316. * operation should be executed asynchronously by the kernel.
  317. *
  318. * If this flag is not supplied the kernel executes the associated
  319. * operations synchronously and doesn't accept any &drm_nouveau_sync
  320. * objects.
  321. */
  322. __u32 flags;
  323. #define DRM_NOUVEAU_VM_BIND_RUN_ASYNC 0x1
  324. /**
  325. * @wait_count: the number of wait &drm_nouveau_syncs
  326. */
  327. __u32 wait_count;
  328. /**
  329. * @sig_count: the number of &drm_nouveau_syncs to signal when finished
  330. */
  331. __u32 sig_count;
  332. /**
  333. * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
  334. */
  335. __u64 wait_ptr;
  336. /**
  337. * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
  338. */
  339. __u64 sig_ptr;
  340. /**
  341. * @op_ptr: pointer to the &drm_nouveau_vm_bind_ops to execute
  342. */
  343. __u64 op_ptr;
  344. };
  345. /**
  346. * struct drm_nouveau_exec_push - EXEC push operation
  347. *
  348. * This structure represents a single EXEC push operation. UMDs should pass an
  349. * array of this structure via struct drm_nouveau_exec's &push_ptr field.
  350. */
  351. struct drm_nouveau_exec_push {
  352. /**
  353. * @va: the virtual address of the push buffer mapping
  354. */
  355. __u64 va;
  356. /**
  357. * @va_len: the length of the push buffer mapping
  358. */
  359. __u32 va_len;
  360. /**
  361. * @flags: the flags for this push buffer mapping
  362. */
  363. __u32 flags;
  364. #define DRM_NOUVEAU_EXEC_PUSH_NO_PREFETCH 0x1
  365. };
  366. /**
  367. * struct drm_nouveau_exec - structure for DRM_IOCTL_NOUVEAU_EXEC
  368. */
  369. struct drm_nouveau_exec {
  370. /**
  371. * @channel: the channel to execute the push buffer in
  372. */
  373. __u32 channel;
  374. /**
  375. * @push_count: the number of &drm_nouveau_exec_push ops
  376. */
  377. __u32 push_count;
  378. /**
  379. * @wait_count: the number of wait &drm_nouveau_syncs
  380. */
  381. __u32 wait_count;
  382. /**
  383. * @sig_count: the number of &drm_nouveau_syncs to signal when finished
  384. */
  385. __u32 sig_count;
  386. /**
  387. * @wait_ptr: pointer to &drm_nouveau_syncs to wait for
  388. */
  389. __u64 wait_ptr;
  390. /**
  391. * @sig_ptr: pointer to &drm_nouveau_syncs to signal when finished
  392. */
  393. __u64 sig_ptr;
  394. /**
  395. * @push_ptr: pointer to &drm_nouveau_exec_push ops
  396. */
  397. __u64 push_ptr;
  398. };
  399. #define DRM_NOUVEAU_GETPARAM 0x00
  400. #define DRM_NOUVEAU_SETPARAM 0x01 /* deprecated */
  401. #define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
  402. #define DRM_NOUVEAU_CHANNEL_FREE 0x03
  403. #define DRM_NOUVEAU_GROBJ_ALLOC 0x04 /* deprecated */
  404. #define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05 /* deprecated */
  405. #define DRM_NOUVEAU_GPUOBJ_FREE 0x06 /* deprecated */
  406. #define DRM_NOUVEAU_NVIF 0x07
  407. #define DRM_NOUVEAU_SVM_INIT 0x08
  408. #define DRM_NOUVEAU_SVM_BIND 0x09
  409. #define DRM_NOUVEAU_VM_INIT 0x10
  410. #define DRM_NOUVEAU_VM_BIND 0x11
  411. #define DRM_NOUVEAU_EXEC 0x12
  412. #define DRM_NOUVEAU_GEM_NEW 0x40
  413. #define DRM_NOUVEAU_GEM_PUSHBUF 0x41
  414. #define DRM_NOUVEAU_GEM_CPU_PREP 0x42
  415. #define DRM_NOUVEAU_GEM_CPU_FINI 0x43
  416. #define DRM_NOUVEAU_GEM_INFO 0x44
  417. struct drm_nouveau_svm_init {
  418. __u64 unmanaged_addr;
  419. __u64 unmanaged_size;
  420. };
  421. struct drm_nouveau_svm_bind {
  422. __u64 header;
  423. __u64 va_start;
  424. __u64 va_end;
  425. __u64 npages;
  426. __u64 stride;
  427. __u64 result;
  428. __u64 reserved0;
  429. __u64 reserved1;
  430. };
  431. #define NOUVEAU_SVM_BIND_COMMAND_SHIFT 0
  432. #define NOUVEAU_SVM_BIND_COMMAND_BITS 8
  433. #define NOUVEAU_SVM_BIND_COMMAND_MASK ((1 << 8) - 1)
  434. #define NOUVEAU_SVM_BIND_PRIORITY_SHIFT 8
  435. #define NOUVEAU_SVM_BIND_PRIORITY_BITS 8
  436. #define NOUVEAU_SVM_BIND_PRIORITY_MASK ((1 << 8) - 1)
  437. #define NOUVEAU_SVM_BIND_TARGET_SHIFT 16
  438. #define NOUVEAU_SVM_BIND_TARGET_BITS 32
  439. #define NOUVEAU_SVM_BIND_TARGET_MASK 0xffffffff
  440. /*
  441. * Below is use to validate ioctl argument, userspace can also use it to make
  442. * sure that no bit are set beyond known fields for a given kernel version.
  443. */
  444. #define NOUVEAU_SVM_BIND_VALID_BITS 48
  445. #define NOUVEAU_SVM_BIND_VALID_MASK ((1ULL << NOUVEAU_SVM_BIND_VALID_BITS) - 1)
  446. /*
  447. * NOUVEAU_BIND_COMMAND__MIGRATE: synchronous migrate to target memory.
  448. * result: number of page successfuly migrate to the target memory.
  449. */
  450. #define NOUVEAU_SVM_BIND_COMMAND__MIGRATE 0
  451. /*
  452. * NOUVEAU_SVM_BIND_HEADER_TARGET__GPU_VRAM: target the GPU VRAM memory.
  453. */
  454. #define NOUVEAU_SVM_BIND_TARGET__GPU_VRAM (1UL << 31)
  455. #define DRM_IOCTL_NOUVEAU_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GETPARAM, struct drm_nouveau_getparam)
  456. #define DRM_IOCTL_NOUVEAU_CHANNEL_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_ALLOC, struct drm_nouveau_channel_alloc)
  457. #define DRM_IOCTL_NOUVEAU_CHANNEL_FREE DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_CHANNEL_FREE, struct drm_nouveau_channel_free)
  458. #define DRM_IOCTL_NOUVEAU_SVM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_INIT, struct drm_nouveau_svm_init)
  459. #define DRM_IOCTL_NOUVEAU_SVM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_SVM_BIND, struct drm_nouveau_svm_bind)
  460. #define DRM_IOCTL_NOUVEAU_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_NEW, struct drm_nouveau_gem_new)
  461. #define DRM_IOCTL_NOUVEAU_GEM_PUSHBUF DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_PUSHBUF, struct drm_nouveau_gem_pushbuf)
  462. #define DRM_IOCTL_NOUVEAU_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_PREP, struct drm_nouveau_gem_cpu_prep)
  463. #define DRM_IOCTL_NOUVEAU_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_CPU_FINI, struct drm_nouveau_gem_cpu_fini)
  464. #define DRM_IOCTL_NOUVEAU_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_GEM_INFO, struct drm_nouveau_gem_info)
  465. #define DRM_IOCTL_NOUVEAU_VM_INIT DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_INIT, struct drm_nouveau_vm_init)
  466. #define DRM_IOCTL_NOUVEAU_VM_BIND DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_VM_BIND, struct drm_nouveau_vm_bind)
  467. #define DRM_IOCTL_NOUVEAU_EXEC DRM_IOWR(DRM_COMMAND_BASE + DRM_NOUVEAU_EXEC, struct drm_nouveau_exec)
  468. #if defined(__cplusplus)
  469. }
  470. #endif
  471. #endif /* __NOUVEAU_DRM_H__ */