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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

msm_drm.h (16617B)


  1. /*
  2. * Copyright (C) 2013 Red Hat
  3. * Author: Rob Clark <robdclark@gmail.com>
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the "Software"),
  7. * to deal in the Software without restriction, including without limitation
  8. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  9. * and/or sell copies of the Software, and to permit persons to whom the
  10. * Software is furnished to do so, subject to the following conditions:
  11. *
  12. * The above copyright notice and this permission notice (including the next
  13. * paragraph) shall be included in all copies or substantial portions of the
  14. * Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22. * SOFTWARE.
  23. */
  24. #ifndef __MSM_DRM_H__
  25. #define __MSM_DRM_H__
  26. #include "drm.h"
  27. #if defined(__cplusplus)
  28. extern "C" {
  29. #endif
  30. /* Please note that modifications to all structs defined here are
  31. * subject to backwards-compatibility constraints:
  32. * 1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
  33. * user/kernel compatibility
  34. * 2) Keep fields aligned to their size
  35. * 3) Because of how drm_ioctl() works, we can add new fields at
  36. * the end of an ioctl if some care is taken: drm_ioctl() will
  37. * zero out the new fields at the tail of the ioctl, so a zero
  38. * value should have a backwards compatible meaning. And for
  39. * output params, userspace won't see the newly added output
  40. * fields.. so that has to be somehow ok.
  41. */
  42. #define MSM_PIPE_NONE 0x00
  43. #define MSM_PIPE_2D0 0x01
  44. #define MSM_PIPE_2D1 0x02
  45. #define MSM_PIPE_3D0 0x10
  46. /* The pipe-id just uses the lower bits, so can be OR'd with flags in
  47. * the upper 16 bits (which could be extended further, if needed, maybe
  48. * we extend/overload the pipe-id some day to deal with multiple rings,
  49. * but even then I don't think we need the full lower 16 bits).
  50. */
  51. #define MSM_PIPE_ID_MASK 0xffff
  52. #define MSM_PIPE_ID(x) ((x) & MSM_PIPE_ID_MASK)
  53. #define MSM_PIPE_FLAGS(x) ((x) & ~MSM_PIPE_ID_MASK)
  54. /* timeouts are specified in clock-monotonic absolute times (to simplify
  55. * restarting interrupted ioctls). The following struct is logically the
  56. * same as 'struct timespec' but 32/64b ABI safe.
  57. */
  58. struct drm_msm_timespec {
  59. __s64 tv_sec; /* seconds */
  60. __s64 tv_nsec; /* nanoseconds */
  61. };
  62. /* Below "RO" indicates a read-only param, "WO" indicates write-only, and
  63. * "RW" indicates a param that can be both read (GET_PARAM) and written
  64. * (SET_PARAM)
  65. */
  66. #define MSM_PARAM_GPU_ID 0x01 /* RO */
  67. #define MSM_PARAM_GMEM_SIZE 0x02 /* RO */
  68. #define MSM_PARAM_CHIP_ID 0x03 /* RO */
  69. #define MSM_PARAM_MAX_FREQ 0x04 /* RO */
  70. #define MSM_PARAM_TIMESTAMP 0x05 /* RO */
  71. #define MSM_PARAM_GMEM_BASE 0x06 /* RO */
  72. #define MSM_PARAM_PRIORITIES 0x07 /* RO: The # of priority levels */
  73. #define MSM_PARAM_PP_PGTABLE 0x08 /* RO: Deprecated, always returns zero */
  74. #define MSM_PARAM_FAULTS 0x09 /* RO */
  75. #define MSM_PARAM_SUSPENDS 0x0a /* RO */
  76. #define MSM_PARAM_SYSPROF 0x0b /* WO: 1 preserves perfcntrs, 2 also disables suspend */
  77. #define MSM_PARAM_COMM 0x0c /* WO: override for task->comm */
  78. #define MSM_PARAM_CMDLINE 0x0d /* WO: override for task cmdline */
  79. #define MSM_PARAM_VA_START 0x0e /* RO: start of valid GPU iova range */
  80. #define MSM_PARAM_VA_SIZE 0x0f /* RO: size of valid GPU iova range (bytes) */
  81. #define MSM_PARAM_HIGHEST_BANK_BIT 0x10 /* RO */
  82. #define MSM_PARAM_RAYTRACING 0x11 /* RO */
  83. #define MSM_PARAM_UBWC_SWIZZLE 0x12 /* RO */
  84. #define MSM_PARAM_MACROTILE_MODE 0x13 /* RO */
  85. /* For backwards compat. The original support for preemption was based on
  86. * a single ring per priority level so # of priority levels equals the #
  87. * of rings. With drm/scheduler providing additional levels of priority,
  88. * the number of priorities is greater than the # of rings. The param is
  89. * renamed to better reflect this.
  90. */
  91. #define MSM_PARAM_NR_RINGS MSM_PARAM_PRIORITIES
  92. struct drm_msm_param {
  93. __u32 pipe; /* in, MSM_PIPE_x */
  94. __u32 param; /* in, MSM_PARAM_x */
  95. __u64 value; /* out (get_param) or in (set_param) */
  96. __u32 len; /* zero for non-pointer params */
  97. __u32 pad; /* must be zero */
  98. };
  99. /*
  100. * GEM buffers:
  101. */
  102. #define MSM_BO_SCANOUT 0x00000001 /* scanout capable */
  103. #define MSM_BO_GPU_READONLY 0x00000002
  104. #define MSM_BO_CACHE_MASK 0x000f0000
  105. /* cache modes */
  106. #define MSM_BO_CACHED 0x00010000
  107. #define MSM_BO_WC 0x00020000
  108. #define MSM_BO_UNCACHED 0x00040000 /* deprecated, use MSM_BO_WC */
  109. #define MSM_BO_CACHED_COHERENT 0x080000
  110. #define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
  111. MSM_BO_GPU_READONLY | \
  112. MSM_BO_CACHE_MASK)
  113. struct drm_msm_gem_new {
  114. __u64 size; /* in */
  115. __u32 flags; /* in, mask of MSM_BO_x */
  116. __u32 handle; /* out */
  117. };
  118. /* Get or set GEM buffer info. The requested value can be passed
  119. * directly in 'value', or for data larger than 64b 'value' is a
  120. * pointer to userspace buffer, with 'len' specifying the number of
  121. * bytes copied into that buffer. For info returned by pointer,
  122. * calling the GEM_INFO ioctl with null 'value' will return the
  123. * required buffer size in 'len'
  124. */
  125. #define MSM_INFO_GET_OFFSET 0x00 /* get mmap() offset, returned by value */
  126. #define MSM_INFO_GET_IOVA 0x01 /* get iova, returned by value */
  127. #define MSM_INFO_SET_NAME 0x02 /* set the debug name (by pointer) */
  128. #define MSM_INFO_GET_NAME 0x03 /* get debug name, returned by pointer */
  129. #define MSM_INFO_SET_IOVA 0x04 /* set the iova, passed by value */
  130. #define MSM_INFO_GET_FLAGS 0x05 /* get the MSM_BO_x flags */
  131. #define MSM_INFO_SET_METADATA 0x06 /* set userspace metadata */
  132. #define MSM_INFO_GET_METADATA 0x07 /* get userspace metadata */
  133. struct drm_msm_gem_info {
  134. __u32 handle; /* in */
  135. __u32 info; /* in - one of MSM_INFO_* */
  136. __u64 value; /* in or out */
  137. __u32 len; /* in or out */
  138. __u32 pad;
  139. };
  140. #define MSM_PREP_READ 0x01
  141. #define MSM_PREP_WRITE 0x02
  142. #define MSM_PREP_NOSYNC 0x04
  143. #define MSM_PREP_BOOST 0x08
  144. #define MSM_PREP_FLAGS (MSM_PREP_READ | \
  145. MSM_PREP_WRITE | \
  146. MSM_PREP_NOSYNC | \
  147. MSM_PREP_BOOST | \
  148. 0)
  149. struct drm_msm_gem_cpu_prep {
  150. __u32 handle; /* in */
  151. __u32 op; /* in, mask of MSM_PREP_x */
  152. struct drm_msm_timespec timeout; /* in */
  153. };
  154. struct drm_msm_gem_cpu_fini {
  155. __u32 handle; /* in */
  156. };
  157. /*
  158. * Cmdstream Submission:
  159. */
  160. /* The value written into the cmdstream is logically:
  161. *
  162. * ((relocbuf->gpuaddr + reloc_offset) << shift) | or
  163. *
  164. * When we have GPU's w/ >32bit ptrs, it should be possible to deal
  165. * with this by emit'ing two reloc entries with appropriate shift
  166. * values. Or a new MSM_SUBMIT_CMD_x type would also be an option.
  167. *
  168. * NOTE that reloc's must be sorted by order of increasing submit_offset,
  169. * otherwise EINVAL.
  170. */
  171. struct drm_msm_gem_submit_reloc {
  172. __u32 submit_offset; /* in, offset from submit_bo */
  173. #ifdef __cplusplus
  174. __u32 _or; /* in, value OR'd with result */
  175. #else
  176. __u32 or; /* in, value OR'd with result */
  177. #endif
  178. __s32 shift; /* in, amount of left shift (can be negative) */
  179. __u32 reloc_idx; /* in, index of reloc_bo buffer */
  180. __u64 reloc_offset; /* in, offset from start of reloc_bo */
  181. };
  182. /* submit-types:
  183. * BUF - this cmd buffer is executed normally.
  184. * IB_TARGET_BUF - this cmd buffer is an IB target. Reloc's are
  185. * processed normally, but the kernel does not setup an IB to
  186. * this buffer in the first-level ringbuffer
  187. * CTX_RESTORE_BUF - only executed if there has been a GPU context
  188. * switch since the last SUBMIT ioctl
  189. */
  190. #define MSM_SUBMIT_CMD_BUF 0x0001
  191. #define MSM_SUBMIT_CMD_IB_TARGET_BUF 0x0002
  192. #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
  193. struct drm_msm_gem_submit_cmd {
  194. __u32 type; /* in, one of MSM_SUBMIT_CMD_x */
  195. __u32 submit_idx; /* in, index of submit_bo cmdstream buffer */
  196. __u32 submit_offset; /* in, offset into submit_bo */
  197. __u32 size; /* in, cmdstream size */
  198. __u32 pad;
  199. __u32 nr_relocs; /* in, number of submit_reloc's */
  200. __u64 relocs; /* in, ptr to array of submit_reloc's */
  201. };
  202. /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
  203. * cmdstream buffer(s) themselves or reloc entries) has one (and only
  204. * one) entry in the submit->bos[] table.
  205. *
  206. * As a optimization, the current buffer (gpu virtual address) can be
  207. * passed back through the 'presumed' field. If on a subsequent reloc,
  208. * userspace passes back a 'presumed' address that is still valid,
  209. * then patching the cmdstream for this entry is skipped. This can
  210. * avoid kernel needing to map/access the cmdstream bo in the common
  211. * case.
  212. */
  213. #define MSM_SUBMIT_BO_READ 0x0001
  214. #define MSM_SUBMIT_BO_WRITE 0x0002
  215. #define MSM_SUBMIT_BO_DUMP 0x0004
  216. #define MSM_SUBMIT_BO_NO_IMPLICIT 0x0008
  217. #define MSM_SUBMIT_BO_FLAGS (MSM_SUBMIT_BO_READ | \
  218. MSM_SUBMIT_BO_WRITE | \
  219. MSM_SUBMIT_BO_DUMP | \
  220. MSM_SUBMIT_BO_NO_IMPLICIT)
  221. struct drm_msm_gem_submit_bo {
  222. __u32 flags; /* in, mask of MSM_SUBMIT_BO_x */
  223. __u32 handle; /* in, GEM handle */
  224. __u64 presumed; /* in/out, presumed buffer address */
  225. };
  226. /* Valid submit ioctl flags: */
  227. #define MSM_SUBMIT_NO_IMPLICIT 0x80000000 /* disable implicit sync */
  228. #define MSM_SUBMIT_FENCE_FD_IN 0x40000000 /* enable input fence_fd */
  229. #define MSM_SUBMIT_FENCE_FD_OUT 0x20000000 /* enable output fence_fd */
  230. #define MSM_SUBMIT_SUDO 0x10000000 /* run submitted cmds from RB */
  231. #define MSM_SUBMIT_SYNCOBJ_IN 0x08000000 /* enable input syncobj */
  232. #define MSM_SUBMIT_SYNCOBJ_OUT 0x04000000 /* enable output syncobj */
  233. #define MSM_SUBMIT_FENCE_SN_IN 0x02000000 /* userspace passes in seqno fence */
  234. #define MSM_SUBMIT_FLAGS ( \
  235. MSM_SUBMIT_NO_IMPLICIT | \
  236. MSM_SUBMIT_FENCE_FD_IN | \
  237. MSM_SUBMIT_FENCE_FD_OUT | \
  238. MSM_SUBMIT_SUDO | \
  239. MSM_SUBMIT_SYNCOBJ_IN | \
  240. MSM_SUBMIT_SYNCOBJ_OUT | \
  241. MSM_SUBMIT_FENCE_SN_IN | \
  242. 0)
  243. #define MSM_SUBMIT_SYNCOBJ_RESET 0x00000001 /* Reset syncobj after wait. */
  244. #define MSM_SUBMIT_SYNCOBJ_FLAGS ( \
  245. MSM_SUBMIT_SYNCOBJ_RESET | \
  246. 0)
  247. struct drm_msm_gem_submit_syncobj {
  248. __u32 handle; /* in, syncobj handle. */
  249. __u32 flags; /* in, from MSM_SUBMIT_SYNCOBJ_FLAGS */
  250. __u64 point; /* in, timepoint for timeline syncobjs. */
  251. };
  252. /* Each cmdstream submit consists of a table of buffers involved, and
  253. * one or more cmdstream buffers. This allows for conditional execution
  254. * (context-restore), and IB buffers needed for per tile/bin draw cmds.
  255. */
  256. struct drm_msm_gem_submit {
  257. __u32 flags; /* MSM_PIPE_x | MSM_SUBMIT_x */
  258. __u32 fence; /* out (or in with MSM_SUBMIT_FENCE_SN_IN flag) */
  259. __u32 nr_bos; /* in, number of submit_bo's */
  260. __u32 nr_cmds; /* in, number of submit_cmd's */
  261. __u64 bos; /* in, ptr to array of submit_bo's */
  262. __u64 cmds; /* in, ptr to array of submit_cmd's */
  263. __s32 fence_fd; /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
  264. __u32 queueid; /* in, submitqueue id */
  265. __u64 in_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
  266. __u64 out_syncobjs; /* in, ptr to array of drm_msm_gem_submit_syncobj */
  267. __u32 nr_in_syncobjs; /* in, number of entries in in_syncobj */
  268. __u32 nr_out_syncobjs; /* in, number of entries in out_syncobj. */
  269. __u32 syncobj_stride; /* in, stride of syncobj arrays. */
  270. __u32 pad; /*in, reserved for future use, always 0. */
  271. };
  272. #define MSM_WAIT_FENCE_BOOST 0x00000001
  273. #define MSM_WAIT_FENCE_FLAGS ( \
  274. MSM_WAIT_FENCE_BOOST | \
  275. 0)
  276. /* The normal way to synchronize with the GPU is just to CPU_PREP on
  277. * a buffer if you need to access it from the CPU (other cmdstream
  278. * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
  279. * handle the required synchronization under the hood). This ioctl
  280. * mainly just exists as a way to implement the gallium pipe_fence
  281. * APIs without requiring a dummy bo to synchronize on.
  282. */
  283. struct drm_msm_wait_fence {
  284. __u32 fence; /* in */
  285. __u32 flags; /* in, bitmask of MSM_WAIT_FENCE_x */
  286. struct drm_msm_timespec timeout; /* in */
  287. __u32 queueid; /* in, submitqueue id */
  288. };
  289. /* madvise provides a way to tell the kernel in case a buffers contents
  290. * can be discarded under memory pressure, which is useful for userspace
  291. * bo cache where we want to optimistically hold on to buffer allocate
  292. * and potential mmap, but allow the pages to be discarded under memory
  293. * pressure.
  294. *
  295. * Typical usage would involve madvise(DONTNEED) when buffer enters BO
  296. * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
  297. * In the WILLNEED case, 'retained' indicates to userspace whether the
  298. * backing pages still exist.
  299. */
  300. #define MSM_MADV_WILLNEED 0 /* backing pages are needed, status returned in 'retained' */
  301. #define MSM_MADV_DONTNEED 1 /* backing pages not needed */
  302. #define __MSM_MADV_PURGED 2 /* internal state */
  303. struct drm_msm_gem_madvise {
  304. __u32 handle; /* in, GEM handle */
  305. __u32 madv; /* in, MSM_MADV_x */
  306. __u32 retained; /* out, whether backing store still exists */
  307. };
  308. /*
  309. * Draw queues allow the user to set specific submission parameter. Command
  310. * submissions specify a specific submitqueue to use. ID 0 is reserved for
  311. * backwards compatibility as a "default" submitqueue
  312. */
  313. #define MSM_SUBMITQUEUE_FLAGS (0)
  314. /*
  315. * The submitqueue priority should be between 0 and MSM_PARAM_PRIORITIES-1,
  316. * a lower numeric value is higher priority.
  317. */
  318. struct drm_msm_submitqueue {
  319. __u32 flags; /* in, MSM_SUBMITQUEUE_x */
  320. __u32 prio; /* in, Priority level */
  321. __u32 id; /* out, identifier */
  322. };
  323. #define MSM_SUBMITQUEUE_PARAM_FAULTS 0
  324. struct drm_msm_submitqueue_query {
  325. __u64 data;
  326. __u32 id;
  327. __u32 param;
  328. __u32 len;
  329. __u32 pad;
  330. };
  331. #define DRM_MSM_GET_PARAM 0x00
  332. #define DRM_MSM_SET_PARAM 0x01
  333. #define DRM_MSM_GEM_NEW 0x02
  334. #define DRM_MSM_GEM_INFO 0x03
  335. #define DRM_MSM_GEM_CPU_PREP 0x04
  336. #define DRM_MSM_GEM_CPU_FINI 0x05
  337. #define DRM_MSM_GEM_SUBMIT 0x06
  338. #define DRM_MSM_WAIT_FENCE 0x07
  339. #define DRM_MSM_GEM_MADVISE 0x08
  340. /* placeholder:
  341. #define DRM_MSM_GEM_SVM_NEW 0x09
  342. */
  343. #define DRM_MSM_SUBMITQUEUE_NEW 0x0A
  344. #define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
  345. #define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
  346. #define DRM_IOCTL_MSM_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
  347. #define DRM_IOCTL_MSM_SET_PARAM DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SET_PARAM, struct drm_msm_param)
  348. #define DRM_IOCTL_MSM_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
  349. #define DRM_IOCTL_MSM_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
  350. #define DRM_IOCTL_MSM_GEM_CPU_PREP DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
  351. #define DRM_IOCTL_MSM_GEM_CPU_FINI DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
  352. #define DRM_IOCTL_MSM_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
  353. #define DRM_IOCTL_MSM_WAIT_FENCE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
  354. #define DRM_IOCTL_MSM_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
  355. #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
  356. #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
  357. #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
  358. #if defined(__cplusplus)
  359. }
  360. #endif
  361. #endif /* __MSM_DRM_H__ */