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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

ivpu_accel.h (11917B)


  1. /* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
  2. /*
  3. * Copyright (C) 2020-2024 Intel Corporation
  4. */
  5. #ifndef __UAPI_IVPU_DRM_H__
  6. #define __UAPI_IVPU_DRM_H__
  7. #include "drm.h"
  8. #if defined(__cplusplus)
  9. extern "C" {
  10. #endif
  11. #define DRM_IVPU_DRIVER_MAJOR 1
  12. #define DRM_IVPU_DRIVER_MINOR 0
  13. #define DRM_IVPU_GET_PARAM 0x00
  14. #define DRM_IVPU_SET_PARAM 0x01
  15. #define DRM_IVPU_BO_CREATE 0x02
  16. #define DRM_IVPU_BO_INFO 0x03
  17. #define DRM_IVPU_SUBMIT 0x05
  18. #define DRM_IVPU_BO_WAIT 0x06
  19. #define DRM_IVPU_METRIC_STREAMER_START 0x07
  20. #define DRM_IVPU_METRIC_STREAMER_STOP 0x08
  21. #define DRM_IVPU_METRIC_STREAMER_GET_DATA 0x09
  22. #define DRM_IVPU_METRIC_STREAMER_GET_INFO 0x0a
  23. #define DRM_IOCTL_IVPU_GET_PARAM \
  24. DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_GET_PARAM, struct drm_ivpu_param)
  25. #define DRM_IOCTL_IVPU_SET_PARAM \
  26. DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SET_PARAM, struct drm_ivpu_param)
  27. #define DRM_IOCTL_IVPU_BO_CREATE \
  28. DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_CREATE, struct drm_ivpu_bo_create)
  29. #define DRM_IOCTL_IVPU_BO_INFO \
  30. DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_INFO, struct drm_ivpu_bo_info)
  31. #define DRM_IOCTL_IVPU_SUBMIT \
  32. DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_SUBMIT, struct drm_ivpu_submit)
  33. #define DRM_IOCTL_IVPU_BO_WAIT \
  34. DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_BO_WAIT, struct drm_ivpu_bo_wait)
  35. #define DRM_IOCTL_IVPU_METRIC_STREAMER_START \
  36. DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_START, \
  37. struct drm_ivpu_metric_streamer_start)
  38. #define DRM_IOCTL_IVPU_METRIC_STREAMER_STOP \
  39. DRM_IOW(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_STOP, \
  40. struct drm_ivpu_metric_streamer_stop)
  41. #define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA \
  42. DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_DATA, \
  43. struct drm_ivpu_metric_streamer_get_data)
  44. #define DRM_IOCTL_IVPU_METRIC_STREAMER_GET_INFO \
  45. DRM_IOWR(DRM_COMMAND_BASE + DRM_IVPU_METRIC_STREAMER_GET_INFO, \
  46. struct drm_ivpu_metric_streamer_get_data)
  47. /**
  48. * DOC: contexts
  49. *
  50. * VPU contexts have private virtual address space, job queues and priority.
  51. * Each context is identified by an unique ID. Context is created on open().
  52. */
  53. #define DRM_IVPU_PARAM_DEVICE_ID 0
  54. #define DRM_IVPU_PARAM_DEVICE_REVISION 1
  55. #define DRM_IVPU_PARAM_PLATFORM_TYPE 2
  56. #define DRM_IVPU_PARAM_CORE_CLOCK_RATE 3
  57. #define DRM_IVPU_PARAM_NUM_CONTEXTS 4
  58. #define DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS 5
  59. #define DRM_IVPU_PARAM_CONTEXT_PRIORITY 6 /* Deprecated */
  60. #define DRM_IVPU_PARAM_CONTEXT_ID 7
  61. #define DRM_IVPU_PARAM_FW_API_VERSION 8
  62. #define DRM_IVPU_PARAM_ENGINE_HEARTBEAT 9
  63. #define DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID 10
  64. #define DRM_IVPU_PARAM_TILE_CONFIG 11
  65. #define DRM_IVPU_PARAM_SKU 12
  66. #define DRM_IVPU_PARAM_CAPABILITIES 13
  67. #define DRM_IVPU_PLATFORM_TYPE_SILICON 0
  68. /* Deprecated, use DRM_IVPU_JOB_PRIORITY */
  69. #define DRM_IVPU_CONTEXT_PRIORITY_IDLE 0
  70. #define DRM_IVPU_CONTEXT_PRIORITY_NORMAL 1
  71. #define DRM_IVPU_CONTEXT_PRIORITY_FOCUS 2
  72. #define DRM_IVPU_CONTEXT_PRIORITY_REALTIME 3
  73. #define DRM_IVPU_JOB_PRIORITY_DEFAULT 0
  74. #define DRM_IVPU_JOB_PRIORITY_IDLE 1
  75. #define DRM_IVPU_JOB_PRIORITY_NORMAL 2
  76. #define DRM_IVPU_JOB_PRIORITY_FOCUS 3
  77. #define DRM_IVPU_JOB_PRIORITY_REALTIME 4
  78. /**
  79. * DRM_IVPU_CAP_METRIC_STREAMER
  80. *
  81. * Metric streamer support. Provides sampling of various hardware performance
  82. * metrics like DMA bandwidth and cache miss/hits. Can be used for profiling.
  83. */
  84. #define DRM_IVPU_CAP_METRIC_STREAMER 1
  85. /**
  86. * DRM_IVPU_CAP_DMA_MEMORY_RANGE
  87. *
  88. * Driver has capability to allocate separate memory range
  89. * accessible by hardware DMA.
  90. */
  91. #define DRM_IVPU_CAP_DMA_MEMORY_RANGE 2
  92. /**
  93. * struct drm_ivpu_param - Get/Set VPU parameters
  94. */
  95. struct drm_ivpu_param {
  96. /**
  97. * @param:
  98. *
  99. * Supported params:
  100. *
  101. * %DRM_IVPU_PARAM_DEVICE_ID:
  102. * PCI Device ID of the VPU device (read-only)
  103. *
  104. * %DRM_IVPU_PARAM_DEVICE_REVISION:
  105. * VPU device revision (read-only)
  106. *
  107. * %DRM_IVPU_PARAM_PLATFORM_TYPE:
  108. * Returns %DRM_IVPU_PLATFORM_TYPE_SILICON on real hardware or device specific
  109. * platform type when executing on a simulator or emulator (read-only)
  110. *
  111. * %DRM_IVPU_PARAM_CORE_CLOCK_RATE:
  112. * Current PLL frequency (read-only)
  113. *
  114. * %DRM_IVPU_PARAM_NUM_CONTEXTS:
  115. * Maximum number of simultaneously existing contexts (read-only)
  116. *
  117. * %DRM_IVPU_PARAM_CONTEXT_BASE_ADDRESS:
  118. * Lowest VPU virtual address available in the current context (read-only)
  119. *
  120. * %DRM_IVPU_PARAM_CONTEXT_ID:
  121. * Current context ID, always greater than 0 (read-only)
  122. *
  123. * %DRM_IVPU_PARAM_FW_API_VERSION:
  124. * Firmware API version array (read-only)
  125. *
  126. * %DRM_IVPU_PARAM_ENGINE_HEARTBEAT:
  127. * Heartbeat value from an engine (read-only).
  128. * Engine ID (i.e. DRM_IVPU_ENGINE_COMPUTE) is given via index.
  129. *
  130. * %DRM_IVPU_PARAM_UNIQUE_INFERENCE_ID:
  131. * Device-unique inference ID (read-only)
  132. *
  133. * %DRM_IVPU_PARAM_TILE_CONFIG:
  134. * VPU tile configuration (read-only)
  135. *
  136. * %DRM_IVPU_PARAM_SKU:
  137. * VPU SKU ID (read-only)
  138. *
  139. * %DRM_IVPU_PARAM_CAPABILITIES:
  140. * Supported capabilities (read-only)
  141. */
  142. __u32 param;
  143. /** @index: Index for params that have multiple instances */
  144. __u32 index;
  145. /** @value: Param value */
  146. __u64 value;
  147. };
  148. #define DRM_IVPU_BO_SHAVE_MEM 0x00000001
  149. #define DRM_IVPU_BO_HIGH_MEM DRM_IVPU_BO_SHAVE_MEM
  150. #define DRM_IVPU_BO_MAPPABLE 0x00000002
  151. #define DRM_IVPU_BO_DMA_MEM 0x00000004
  152. #define DRM_IVPU_BO_CACHED 0x00000000
  153. #define DRM_IVPU_BO_UNCACHED 0x00010000
  154. #define DRM_IVPU_BO_WC 0x00020000
  155. #define DRM_IVPU_BO_CACHE_MASK 0x00030000
  156. #define DRM_IVPU_BO_FLAGS \
  157. (DRM_IVPU_BO_HIGH_MEM | \
  158. DRM_IVPU_BO_MAPPABLE | \
  159. DRM_IVPU_BO_DMA_MEM | \
  160. DRM_IVPU_BO_CACHE_MASK)
  161. /**
  162. * struct drm_ivpu_bo_create - Create BO backed by SHMEM
  163. *
  164. * Create GEM buffer object allocated in SHMEM memory.
  165. */
  166. struct drm_ivpu_bo_create {
  167. /** @size: The size in bytes of the allocated memory */
  168. __u64 size;
  169. /**
  170. * @flags:
  171. *
  172. * Supported flags:
  173. *
  174. * %DRM_IVPU_BO_HIGH_MEM:
  175. *
  176. * Allocate VPU address from >4GB range.
  177. * Buffer object with vpu address >4GB can be always accessed by the
  178. * VPU DMA engine, but some HW generation may not be able to access
  179. * this memory from then firmware running on the VPU management processor.
  180. * Suitable for input, output and some scratch buffers.
  181. *
  182. * %DRM_IVPU_BO_MAPPABLE:
  183. *
  184. * Buffer object can be mapped using mmap().
  185. *
  186. * %DRM_IVPU_BO_CACHED:
  187. *
  188. * Allocated BO will be cached on host side (WB) and snooped on the VPU side.
  189. * This is the default caching mode.
  190. *
  191. * %DRM_IVPU_BO_UNCACHED:
  192. *
  193. * Not supported. Use DRM_IVPU_BO_WC instead.
  194. *
  195. * %DRM_IVPU_BO_WC:
  196. *
  197. * Allocated BO will use write combining buffer for writes but reads will be
  198. * uncached.
  199. */
  200. __u32 flags;
  201. /** @handle: Returned GEM object handle */
  202. __u32 handle;
  203. /** @vpu_addr: Returned VPU virtual address */
  204. __u64 vpu_addr;
  205. };
  206. /**
  207. * struct drm_ivpu_bo_info - Query buffer object info
  208. */
  209. struct drm_ivpu_bo_info {
  210. /** @handle: Handle of the queried BO */
  211. __u32 handle;
  212. /** @flags: Returned flags used to create the BO */
  213. __u32 flags;
  214. /** @vpu_addr: Returned VPU virtual address */
  215. __u64 vpu_addr;
  216. /**
  217. * @mmap_offset:
  218. *
  219. * Returned offset to be used in mmap(). 0 in case the BO is not mappable.
  220. */
  221. __u64 mmap_offset;
  222. /** @size: Returned GEM object size, aligned to PAGE_SIZE */
  223. __u64 size;
  224. };
  225. /* drm_ivpu_submit engines */
  226. #define DRM_IVPU_ENGINE_COMPUTE 0
  227. #define DRM_IVPU_ENGINE_COPY 1
  228. /**
  229. * struct drm_ivpu_submit - Submit commands to the VPU
  230. *
  231. * Execute a single command buffer on a given VPU engine.
  232. * Handles to all referenced buffer objects have to be provided in @buffers_ptr.
  233. *
  234. * User space may wait on job completion using %DRM_IVPU_BO_WAIT ioctl.
  235. */
  236. struct drm_ivpu_submit {
  237. /**
  238. * @buffers_ptr:
  239. *
  240. * A pointer to an u32 array of GEM handles of the BOs required for this job.
  241. * The number of elements in the array must be equal to the value given by @buffer_count.
  242. *
  243. * The first BO is the command buffer. The rest of array has to contain all
  244. * BOs referenced from the command buffer.
  245. */
  246. __u64 buffers_ptr;
  247. /** @buffer_count: Number of elements in the @buffers_ptr */
  248. __u32 buffer_count;
  249. /**
  250. * @engine: Select the engine this job should be executed on
  251. *
  252. * %DRM_IVPU_ENGINE_COMPUTE:
  253. *
  254. * Performs Deep Learning Neural Compute Inference Operations
  255. *
  256. * %DRM_IVPU_ENGINE_COPY:
  257. *
  258. * Performs memory copy operations to/from system memory allocated for VPU
  259. */
  260. __u32 engine;
  261. /** @flags: Reserved for future use - must be zero */
  262. __u32 flags;
  263. /**
  264. * @commands_offset:
  265. *
  266. * Offset inside the first buffer in @buffers_ptr containing commands
  267. * to be executed. The offset has to be 8-byte aligned.
  268. */
  269. __u32 commands_offset;
  270. /**
  271. * @priority:
  272. *
  273. * Priority to be set for related job command queue, can be one of the following:
  274. * %DRM_IVPU_JOB_PRIORITY_DEFAULT
  275. * %DRM_IVPU_JOB_PRIORITY_IDLE
  276. * %DRM_IVPU_JOB_PRIORITY_NORMAL
  277. * %DRM_IVPU_JOB_PRIORITY_FOCUS
  278. * %DRM_IVPU_JOB_PRIORITY_REALTIME
  279. */
  280. __u32 priority;
  281. };
  282. /* drm_ivpu_bo_wait job status codes */
  283. #define DRM_IVPU_JOB_STATUS_SUCCESS 0
  284. #define DRM_IVPU_JOB_STATUS_ABORTED 256
  285. /**
  286. * struct drm_ivpu_bo_wait - Wait for BO to become inactive
  287. *
  288. * Blocks until a given buffer object becomes inactive.
  289. * With @timeout_ms set to 0 returns immediately.
  290. */
  291. struct drm_ivpu_bo_wait {
  292. /** @handle: Handle to the buffer object to be waited on */
  293. __u32 handle;
  294. /** @flags: Reserved for future use - must be zero */
  295. __u32 flags;
  296. /** @timeout_ns: Absolute timeout in nanoseconds (may be zero) */
  297. __s64 timeout_ns;
  298. /**
  299. * @job_status:
  300. *
  301. * Job status code which is updated after the job is completed.
  302. * &DRM_IVPU_JOB_STATUS_SUCCESS or device specific error otherwise.
  303. * Valid only if @handle points to a command buffer.
  304. */
  305. __u32 job_status;
  306. /** @pad: Padding - must be zero */
  307. __u32 pad;
  308. };
  309. /**
  310. * struct drm_ivpu_metric_streamer_start - Start collecting metric data
  311. */
  312. struct drm_ivpu_metric_streamer_start {
  313. /** @metric_group_mask: Indicates metric streamer instance */
  314. __u64 metric_group_mask;
  315. /** @sampling_period_ns: Sampling period in nanoseconds */
  316. __u64 sampling_period_ns;
  317. /**
  318. * @read_period_samples:
  319. *
  320. * Number of samples after which user space will try to read the data.
  321. * Reading the data after significantly longer period may cause data loss.
  322. */
  323. __u32 read_period_samples;
  324. /** @sample_size: Returned size of a single sample in bytes */
  325. __u32 sample_size;
  326. /** @max_data_size: Returned max @data_size from %DRM_IOCTL_IVPU_METRIC_STREAMER_GET_DATA */
  327. __u32 max_data_size;
  328. };
  329. /**
  330. * struct drm_ivpu_metric_streamer_get_data - Copy collected metric data
  331. */
  332. struct drm_ivpu_metric_streamer_get_data {
  333. /** @metric_group_mask: Indicates metric streamer instance */
  334. __u64 metric_group_mask;
  335. /** @buffer_ptr: A pointer to a destination for the copied data */
  336. __u64 buffer_ptr;
  337. /** @buffer_size: Size of the destination buffer */
  338. __u64 buffer_size;
  339. /**
  340. * @data_size: Returned size of copied metric data
  341. *
  342. * If the @buffer_size is zero, returns the amount of data ready to be copied.
  343. */
  344. __u64 data_size;
  345. };
  346. /**
  347. * struct drm_ivpu_metric_streamer_stop - Stop collecting metric data
  348. */
  349. struct drm_ivpu_metric_streamer_stop {
  350. /** @metric_group_mask: Indicates metric streamer instance */
  351. __u64 metric_group_mask;
  352. };
  353. #if defined(__cplusplus)
  354. }
  355. #endif
  356. #endif /* __UAPI_IVPU_DRM_H__ */