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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

i915_drm.h (131737B)


  1. /*
  2. * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
  3. * All Rights Reserved.
  4. *
  5. * Permission is hereby granted, free of charge, to any person obtaining a
  6. * copy of this software and associated documentation files (the
  7. * "Software"), to deal in the Software without restriction, including
  8. * without limitation the rights to use, copy, modify, merge, publish,
  9. * distribute, sub license, and/or sell copies of the Software, and to
  10. * permit persons to whom the Software is furnished to do so, subject to
  11. * the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the
  14. * next paragraph) shall be included in all copies or substantial portions
  15. * of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  18. * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  19. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  20. * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  21. * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  22. * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  23. * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  24. *
  25. */
  26. #ifndef _I915_DRM_H_
  27. #define _I915_DRM_H_
  28. #include "drm.h"
  29. #if defined(__cplusplus)
  30. extern "C" {
  31. #endif
  32. /* Please note that modifications to all structs defined here are
  33. * subject to backwards-compatibility constraints.
  34. */
  35. /**
  36. * DOC: uevents generated by i915 on its device node
  37. *
  38. * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch
  39. * event from the GPU L3 cache. Additional information supplied is ROW,
  40. * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep
  41. * track of these events, and if a specific cache-line seems to have a
  42. * persistent error, remap it with the L3 remapping tool supplied in
  43. * intel-gpu-tools. The value supplied with the event is always 1.
  44. *
  45. * I915_ERROR_UEVENT - Generated upon error detection, currently only via
  46. * hangcheck. The error detection event is a good indicator of when things
  47. * began to go badly. The value supplied with the event is a 1 upon error
  48. * detection, and a 0 upon reset completion, signifying no more error
  49. * exists. NOTE: Disabling hangcheck or reset via module parameter will
  50. * cause the related events to not be seen.
  51. *
  52. * I915_RESET_UEVENT - Event is generated just before an attempt to reset the
  53. * GPU. The value supplied with the event is always 1. NOTE: Disable
  54. * reset via module parameter will cause this event to not be seen.
  55. */
  56. #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR"
  57. #define I915_ERROR_UEVENT "ERROR"
  58. #define I915_RESET_UEVENT "RESET"
  59. /**
  60. * struct i915_user_extension - Base class for defining a chain of extensions
  61. *
  62. * Many interfaces need to grow over time. In most cases we can simply
  63. * extend the struct and have userspace pass in more data. Another option,
  64. * as demonstrated by Vulkan's approach to providing extensions for forward
  65. * and backward compatibility, is to use a list of optional structs to
  66. * provide those extra details.
  67. *
  68. * The key advantage to using an extension chain is that it allows us to
  69. * redefine the interface more easily than an ever growing struct of
  70. * increasing complexity, and for large parts of that interface to be
  71. * entirely optional. The downside is more pointer chasing; chasing across
  72. * the boundary with pointers encapsulated inside u64.
  73. *
  74. * Example chaining:
  75. *
  76. * .. code-block:: C
  77. *
  78. * struct i915_user_extension ext3 {
  79. * .next_extension = 0, // end
  80. * .name = ...,
  81. * };
  82. * struct i915_user_extension ext2 {
  83. * .next_extension = (uintptr_t)&ext3,
  84. * .name = ...,
  85. * };
  86. * struct i915_user_extension ext1 {
  87. * .next_extension = (uintptr_t)&ext2,
  88. * .name = ...,
  89. * };
  90. *
  91. * Typically the struct i915_user_extension would be embedded in some uAPI
  92. * struct, and in this case we would feed it the head of the chain(i.e ext1),
  93. * which would then apply all of the above extensions.
  94. *
  95. */
  96. struct i915_user_extension {
  97. /**
  98. * @next_extension:
  99. *
  100. * Pointer to the next struct i915_user_extension, or zero if the end.
  101. */
  102. __u64 next_extension;
  103. /**
  104. * @name: Name of the extension.
  105. *
  106. * Note that the name here is just some integer.
  107. *
  108. * Also note that the name space for this is not global for the whole
  109. * driver, but rather its scope/meaning is limited to the specific piece
  110. * of uAPI which has embedded the struct i915_user_extension.
  111. */
  112. __u32 name;
  113. /**
  114. * @flags: MBZ
  115. *
  116. * All undefined bits must be zero.
  117. */
  118. __u32 flags;
  119. /**
  120. * @rsvd: MBZ
  121. *
  122. * Reserved for future use; must be zero.
  123. */
  124. __u32 rsvd[4];
  125. };
  126. /*
  127. * MOCS indexes used for GPU surfaces, defining the cacheability of the
  128. * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
  129. */
  130. enum i915_mocs_table_index {
  131. /*
  132. * Not cached anywhere, coherency between CPU and GPU accesses is
  133. * guaranteed.
  134. */
  135. I915_MOCS_UNCACHED,
  136. /*
  137. * Cacheability and coherency controlled by the kernel automatically
  138. * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current
  139. * usage of the surface (used for display scanout or not).
  140. */
  141. I915_MOCS_PTE,
  142. /*
  143. * Cached in all GPU caches available on the platform.
  144. * Coherency between CPU and GPU accesses to the surface is not
  145. * guaranteed without extra synchronization.
  146. */
  147. I915_MOCS_CACHED,
  148. };
  149. /**
  150. * enum drm_i915_gem_engine_class - uapi engine type enumeration
  151. *
  152. * Different engines serve different roles, and there may be more than one
  153. * engine serving each role. This enum provides a classification of the role
  154. * of the engine, which may be used when requesting operations to be performed
  155. * on a certain subset of engines, or for providing information about that
  156. * group.
  157. */
  158. enum drm_i915_gem_engine_class {
  159. /**
  160. * @I915_ENGINE_CLASS_RENDER:
  161. *
  162. * Render engines support instructions used for 3D, Compute (GPGPU),
  163. * and programmable media workloads. These instructions fetch data and
  164. * dispatch individual work items to threads that operate in parallel.
  165. * The threads run small programs (called "kernels" or "shaders") on
  166. * the GPU's execution units (EUs).
  167. */
  168. I915_ENGINE_CLASS_RENDER = 0,
  169. /**
  170. * @I915_ENGINE_CLASS_COPY:
  171. *
  172. * Copy engines (also referred to as "blitters") support instructions
  173. * that move blocks of data from one location in memory to another,
  174. * or that fill a specified location of memory with fixed data.
  175. * Copy engines can perform pre-defined logical or bitwise operations
  176. * on the source, destination, or pattern data.
  177. */
  178. I915_ENGINE_CLASS_COPY = 1,
  179. /**
  180. * @I915_ENGINE_CLASS_VIDEO:
  181. *
  182. * Video engines (also referred to as "bit stream decode" (BSD) or
  183. * "vdbox") support instructions that perform fixed-function media
  184. * decode and encode.
  185. */
  186. I915_ENGINE_CLASS_VIDEO = 2,
  187. /**
  188. * @I915_ENGINE_CLASS_VIDEO_ENHANCE:
  189. *
  190. * Video enhancement engines (also referred to as "vebox") support
  191. * instructions related to image enhancement.
  192. */
  193. I915_ENGINE_CLASS_VIDEO_ENHANCE = 3,
  194. /**
  195. * @I915_ENGINE_CLASS_COMPUTE:
  196. *
  197. * Compute engines support a subset of the instructions available
  198. * on render engines: compute engines support Compute (GPGPU) and
  199. * programmable media workloads, but do not support the 3D pipeline.
  200. */
  201. I915_ENGINE_CLASS_COMPUTE = 4,
  202. /* Values in this enum should be kept compact. */
  203. /**
  204. * @I915_ENGINE_CLASS_INVALID:
  205. *
  206. * Placeholder value to represent an invalid engine class assignment.
  207. */
  208. I915_ENGINE_CLASS_INVALID = -1
  209. };
  210. /**
  211. * struct i915_engine_class_instance - Engine class/instance identifier
  212. *
  213. * There may be more than one engine fulfilling any role within the system.
  214. * Each engine of a class is given a unique instance number and therefore
  215. * any engine can be specified by its class:instance tuplet. APIs that allow
  216. * access to any engine in the system will use struct i915_engine_class_instance
  217. * for this identification.
  218. */
  219. struct i915_engine_class_instance {
  220. /**
  221. * @engine_class:
  222. *
  223. * Engine class from enum drm_i915_gem_engine_class
  224. */
  225. __u16 engine_class;
  226. #define I915_ENGINE_CLASS_INVALID_NONE -1
  227. #define I915_ENGINE_CLASS_INVALID_VIRTUAL -2
  228. /**
  229. * @engine_instance:
  230. *
  231. * Engine instance.
  232. */
  233. __u16 engine_instance;
  234. };
  235. /**
  236. * DOC: perf_events exposed by i915 through /sys/bus/event_sources/drivers/i915
  237. *
  238. */
  239. enum drm_i915_pmu_engine_sample {
  240. I915_SAMPLE_BUSY = 0,
  241. I915_SAMPLE_WAIT = 1,
  242. I915_SAMPLE_SEMA = 2
  243. };
  244. #define I915_PMU_SAMPLE_BITS (4)
  245. #define I915_PMU_SAMPLE_MASK (0xf)
  246. #define I915_PMU_SAMPLE_INSTANCE_BITS (8)
  247. #define I915_PMU_CLASS_SHIFT \
  248. (I915_PMU_SAMPLE_BITS + I915_PMU_SAMPLE_INSTANCE_BITS)
  249. #define __I915_PMU_ENGINE(class, instance, sample) \
  250. ((class) << I915_PMU_CLASS_SHIFT | \
  251. (instance) << I915_PMU_SAMPLE_BITS | \
  252. (sample))
  253. #define I915_PMU_ENGINE_BUSY(class, instance) \
  254. __I915_PMU_ENGINE(class, instance, I915_SAMPLE_BUSY)
  255. #define I915_PMU_ENGINE_WAIT(class, instance) \
  256. __I915_PMU_ENGINE(class, instance, I915_SAMPLE_WAIT)
  257. #define I915_PMU_ENGINE_SEMA(class, instance) \
  258. __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA)
  259. /*
  260. * Top 4 bits of every non-engine counter are GT id.
  261. */
  262. #define __I915_PMU_GT_SHIFT (60)
  263. #define ___I915_PMU_OTHER(gt, x) \
  264. (((__u64)__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) | \
  265. ((__u64)(gt) << __I915_PMU_GT_SHIFT))
  266. #define __I915_PMU_OTHER(x) ___I915_PMU_OTHER(0, x)
  267. #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)
  268. #define I915_PMU_REQUESTED_FREQUENCY __I915_PMU_OTHER(1)
  269. #define I915_PMU_INTERRUPTS __I915_PMU_OTHER(2)
  270. #define I915_PMU_RC6_RESIDENCY __I915_PMU_OTHER(3)
  271. #define I915_PMU_SOFTWARE_GT_AWAKE_TIME __I915_PMU_OTHER(4)
  272. #define I915_PMU_LAST /* Deprecated - do not use */ I915_PMU_RC6_RESIDENCY
  273. #define __I915_PMU_ACTUAL_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 0)
  274. #define __I915_PMU_REQUESTED_FREQUENCY(gt) ___I915_PMU_OTHER(gt, 1)
  275. #define __I915_PMU_INTERRUPTS(gt) ___I915_PMU_OTHER(gt, 2)
  276. #define __I915_PMU_RC6_RESIDENCY(gt) ___I915_PMU_OTHER(gt, 3)
  277. #define __I915_PMU_SOFTWARE_GT_AWAKE_TIME(gt) ___I915_PMU_OTHER(gt, 4)
  278. /* Each region is a minimum of 16k, and there are at most 255 of them.
  279. */
  280. #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
  281. * of chars for next/prev indices */
  282. #define I915_LOG_MIN_TEX_REGION_SIZE 14
  283. typedef struct _drm_i915_init {
  284. enum {
  285. I915_INIT_DMA = 0x01,
  286. I915_CLEANUP_DMA = 0x02,
  287. I915_RESUME_DMA = 0x03
  288. } func;
  289. unsigned int mmio_offset;
  290. int sarea_priv_offset;
  291. unsigned int ring_start;
  292. unsigned int ring_end;
  293. unsigned int ring_size;
  294. unsigned int front_offset;
  295. unsigned int back_offset;
  296. unsigned int depth_offset;
  297. unsigned int w;
  298. unsigned int h;
  299. unsigned int pitch;
  300. unsigned int pitch_bits;
  301. unsigned int back_pitch;
  302. unsigned int depth_pitch;
  303. unsigned int cpp;
  304. unsigned int chipset;
  305. } drm_i915_init_t;
  306. typedef struct _drm_i915_sarea {
  307. struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
  308. int last_upload; /* last time texture was uploaded */
  309. int last_enqueue; /* last time a buffer was enqueued */
  310. int last_dispatch; /* age of the most recently dispatched buffer */
  311. int ctxOwner; /* last context to upload state */
  312. int texAge;
  313. int pf_enabled; /* is pageflipping allowed? */
  314. int pf_active;
  315. int pf_current_page; /* which buffer is being displayed? */
  316. int perf_boxes; /* performance boxes to be displayed */
  317. int width, height; /* screen size in pixels */
  318. drm_handle_t front_handle;
  319. int front_offset;
  320. int front_size;
  321. drm_handle_t back_handle;
  322. int back_offset;
  323. int back_size;
  324. drm_handle_t depth_handle;
  325. int depth_offset;
  326. int depth_size;
  327. drm_handle_t tex_handle;
  328. int tex_offset;
  329. int tex_size;
  330. int log_tex_granularity;
  331. int pitch;
  332. int rotation; /* 0, 90, 180 or 270 */
  333. int rotated_offset;
  334. int rotated_size;
  335. int rotated_pitch;
  336. int virtualX, virtualY;
  337. unsigned int front_tiled;
  338. unsigned int back_tiled;
  339. unsigned int depth_tiled;
  340. unsigned int rotated_tiled;
  341. unsigned int rotated2_tiled;
  342. int pipeA_x;
  343. int pipeA_y;
  344. int pipeA_w;
  345. int pipeA_h;
  346. int pipeB_x;
  347. int pipeB_y;
  348. int pipeB_w;
  349. int pipeB_h;
  350. /* fill out some space for old userspace triple buffer */
  351. drm_handle_t unused_handle;
  352. __u32 unused1, unused2, unused3;
  353. /* buffer object handles for static buffers. May change
  354. * over the lifetime of the client.
  355. */
  356. __u32 front_bo_handle;
  357. __u32 back_bo_handle;
  358. __u32 unused_bo_handle;
  359. __u32 depth_bo_handle;
  360. } drm_i915_sarea_t;
  361. /* due to userspace building against these headers we need some compat here */
  362. #define planeA_x pipeA_x
  363. #define planeA_y pipeA_y
  364. #define planeA_w pipeA_w
  365. #define planeA_h pipeA_h
  366. #define planeB_x pipeB_x
  367. #define planeB_y pipeB_y
  368. #define planeB_w pipeB_w
  369. #define planeB_h pipeB_h
  370. /* Flags for perf_boxes
  371. */
  372. #define I915_BOX_RING_EMPTY 0x1
  373. #define I915_BOX_FLIP 0x2
  374. #define I915_BOX_WAIT 0x4
  375. #define I915_BOX_TEXTURE_LOAD 0x8
  376. #define I915_BOX_LOST_CONTEXT 0x10
  377. /*
  378. * i915 specific ioctls.
  379. *
  380. * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie
  381. * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset
  382. * against DRM_COMMAND_BASE and should be between [0x0, 0x60).
  383. */
  384. #define DRM_I915_INIT 0x00
  385. #define DRM_I915_FLUSH 0x01
  386. #define DRM_I915_FLIP 0x02
  387. #define DRM_I915_BATCHBUFFER 0x03
  388. #define DRM_I915_IRQ_EMIT 0x04
  389. #define DRM_I915_IRQ_WAIT 0x05
  390. #define DRM_I915_GETPARAM 0x06
  391. #define DRM_I915_SETPARAM 0x07
  392. #define DRM_I915_ALLOC 0x08
  393. #define DRM_I915_FREE 0x09
  394. #define DRM_I915_INIT_HEAP 0x0a
  395. #define DRM_I915_CMDBUFFER 0x0b
  396. #define DRM_I915_DESTROY_HEAP 0x0c
  397. #define DRM_I915_SET_VBLANK_PIPE 0x0d
  398. #define DRM_I915_GET_VBLANK_PIPE 0x0e
  399. #define DRM_I915_VBLANK_SWAP 0x0f
  400. #define DRM_I915_HWS_ADDR 0x11
  401. #define DRM_I915_GEM_INIT 0x13
  402. #define DRM_I915_GEM_EXECBUFFER 0x14
  403. #define DRM_I915_GEM_PIN 0x15
  404. #define DRM_I915_GEM_UNPIN 0x16
  405. #define DRM_I915_GEM_BUSY 0x17
  406. #define DRM_I915_GEM_THROTTLE 0x18
  407. #define DRM_I915_GEM_ENTERVT 0x19
  408. #define DRM_I915_GEM_LEAVEVT 0x1a
  409. #define DRM_I915_GEM_CREATE 0x1b
  410. #define DRM_I915_GEM_PREAD 0x1c
  411. #define DRM_I915_GEM_PWRITE 0x1d
  412. #define DRM_I915_GEM_MMAP 0x1e
  413. #define DRM_I915_GEM_SET_DOMAIN 0x1f
  414. #define DRM_I915_GEM_SW_FINISH 0x20
  415. #define DRM_I915_GEM_SET_TILING 0x21
  416. #define DRM_I915_GEM_GET_TILING 0x22
  417. #define DRM_I915_GEM_GET_APERTURE 0x23
  418. #define DRM_I915_GEM_MMAP_GTT 0x24
  419. #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
  420. #define DRM_I915_GEM_MADVISE 0x26
  421. #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
  422. #define DRM_I915_OVERLAY_ATTRS 0x28
  423. #define DRM_I915_GEM_EXECBUFFER2 0x29
  424. #define DRM_I915_GEM_EXECBUFFER2_WR DRM_I915_GEM_EXECBUFFER2
  425. #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
  426. #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
  427. #define DRM_I915_GEM_WAIT 0x2c
  428. #define DRM_I915_GEM_CONTEXT_CREATE 0x2d
  429. #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e
  430. #define DRM_I915_GEM_SET_CACHING 0x2f
  431. #define DRM_I915_GEM_GET_CACHING 0x30
  432. #define DRM_I915_REG_READ 0x31
  433. #define DRM_I915_GET_RESET_STATS 0x32
  434. #define DRM_I915_GEM_USERPTR 0x33
  435. #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
  436. #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
  437. #define DRM_I915_PERF_OPEN 0x36
  438. #define DRM_I915_PERF_ADD_CONFIG 0x37
  439. #define DRM_I915_PERF_REMOVE_CONFIG 0x38
  440. #define DRM_I915_QUERY 0x39
  441. #define DRM_I915_GEM_VM_CREATE 0x3a
  442. #define DRM_I915_GEM_VM_DESTROY 0x3b
  443. #define DRM_I915_GEM_CREATE_EXT 0x3c
  444. /* Must be kept compact -- no holes */
  445. #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
  446. #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
  447. #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP)
  448. #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
  449. #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
  450. #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
  451. #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
  452. #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
  453. #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
  454. #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
  455. #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
  456. #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
  457. #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
  458. #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
  459. #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
  460. #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
  461. #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init)
  462. #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
  463. #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
  464. #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
  465. #define DRM_IOCTL_I915_GEM_EXECBUFFER2_WR DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2_WR, struct drm_i915_gem_execbuffer2)
  466. #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
  467. #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
  468. #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
  469. #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching)
  470. #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching)
  471. #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
  472. #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
  473. #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
  474. #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
  475. #define DRM_IOCTL_I915_GEM_CREATE_EXT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE_EXT, struct drm_i915_gem_create_ext)
  476. #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
  477. #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
  478. #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
  479. #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
  480. #define DRM_IOCTL_I915_GEM_MMAP_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_offset)
  481. #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
  482. #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
  483. #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
  484. #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
  485. #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
  486. #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
  487. #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
  488. #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
  489. #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
  490. #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
  491. #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
  492. #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait)
  493. #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
  494. #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE_EXT DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create_ext)
  495. #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
  496. #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
  497. #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
  498. #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
  499. #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
  500. #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
  501. #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param)
  502. #define DRM_IOCTL_I915_PERF_ADD_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_ADD_CONFIG, struct drm_i915_perf_oa_config)
  503. #define DRM_IOCTL_I915_PERF_REMOVE_CONFIG DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_REMOVE_CONFIG, __u64)
  504. #define DRM_IOCTL_I915_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_QUERY, struct drm_i915_query)
  505. #define DRM_IOCTL_I915_GEM_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_VM_CREATE, struct drm_i915_gem_vm_control)
  506. #define DRM_IOCTL_I915_GEM_VM_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_VM_DESTROY, struct drm_i915_gem_vm_control)
  507. /* Allow drivers to submit batchbuffers directly to hardware, relying
  508. * on the security mechanisms provided by hardware.
  509. */
  510. typedef struct drm_i915_batchbuffer {
  511. int start; /* agp offset */
  512. int used; /* nr bytes in use */
  513. int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
  514. int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
  515. int num_cliprects; /* mulitpass with multiple cliprects? */
  516. struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
  517. } drm_i915_batchbuffer_t;
  518. /* As above, but pass a pointer to userspace buffer which can be
  519. * validated by the kernel prior to sending to hardware.
  520. */
  521. typedef struct _drm_i915_cmdbuffer {
  522. char *buf; /* pointer to userspace command buffer */
  523. int sz; /* nr bytes in buf */
  524. int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
  525. int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
  526. int num_cliprects; /* mulitpass with multiple cliprects? */
  527. struct drm_clip_rect *cliprects; /* pointer to userspace cliprects */
  528. } drm_i915_cmdbuffer_t;
  529. /* Userspace can request & wait on irq's:
  530. */
  531. typedef struct drm_i915_irq_emit {
  532. int *irq_seq;
  533. } drm_i915_irq_emit_t;
  534. typedef struct drm_i915_irq_wait {
  535. int irq_seq;
  536. } drm_i915_irq_wait_t;
  537. /*
  538. * Different modes of per-process Graphics Translation Table,
  539. * see I915_PARAM_HAS_ALIASING_PPGTT
  540. */
  541. #define I915_GEM_PPGTT_NONE 0
  542. #define I915_GEM_PPGTT_ALIASING 1
  543. #define I915_GEM_PPGTT_FULL 2
  544. /* Ioctl to query kernel params:
  545. */
  546. #define I915_PARAM_IRQ_ACTIVE 1
  547. #define I915_PARAM_ALLOW_BATCHBUFFER 2
  548. #define I915_PARAM_LAST_DISPATCH 3
  549. #define I915_PARAM_CHIPSET_ID 4
  550. #define I915_PARAM_HAS_GEM 5
  551. #define I915_PARAM_NUM_FENCES_AVAIL 6
  552. #define I915_PARAM_HAS_OVERLAY 7
  553. #define I915_PARAM_HAS_PAGEFLIPPING 8
  554. #define I915_PARAM_HAS_EXECBUF2 9
  555. #define I915_PARAM_HAS_BSD 10
  556. #define I915_PARAM_HAS_BLT 11
  557. #define I915_PARAM_HAS_RELAXED_FENCING 12
  558. #define I915_PARAM_HAS_COHERENT_RINGS 13
  559. #define I915_PARAM_HAS_EXEC_CONSTANTS 14
  560. #define I915_PARAM_HAS_RELAXED_DELTA 15
  561. #define I915_PARAM_HAS_GEN7_SOL_RESET 16
  562. #define I915_PARAM_HAS_LLC 17
  563. #define I915_PARAM_HAS_ALIASING_PPGTT 18
  564. #define I915_PARAM_HAS_WAIT_TIMEOUT 19
  565. #define I915_PARAM_HAS_SEMAPHORES 20
  566. #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21
  567. #define I915_PARAM_HAS_VEBOX 22
  568. #define I915_PARAM_HAS_SECURE_BATCHES 23
  569. #define I915_PARAM_HAS_PINNED_BATCHES 24
  570. #define I915_PARAM_HAS_EXEC_NO_RELOC 25
  571. #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
  572. #define I915_PARAM_HAS_WT 27
  573. #define I915_PARAM_CMD_PARSER_VERSION 28
  574. #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
  575. #define I915_PARAM_MMAP_VERSION 30
  576. #define I915_PARAM_HAS_BSD2 31
  577. #define I915_PARAM_REVISION 32
  578. #define I915_PARAM_SUBSLICE_TOTAL 33
  579. #define I915_PARAM_EU_TOTAL 34
  580. #define I915_PARAM_HAS_GPU_RESET 35
  581. #define I915_PARAM_HAS_RESOURCE_STREAMER 36
  582. #define I915_PARAM_HAS_EXEC_SOFTPIN 37
  583. #define I915_PARAM_HAS_POOLED_EU 38
  584. #define I915_PARAM_MIN_EU_IN_POOL 39
  585. #define I915_PARAM_MMAP_GTT_VERSION 40
  586. /*
  587. * Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution
  588. * priorities and the driver will attempt to execute batches in priority order.
  589. * The param returns a capability bitmask, nonzero implies that the scheduler
  590. * is enabled, with different features present according to the mask.
  591. *
  592. * The initial priority for each batch is supplied by the context and is
  593. * controlled via I915_CONTEXT_PARAM_PRIORITY.
  594. */
  595. #define I915_PARAM_HAS_SCHEDULER 41
  596. #define I915_SCHEDULER_CAP_ENABLED (1ul << 0)
  597. #define I915_SCHEDULER_CAP_PRIORITY (1ul << 1)
  598. #define I915_SCHEDULER_CAP_PREEMPTION (1ul << 2)
  599. #define I915_SCHEDULER_CAP_SEMAPHORES (1ul << 3)
  600. #define I915_SCHEDULER_CAP_ENGINE_BUSY_STATS (1ul << 4)
  601. /*
  602. * Indicates the 2k user priority levels are statically mapped into 3 buckets as
  603. * follows:
  604. *
  605. * -1k to -1 Low priority
  606. * 0 Normal priority
  607. * 1 to 1k Highest priority
  608. */
  609. #define I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP (1ul << 5)
  610. /*
  611. * Query the status of HuC load.
  612. *
  613. * The query can fail in the following scenarios with the listed error codes:
  614. * -ENODEV if HuC is not present on this platform,
  615. * -EOPNOTSUPP if HuC firmware usage is disabled,
  616. * -ENOPKG if HuC firmware fetch failed,
  617. * -ENOEXEC if HuC firmware is invalid or mismatched,
  618. * -ENOMEM if i915 failed to prepare the FW objects for transfer to the uC,
  619. * -EIO if the FW transfer or the FW authentication failed.
  620. *
  621. * If the IOCTL is successful, the returned parameter will be set to one of the
  622. * following values:
  623. * * 0 if HuC firmware load is not complete,
  624. * * 1 if HuC firmware is loaded and fully authenticated,
  625. * * 2 if HuC firmware is loaded and authenticated for clear media only
  626. */
  627. #define I915_PARAM_HUC_STATUS 42
  628. /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to opt-out of
  629. * synchronisation with implicit fencing on individual objects.
  630. * See EXEC_OBJECT_ASYNC.
  631. */
  632. #define I915_PARAM_HAS_EXEC_ASYNC 43
  633. /* Query whether DRM_I915_GEM_EXECBUFFER2 supports explicit fence support -
  634. * both being able to pass in a sync_file fd to wait upon before executing,
  635. * and being able to return a new sync_file fd that is signaled when the
  636. * current request is complete. See I915_EXEC_FENCE_IN and I915_EXEC_FENCE_OUT.
  637. */
  638. #define I915_PARAM_HAS_EXEC_FENCE 44
  639. /* Query whether DRM_I915_GEM_EXECBUFFER2 supports the ability to capture
  640. * user-specified buffers for post-mortem debugging of GPU hangs. See
  641. * EXEC_OBJECT_CAPTURE.
  642. */
  643. #define I915_PARAM_HAS_EXEC_CAPTURE 45
  644. #define I915_PARAM_SLICE_MASK 46
  645. /* Assuming it's uniform for each slice, this queries the mask of subslices
  646. * per-slice for this system.
  647. */
  648. #define I915_PARAM_SUBSLICE_MASK 47
  649. /*
  650. * Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying the batch buffer
  651. * as the first execobject as opposed to the last. See I915_EXEC_BATCH_FIRST.
  652. */
  653. #define I915_PARAM_HAS_EXEC_BATCH_FIRST 48
  654. /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
  655. * drm_i915_gem_exec_fence structures. See I915_EXEC_FENCE_ARRAY.
  656. */
  657. #define I915_PARAM_HAS_EXEC_FENCE_ARRAY 49
  658. /*
  659. * Query whether every context (both per-file default and user created) is
  660. * isolated (insofar as HW supports). If this parameter is not true, then
  661. * freshly created contexts may inherit values from an existing context,
  662. * rather than default HW values. If true, it also ensures (insofar as HW
  663. * supports) that all state set by this context will not leak to any other
  664. * context.
  665. *
  666. * As not every engine across every gen support contexts, the returned
  667. * value reports the support of context isolation for individual engines by
  668. * returning a bitmask of each engine class set to true if that class supports
  669. * isolation.
  670. */
  671. #define I915_PARAM_HAS_CONTEXT_ISOLATION 50
  672. /* Frequency of the command streamer timestamps given by the *_TIMESTAMP
  673. * registers. This used to be fixed per platform but from CNL onwards, this
  674. * might vary depending on the parts.
  675. */
  676. #define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51
  677. /*
  678. * Once upon a time we supposed that writes through the GGTT would be
  679. * immediately in physical memory (once flushed out of the CPU path). However,
  680. * on a few different processors and chipsets, this is not necessarily the case
  681. * as the writes appear to be buffered internally. Thus a read of the backing
  682. * storage (physical memory) via a different path (with different physical tags
  683. * to the indirect write via the GGTT) will see stale values from before
  684. * the GGTT write. Inside the kernel, we can for the most part keep track of
  685. * the different read/write domains in use (e.g. set-domain), but the assumption
  686. * of coherency is baked into the ABI, hence reporting its true state in this
  687. * parameter.
  688. *
  689. * Reports true when writes via mmap_gtt are immediately visible following an
  690. * lfence to flush the WCB.
  691. *
  692. * Reports false when writes via mmap_gtt are indeterminately delayed in an in
  693. * internal buffer and are _not_ immediately visible to third parties accessing
  694. * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC
  695. * communications channel when reporting false is strongly disadvised.
  696. */
  697. #define I915_PARAM_MMAP_GTT_COHERENT 52
  698. /*
  699. * Query whether DRM_I915_GEM_EXECBUFFER2 supports coordination of parallel
  700. * execution through use of explicit fence support.
  701. * See I915_EXEC_FENCE_OUT and I915_EXEC_FENCE_SUBMIT.
  702. */
  703. #define I915_PARAM_HAS_EXEC_SUBMIT_FENCE 53
  704. /*
  705. * Revision of the i915-perf uAPI. The value returned helps determine what
  706. * i915-perf features are available. See drm_i915_perf_property_id.
  707. */
  708. #define I915_PARAM_PERF_REVISION 54
  709. /* Query whether DRM_I915_GEM_EXECBUFFER2 supports supplying an array of
  710. * timeline syncobj through drm_i915_gem_execbuffer_ext_timeline_fences. See
  711. * I915_EXEC_USE_EXTENSIONS.
  712. */
  713. #define I915_PARAM_HAS_EXEC_TIMELINE_FENCES 55
  714. /* Query if the kernel supports the I915_USERPTR_PROBE flag. */
  715. #define I915_PARAM_HAS_USERPTR_PROBE 56
  716. /*
  717. * Frequency of the timestamps in OA reports. This used to be the same as the CS
  718. * timestamp frequency, but differs on some platforms.
  719. */
  720. #define I915_PARAM_OA_TIMESTAMP_FREQUENCY 57
  721. /*
  722. * Query the status of PXP support in i915.
  723. *
  724. * The query can fail in the following scenarios with the listed error codes:
  725. * -ENODEV = PXP support is not available on the GPU device or in the
  726. * kernel due to missing component drivers or kernel configs.
  727. *
  728. * If the IOCTL is successful, the returned parameter will be set to one of
  729. * the following values:
  730. * 1 = PXP feature is supported and is ready for use.
  731. * 2 = PXP feature is supported but should be ready soon (pending
  732. * initialization of non-i915 system dependencies).
  733. *
  734. * NOTE: When param is supported (positive return values), user space should
  735. * still refer to the GEM PXP context-creation UAPI header specs to be
  736. * aware of possible failure due to system state machine at the time.
  737. */
  738. #define I915_PARAM_PXP_STATUS 58
  739. /*
  740. * Query if kernel allows marking a context to send a Freq hint to SLPC. This
  741. * will enable use of the strategies allowed by the SLPC algorithm.
  742. */
  743. #define I915_PARAM_HAS_CONTEXT_FREQ_HINT 59
  744. /* Must be kept compact -- no holes and well documented */
  745. /**
  746. * struct drm_i915_getparam - Driver parameter query structure.
  747. */
  748. struct drm_i915_getparam {
  749. /** @param: Driver parameter to query. */
  750. __s32 param;
  751. /**
  752. * @value: Address of memory where queried value should be put.
  753. *
  754. * WARNING: Using pointers instead of fixed-size u64 means we need to write
  755. * compat32 code. Don't repeat this mistake.
  756. */
  757. int *value;
  758. };
  759. /**
  760. * typedef drm_i915_getparam_t - Driver parameter query structure.
  761. * See struct drm_i915_getparam.
  762. */
  763. typedef struct drm_i915_getparam drm_i915_getparam_t;
  764. /* Ioctl to set kernel params:
  765. */
  766. #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
  767. #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
  768. #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
  769. #define I915_SETPARAM_NUM_USED_FENCES 4
  770. /* Must be kept compact -- no holes */
  771. typedef struct drm_i915_setparam {
  772. int param;
  773. int value;
  774. } drm_i915_setparam_t;
  775. /* A memory manager for regions of shared memory:
  776. */
  777. #define I915_MEM_REGION_AGP 1
  778. typedef struct drm_i915_mem_alloc {
  779. int region;
  780. int alignment;
  781. int size;
  782. int *region_offset; /* offset from start of fb or agp */
  783. } drm_i915_mem_alloc_t;
  784. typedef struct drm_i915_mem_free {
  785. int region;
  786. int region_offset;
  787. } drm_i915_mem_free_t;
  788. typedef struct drm_i915_mem_init_heap {
  789. int region;
  790. int size;
  791. int start;
  792. } drm_i915_mem_init_heap_t;
  793. /* Allow memory manager to be torn down and re-initialized (eg on
  794. * rotate):
  795. */
  796. typedef struct drm_i915_mem_destroy_heap {
  797. int region;
  798. } drm_i915_mem_destroy_heap_t;
  799. /* Allow X server to configure which pipes to monitor for vblank signals
  800. */
  801. #define DRM_I915_VBLANK_PIPE_A 1
  802. #define DRM_I915_VBLANK_PIPE_B 2
  803. typedef struct drm_i915_vblank_pipe {
  804. int pipe;
  805. } drm_i915_vblank_pipe_t;
  806. /* Schedule buffer swap at given vertical blank:
  807. */
  808. typedef struct drm_i915_vblank_swap {
  809. drm_drawable_t drawable;
  810. enum drm_vblank_seq_type seqtype;
  811. unsigned int sequence;
  812. } drm_i915_vblank_swap_t;
  813. typedef struct drm_i915_hws_addr {
  814. __u64 addr;
  815. } drm_i915_hws_addr_t;
  816. struct drm_i915_gem_init {
  817. /**
  818. * Beginning offset in the GTT to be managed by the DRM memory
  819. * manager.
  820. */
  821. __u64 gtt_start;
  822. /**
  823. * Ending offset in the GTT to be managed by the DRM memory
  824. * manager.
  825. */
  826. __u64 gtt_end;
  827. };
  828. struct drm_i915_gem_create {
  829. /**
  830. * Requested size for the object.
  831. *
  832. * The (page-aligned) allocated size for the object will be returned.
  833. */
  834. __u64 size;
  835. /**
  836. * Returned handle for the object.
  837. *
  838. * Object handles are nonzero.
  839. */
  840. __u32 handle;
  841. __u32 pad;
  842. };
  843. struct drm_i915_gem_pread {
  844. /** Handle for the object being read. */
  845. __u32 handle;
  846. __u32 pad;
  847. /** Offset into the object to read from */
  848. __u64 offset;
  849. /** Length of data to read */
  850. __u64 size;
  851. /**
  852. * Pointer to write the data into.
  853. *
  854. * This is a fixed-size type for 32/64 compatibility.
  855. */
  856. __u64 data_ptr;
  857. };
  858. struct drm_i915_gem_pwrite {
  859. /** Handle for the object being written to. */
  860. __u32 handle;
  861. __u32 pad;
  862. /** Offset into the object to write to */
  863. __u64 offset;
  864. /** Length of data to write */
  865. __u64 size;
  866. /**
  867. * Pointer to read the data from.
  868. *
  869. * This is a fixed-size type for 32/64 compatibility.
  870. */
  871. __u64 data_ptr;
  872. };
  873. struct drm_i915_gem_mmap {
  874. /** Handle for the object being mapped. */
  875. __u32 handle;
  876. __u32 pad;
  877. /** Offset in the object to map. */
  878. __u64 offset;
  879. /**
  880. * Length of data to map.
  881. *
  882. * The value will be page-aligned.
  883. */
  884. __u64 size;
  885. /**
  886. * Returned pointer the data was mapped at.
  887. *
  888. * This is a fixed-size type for 32/64 compatibility.
  889. */
  890. __u64 addr_ptr;
  891. /**
  892. * Flags for extended behaviour.
  893. *
  894. * Added in version 2.
  895. */
  896. __u64 flags;
  897. #define I915_MMAP_WC 0x1
  898. };
  899. struct drm_i915_gem_mmap_gtt {
  900. /** Handle for the object being mapped. */
  901. __u32 handle;
  902. __u32 pad;
  903. /**
  904. * Fake offset to use for subsequent mmap call
  905. *
  906. * This is a fixed-size type for 32/64 compatibility.
  907. */
  908. __u64 offset;
  909. };
  910. /**
  911. * struct drm_i915_gem_mmap_offset - Retrieve an offset so we can mmap this buffer object.
  912. *
  913. * This struct is passed as argument to the `DRM_IOCTL_I915_GEM_MMAP_OFFSET` ioctl,
  914. * and is used to retrieve the fake offset to mmap an object specified by &handle.
  915. *
  916. * The legacy way of using `DRM_IOCTL_I915_GEM_MMAP` is removed on gen12+.
  917. * `DRM_IOCTL_I915_GEM_MMAP_GTT` is an older supported alias to this struct, but will behave
  918. * as setting the &extensions to 0, and &flags to `I915_MMAP_OFFSET_GTT`.
  919. */
  920. struct drm_i915_gem_mmap_offset {
  921. /** @handle: Handle for the object being mapped. */
  922. __u32 handle;
  923. /** @pad: Must be zero */
  924. __u32 pad;
  925. /**
  926. * @offset: The fake offset to use for subsequent mmap call
  927. *
  928. * This is a fixed-size type for 32/64 compatibility.
  929. */
  930. __u64 offset;
  931. /**
  932. * @flags: Flags for extended behaviour.
  933. *
  934. * It is mandatory that one of the `MMAP_OFFSET` types
  935. * should be included:
  936. *
  937. * - `I915_MMAP_OFFSET_GTT`: Use mmap with the object bound to GTT. (Write-Combined)
  938. * - `I915_MMAP_OFFSET_WC`: Use Write-Combined caching.
  939. * - `I915_MMAP_OFFSET_WB`: Use Write-Back caching.
  940. * - `I915_MMAP_OFFSET_FIXED`: Use object placement to determine caching.
  941. *
  942. * On devices with local memory `I915_MMAP_OFFSET_FIXED` is the only valid
  943. * type. On devices without local memory, this caching mode is invalid.
  944. *
  945. * As caching mode when specifying `I915_MMAP_OFFSET_FIXED`, WC or WB will
  946. * be used, depending on the object placement on creation. WB will be used
  947. * when the object can only exist in system memory, WC otherwise.
  948. */
  949. __u64 flags;
  950. #define I915_MMAP_OFFSET_GTT 0
  951. #define I915_MMAP_OFFSET_WC 1
  952. #define I915_MMAP_OFFSET_WB 2
  953. #define I915_MMAP_OFFSET_UC 3
  954. #define I915_MMAP_OFFSET_FIXED 4
  955. /**
  956. * @extensions: Zero-terminated chain of extensions.
  957. *
  958. * No current extensions defined; mbz.
  959. */
  960. __u64 extensions;
  961. };
  962. /**
  963. * struct drm_i915_gem_set_domain - Adjust the objects write or read domain, in
  964. * preparation for accessing the pages via some CPU domain.
  965. *
  966. * Specifying a new write or read domain will flush the object out of the
  967. * previous domain(if required), before then updating the objects domain
  968. * tracking with the new domain.
  969. *
  970. * Note this might involve waiting for the object first if it is still active on
  971. * the GPU.
  972. *
  973. * Supported values for @read_domains and @write_domain:
  974. *
  975. * - I915_GEM_DOMAIN_WC: Uncached write-combined domain
  976. * - I915_GEM_DOMAIN_CPU: CPU cache domain
  977. * - I915_GEM_DOMAIN_GTT: Mappable aperture domain
  978. *
  979. * All other domains are rejected.
  980. *
  981. * Note that for discrete, starting from DG1, this is no longer supported, and
  982. * is instead rejected. On such platforms the CPU domain is effectively static,
  983. * where we also only support a single &drm_i915_gem_mmap_offset cache mode,
  984. * which can't be set explicitly and instead depends on the object placements,
  985. * as per the below.
  986. *
  987. * Implicit caching rules, starting from DG1:
  988. *
  989. * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
  990. * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
  991. * mapped as write-combined only.
  992. *
  993. * - Everything else is always allocated and mapped as write-back, with the
  994. * guarantee that everything is also coherent with the GPU.
  995. *
  996. * Note that this is likely to change in the future again, where we might need
  997. * more flexibility on future devices, so making this all explicit as part of a
  998. * new &drm_i915_gem_create_ext extension is probable.
  999. */
  1000. struct drm_i915_gem_set_domain {
  1001. /** @handle: Handle for the object. */
  1002. __u32 handle;
  1003. /** @read_domains: New read domains. */
  1004. __u32 read_domains;
  1005. /**
  1006. * @write_domain: New write domain.
  1007. *
  1008. * Note that having something in the write domain implies it's in the
  1009. * read domain, and only that read domain.
  1010. */
  1011. __u32 write_domain;
  1012. };
  1013. struct drm_i915_gem_sw_finish {
  1014. /** Handle for the object */
  1015. __u32 handle;
  1016. };
  1017. struct drm_i915_gem_relocation_entry {
  1018. /**
  1019. * Handle of the buffer being pointed to by this relocation entry.
  1020. *
  1021. * It's appealing to make this be an index into the mm_validate_entry
  1022. * list to refer to the buffer, but this allows the driver to create
  1023. * a relocation list for state buffers and not re-write it per
  1024. * exec using the buffer.
  1025. */
  1026. __u32 target_handle;
  1027. /**
  1028. * Value to be added to the offset of the target buffer to make up
  1029. * the relocation entry.
  1030. */
  1031. __u32 delta;
  1032. /** Offset in the buffer the relocation entry will be written into */
  1033. __u64 offset;
  1034. /**
  1035. * Offset value of the target buffer that the relocation entry was last
  1036. * written as.
  1037. *
  1038. * If the buffer has the same offset as last time, we can skip syncing
  1039. * and writing the relocation. This value is written back out by
  1040. * the execbuffer ioctl when the relocation is written.
  1041. */
  1042. __u64 presumed_offset;
  1043. /**
  1044. * Target memory domains read by this operation.
  1045. */
  1046. __u32 read_domains;
  1047. /**
  1048. * Target memory domains written by this operation.
  1049. *
  1050. * Note that only one domain may be written by the whole
  1051. * execbuffer operation, so that where there are conflicts,
  1052. * the application will get -EINVAL back.
  1053. */
  1054. __u32 write_domain;
  1055. };
  1056. /** @{
  1057. * Intel memory domains
  1058. *
  1059. * Most of these just align with the various caches in
  1060. * the system and are used to flush and invalidate as
  1061. * objects end up cached in different domains.
  1062. */
  1063. /** CPU cache */
  1064. #define I915_GEM_DOMAIN_CPU 0x00000001
  1065. /** Render cache, used by 2D and 3D drawing */
  1066. #define I915_GEM_DOMAIN_RENDER 0x00000002
  1067. /** Sampler cache, used by texture engine */
  1068. #define I915_GEM_DOMAIN_SAMPLER 0x00000004
  1069. /** Command queue, used to load batch buffers */
  1070. #define I915_GEM_DOMAIN_COMMAND 0x00000008
  1071. /** Instruction cache, used by shader programs */
  1072. #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
  1073. /** Vertex address cache */
  1074. #define I915_GEM_DOMAIN_VERTEX 0x00000020
  1075. /** GTT domain - aperture and scanout */
  1076. #define I915_GEM_DOMAIN_GTT 0x00000040
  1077. /** WC domain - uncached access */
  1078. #define I915_GEM_DOMAIN_WC 0x00000080
  1079. /** @} */
  1080. struct drm_i915_gem_exec_object {
  1081. /**
  1082. * User's handle for a buffer to be bound into the GTT for this
  1083. * operation.
  1084. */
  1085. __u32 handle;
  1086. /** Number of relocations to be performed on this buffer */
  1087. __u32 relocation_count;
  1088. /**
  1089. * Pointer to array of struct drm_i915_gem_relocation_entry containing
  1090. * the relocations to be performed in this buffer.
  1091. */
  1092. __u64 relocs_ptr;
  1093. /** Required alignment in graphics aperture */
  1094. __u64 alignment;
  1095. /**
  1096. * Returned value of the updated offset of the object, for future
  1097. * presumed_offset writes.
  1098. */
  1099. __u64 offset;
  1100. };
  1101. /* DRM_IOCTL_I915_GEM_EXECBUFFER was removed in Linux 5.13 */
  1102. struct drm_i915_gem_execbuffer {
  1103. /**
  1104. * List of buffers to be validated with their relocations to be
  1105. * performend on them.
  1106. *
  1107. * This is a pointer to an array of struct drm_i915_gem_validate_entry.
  1108. *
  1109. * These buffers must be listed in an order such that all relocations
  1110. * a buffer is performing refer to buffers that have already appeared
  1111. * in the validate list.
  1112. */
  1113. __u64 buffers_ptr;
  1114. __u32 buffer_count;
  1115. /** Offset in the batchbuffer to start execution from. */
  1116. __u32 batch_start_offset;
  1117. /** Bytes used in batchbuffer from batch_start_offset */
  1118. __u32 batch_len;
  1119. __u32 DR1;
  1120. __u32 DR4;
  1121. __u32 num_cliprects;
  1122. /** This is a struct drm_clip_rect *cliprects */
  1123. __u64 cliprects_ptr;
  1124. };
  1125. struct drm_i915_gem_exec_object2 {
  1126. /**
  1127. * User's handle for a buffer to be bound into the GTT for this
  1128. * operation.
  1129. */
  1130. __u32 handle;
  1131. /** Number of relocations to be performed on this buffer */
  1132. __u32 relocation_count;
  1133. /**
  1134. * Pointer to array of struct drm_i915_gem_relocation_entry containing
  1135. * the relocations to be performed in this buffer.
  1136. */
  1137. __u64 relocs_ptr;
  1138. /** Required alignment in graphics aperture */
  1139. __u64 alignment;
  1140. /**
  1141. * When the EXEC_OBJECT_PINNED flag is specified this is populated by
  1142. * the user with the GTT offset at which this object will be pinned.
  1143. *
  1144. * When the I915_EXEC_NO_RELOC flag is specified this must contain the
  1145. * presumed_offset of the object.
  1146. *
  1147. * During execbuffer2 the kernel populates it with the value of the
  1148. * current GTT offset of the object, for future presumed_offset writes.
  1149. *
  1150. * See struct drm_i915_gem_create_ext for the rules when dealing with
  1151. * alignment restrictions with I915_MEMORY_CLASS_DEVICE, on devices with
  1152. * minimum page sizes, like DG2.
  1153. */
  1154. __u64 offset;
  1155. #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
  1156. #define EXEC_OBJECT_NEEDS_GTT (1<<1)
  1157. #define EXEC_OBJECT_WRITE (1<<2)
  1158. #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3)
  1159. #define EXEC_OBJECT_PINNED (1<<4)
  1160. #define EXEC_OBJECT_PAD_TO_SIZE (1<<5)
  1161. /* The kernel implicitly tracks GPU activity on all GEM objects, and
  1162. * synchronises operations with outstanding rendering. This includes
  1163. * rendering on other devices if exported via dma-buf. However, sometimes
  1164. * this tracking is too coarse and the user knows better. For example,
  1165. * if the object is split into non-overlapping ranges shared between different
  1166. * clients or engines (i.e. suballocating objects), the implicit tracking
  1167. * by kernel assumes that each operation affects the whole object rather
  1168. * than an individual range, causing needless synchronisation between clients.
  1169. * The kernel will also forgo any CPU cache flushes prior to rendering from
  1170. * the object as the client is expected to be also handling such domain
  1171. * tracking.
  1172. *
  1173. * The kernel maintains the implicit tracking in order to manage resources
  1174. * used by the GPU - this flag only disables the synchronisation prior to
  1175. * rendering with this object in this execbuf.
  1176. *
  1177. * Opting out of implicit synhronisation requires the user to do its own
  1178. * explicit tracking to avoid rendering corruption. See, for example,
  1179. * I915_PARAM_HAS_EXEC_FENCE to order execbufs and execute them asynchronously.
  1180. */
  1181. #define EXEC_OBJECT_ASYNC (1<<6)
  1182. /* Request that the contents of this execobject be copied into the error
  1183. * state upon a GPU hang involving this batch for post-mortem debugging.
  1184. * These buffers are recorded in no particular order as "user" in
  1185. * /sys/class/drm/cardN/error. Query I915_PARAM_HAS_EXEC_CAPTURE to see
  1186. * if the kernel supports this flag.
  1187. */
  1188. #define EXEC_OBJECT_CAPTURE (1<<7)
  1189. /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */
  1190. #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_CAPTURE<<1)
  1191. __u64 flags;
  1192. union {
  1193. __u64 rsvd1;
  1194. __u64 pad_to_size;
  1195. };
  1196. __u64 rsvd2;
  1197. };
  1198. /**
  1199. * struct drm_i915_gem_exec_fence - An input or output fence for the execbuf
  1200. * ioctl.
  1201. *
  1202. * The request will wait for input fence to signal before submission.
  1203. *
  1204. * The returned output fence will be signaled after the completion of the
  1205. * request.
  1206. */
  1207. struct drm_i915_gem_exec_fence {
  1208. /** @handle: User's handle for a drm_syncobj to wait on or signal. */
  1209. __u32 handle;
  1210. /**
  1211. * @flags: Supported flags are:
  1212. *
  1213. * I915_EXEC_FENCE_WAIT:
  1214. * Wait for the input fence before request submission.
  1215. *
  1216. * I915_EXEC_FENCE_SIGNAL:
  1217. * Return request completion fence as output
  1218. */
  1219. __u32 flags;
  1220. #define I915_EXEC_FENCE_WAIT (1<<0)
  1221. #define I915_EXEC_FENCE_SIGNAL (1<<1)
  1222. #define __I915_EXEC_FENCE_UNKNOWN_FLAGS (-(I915_EXEC_FENCE_SIGNAL << 1))
  1223. };
  1224. /**
  1225. * struct drm_i915_gem_execbuffer_ext_timeline_fences - Timeline fences
  1226. * for execbuf ioctl.
  1227. *
  1228. * This structure describes an array of drm_syncobj and associated points for
  1229. * timeline variants of drm_syncobj. It is invalid to append this structure to
  1230. * the execbuf if I915_EXEC_FENCE_ARRAY is set.
  1231. */
  1232. struct drm_i915_gem_execbuffer_ext_timeline_fences {
  1233. #define DRM_I915_GEM_EXECBUFFER_EXT_TIMELINE_FENCES 0
  1234. /** @base: Extension link. See struct i915_user_extension. */
  1235. struct i915_user_extension base;
  1236. /**
  1237. * @fence_count: Number of elements in the @handles_ptr & @value_ptr
  1238. * arrays.
  1239. */
  1240. __u64 fence_count;
  1241. /**
  1242. * @handles_ptr: Pointer to an array of struct drm_i915_gem_exec_fence
  1243. * of length @fence_count.
  1244. */
  1245. __u64 handles_ptr;
  1246. /**
  1247. * @values_ptr: Pointer to an array of u64 values of length
  1248. * @fence_count.
  1249. * Values must be 0 for a binary drm_syncobj. A Value of 0 for a
  1250. * timeline drm_syncobj is invalid as it turns a drm_syncobj into a
  1251. * binary one.
  1252. */
  1253. __u64 values_ptr;
  1254. };
  1255. /**
  1256. * struct drm_i915_gem_execbuffer2 - Structure for DRM_I915_GEM_EXECBUFFER2
  1257. * ioctl.
  1258. */
  1259. struct drm_i915_gem_execbuffer2 {
  1260. /** @buffers_ptr: Pointer to a list of gem_exec_object2 structs */
  1261. __u64 buffers_ptr;
  1262. /** @buffer_count: Number of elements in @buffers_ptr array */
  1263. __u32 buffer_count;
  1264. /**
  1265. * @batch_start_offset: Offset in the batchbuffer to start execution
  1266. * from.
  1267. */
  1268. __u32 batch_start_offset;
  1269. /**
  1270. * @batch_len: Length in bytes of the batch buffer, starting from the
  1271. * @batch_start_offset. If 0, length is assumed to be the batch buffer
  1272. * object size.
  1273. */
  1274. __u32 batch_len;
  1275. /** @DR1: deprecated */
  1276. __u32 DR1;
  1277. /** @DR4: deprecated */
  1278. __u32 DR4;
  1279. /** @num_cliprects: See @cliprects_ptr */
  1280. __u32 num_cliprects;
  1281. /**
  1282. * @cliprects_ptr: Kernel clipping was a DRI1 misfeature.
  1283. *
  1284. * It is invalid to use this field if I915_EXEC_FENCE_ARRAY or
  1285. * I915_EXEC_USE_EXTENSIONS flags are not set.
  1286. *
  1287. * If I915_EXEC_FENCE_ARRAY is set, then this is a pointer to an array
  1288. * of &drm_i915_gem_exec_fence and @num_cliprects is the length of the
  1289. * array.
  1290. *
  1291. * If I915_EXEC_USE_EXTENSIONS is set, then this is a pointer to a
  1292. * single &i915_user_extension and num_cliprects is 0.
  1293. */
  1294. __u64 cliprects_ptr;
  1295. /** @flags: Execbuf flags */
  1296. __u64 flags;
  1297. #define I915_EXEC_RING_MASK (0x3f)
  1298. #define I915_EXEC_DEFAULT (0<<0)
  1299. #define I915_EXEC_RENDER (1<<0)
  1300. #define I915_EXEC_BSD (2<<0)
  1301. #define I915_EXEC_BLT (3<<0)
  1302. #define I915_EXEC_VEBOX (4<<0)
  1303. /* Used for switching the constants addressing mode on gen4+ RENDER ring.
  1304. * Gen6+ only supports relative addressing to dynamic state (default) and
  1305. * absolute addressing.
  1306. *
  1307. * These flags are ignored for the BSD and BLT rings.
  1308. */
  1309. #define I915_EXEC_CONSTANTS_MASK (3<<6)
  1310. #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
  1311. #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
  1312. #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
  1313. /** Resets the SO write offset registers for transform feedback on gen7. */
  1314. #define I915_EXEC_GEN7_SOL_RESET (1<<8)
  1315. /** Request a privileged ("secure") batch buffer. Note only available for
  1316. * DRM_ROOT_ONLY | DRM_MASTER processes.
  1317. */
  1318. #define I915_EXEC_SECURE (1<<9)
  1319. /** Inform the kernel that the batch is and will always be pinned. This
  1320. * negates the requirement for a workaround to be performed to avoid
  1321. * an incoherent CS (such as can be found on 830/845). If this flag is
  1322. * not passed, the kernel will endeavour to make sure the batch is
  1323. * coherent with the CS before execution. If this flag is passed,
  1324. * userspace assumes the responsibility for ensuring the same.
  1325. */
  1326. #define I915_EXEC_IS_PINNED (1<<10)
  1327. /** Provide a hint to the kernel that the command stream and auxiliary
  1328. * state buffers already holds the correct presumed addresses and so the
  1329. * relocation process may be skipped if no buffers need to be moved in
  1330. * preparation for the execbuffer.
  1331. */
  1332. #define I915_EXEC_NO_RELOC (1<<11)
  1333. /** Use the reloc.handle as an index into the exec object array rather
  1334. * than as the per-file handle.
  1335. */
  1336. #define I915_EXEC_HANDLE_LUT (1<<12)
  1337. /** Used for switching BSD rings on the platforms with two BSD rings */
  1338. #define I915_EXEC_BSD_SHIFT (13)
  1339. #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT)
  1340. /* default ping-pong mode */
  1341. #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT)
  1342. #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT)
  1343. #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT)
  1344. /** Tell the kernel that the batchbuffer is processed by
  1345. * the resource streamer.
  1346. */
  1347. #define I915_EXEC_RESOURCE_STREAMER (1<<15)
  1348. /* Setting I915_EXEC_FENCE_IN implies that lower_32_bits(rsvd2) represent
  1349. * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
  1350. * the batch.
  1351. *
  1352. * Returns -EINVAL if the sync_file fd cannot be found.
  1353. */
  1354. #define I915_EXEC_FENCE_IN (1<<16)
  1355. /* Setting I915_EXEC_FENCE_OUT causes the ioctl to return a sync_file fd
  1356. * in the upper_32_bits(rsvd2) upon success. Ownership of the fd is given
  1357. * to the caller, and it should be close() after use. (The fd is a regular
  1358. * file descriptor and will be cleaned up on process termination. It holds
  1359. * a reference to the request, but nothing else.)
  1360. *
  1361. * The sync_file fd can be combined with other sync_file and passed either
  1362. * to execbuf using I915_EXEC_FENCE_IN, to atomic KMS ioctls (so that a flip
  1363. * will only occur after this request completes), or to other devices.
  1364. *
  1365. * Using I915_EXEC_FENCE_OUT requires use of
  1366. * DRM_IOCTL_I915_GEM_EXECBUFFER2_WR ioctl so that the result is written
  1367. * back to userspace. Failure to do so will cause the out-fence to always
  1368. * be reported as zero, and the real fence fd to be leaked.
  1369. */
  1370. #define I915_EXEC_FENCE_OUT (1<<17)
  1371. /*
  1372. * Traditionally the execbuf ioctl has only considered the final element in
  1373. * the execobject[] to be the executable batch. Often though, the client
  1374. * will known the batch object prior to construction and being able to place
  1375. * it into the execobject[] array first can simplify the relocation tracking.
  1376. * Setting I915_EXEC_BATCH_FIRST tells execbuf to use element 0 of the
  1377. * execobject[] as the * batch instead (the default is to use the last
  1378. * element).
  1379. */
  1380. #define I915_EXEC_BATCH_FIRST (1<<18)
  1381. /* Setting I915_FENCE_ARRAY implies that num_cliprects and cliprects_ptr
  1382. * define an array of i915_gem_exec_fence structures which specify a set of
  1383. * dma fences to wait upon or signal.
  1384. */
  1385. #define I915_EXEC_FENCE_ARRAY (1<<19)
  1386. /*
  1387. * Setting I915_EXEC_FENCE_SUBMIT implies that lower_32_bits(rsvd2) represent
  1388. * a sync_file fd to wait upon (in a nonblocking manner) prior to executing
  1389. * the batch.
  1390. *
  1391. * Returns -EINVAL if the sync_file fd cannot be found.
  1392. */
  1393. #define I915_EXEC_FENCE_SUBMIT (1 << 20)
  1394. /*
  1395. * Setting I915_EXEC_USE_EXTENSIONS implies that
  1396. * drm_i915_gem_execbuffer2.cliprects_ptr is treated as a pointer to an linked
  1397. * list of i915_user_extension. Each i915_user_extension node is the base of a
  1398. * larger structure. The list of supported structures are listed in the
  1399. * drm_i915_gem_execbuffer_ext enum.
  1400. */
  1401. #define I915_EXEC_USE_EXTENSIONS (1 << 21)
  1402. #define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_USE_EXTENSIONS << 1))
  1403. /** @rsvd1: Context id */
  1404. __u64 rsvd1;
  1405. /**
  1406. * @rsvd2: in and out sync_file file descriptors.
  1407. *
  1408. * When I915_EXEC_FENCE_IN or I915_EXEC_FENCE_SUBMIT flag is set, the
  1409. * lower 32 bits of this field will have the in sync_file fd (input).
  1410. *
  1411. * When I915_EXEC_FENCE_OUT flag is set, the upper 32 bits of this
  1412. * field will have the out sync_file fd (output).
  1413. */
  1414. __u64 rsvd2;
  1415. };
  1416. #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
  1417. #define i915_execbuffer2_set_context_id(eb2, context) \
  1418. (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK
  1419. #define i915_execbuffer2_get_context_id(eb2) \
  1420. ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK)
  1421. struct drm_i915_gem_pin {
  1422. /** Handle of the buffer to be pinned. */
  1423. __u32 handle;
  1424. __u32 pad;
  1425. /** alignment required within the aperture */
  1426. __u64 alignment;
  1427. /** Returned GTT offset of the buffer. */
  1428. __u64 offset;
  1429. };
  1430. struct drm_i915_gem_unpin {
  1431. /** Handle of the buffer to be unpinned. */
  1432. __u32 handle;
  1433. __u32 pad;
  1434. };
  1435. struct drm_i915_gem_busy {
  1436. /** Handle of the buffer to check for busy */
  1437. __u32 handle;
  1438. /** Return busy status
  1439. *
  1440. * A return of 0 implies that the object is idle (after
  1441. * having flushed any pending activity), and a non-zero return that
  1442. * the object is still in-flight on the GPU. (The GPU has not yet
  1443. * signaled completion for all pending requests that reference the
  1444. * object.) An object is guaranteed to become idle eventually (so
  1445. * long as no new GPU commands are executed upon it). Due to the
  1446. * asynchronous nature of the hardware, an object reported
  1447. * as busy may become idle before the ioctl is completed.
  1448. *
  1449. * Furthermore, if the object is busy, which engine is busy is only
  1450. * provided as a guide and only indirectly by reporting its class
  1451. * (there may be more than one engine in each class). There are race
  1452. * conditions which prevent the report of which engines are busy from
  1453. * being always accurate. However, the converse is not true. If the
  1454. * object is idle, the result of the ioctl, that all engines are idle,
  1455. * is accurate.
  1456. *
  1457. * The returned dword is split into two fields to indicate both
  1458. * the engine classes on which the object is being read, and the
  1459. * engine class on which it is currently being written (if any).
  1460. *
  1461. * The low word (bits 0:15) indicate if the object is being written
  1462. * to by any engine (there can only be one, as the GEM implicit
  1463. * synchronisation rules force writes to be serialised). Only the
  1464. * engine class (offset by 1, I915_ENGINE_CLASS_RENDER is reported as
  1465. * 1 not 0 etc) for the last write is reported.
  1466. *
  1467. * The high word (bits 16:31) are a bitmask of which engines classes
  1468. * are currently reading from the object. Multiple engines may be
  1469. * reading from the object simultaneously.
  1470. *
  1471. * The value of each engine class is the same as specified in the
  1472. * I915_CONTEXT_PARAM_ENGINES context parameter and via perf, i.e.
  1473. * I915_ENGINE_CLASS_RENDER, I915_ENGINE_CLASS_COPY, etc.
  1474. * Some hardware may have parallel execution engines, e.g. multiple
  1475. * media engines, which are mapped to the same class identifier and so
  1476. * are not separately reported for busyness.
  1477. *
  1478. * Caveat emptor:
  1479. * Only the boolean result of this query is reliable; that is whether
  1480. * the object is idle or busy. The report of which engines are busy
  1481. * should be only used as a heuristic.
  1482. */
  1483. __u32 busy;
  1484. };
  1485. /**
  1486. * struct drm_i915_gem_caching - Set or get the caching for given object
  1487. * handle.
  1488. *
  1489. * Allow userspace to control the GTT caching bits for a given object when the
  1490. * object is later mapped through the ppGTT(or GGTT on older platforms lacking
  1491. * ppGTT support, or if the object is used for scanout). Note that this might
  1492. * require unbinding the object from the GTT first, if its current caching value
  1493. * doesn't match.
  1494. *
  1495. * Note that this all changes on discrete platforms, starting from DG1, the
  1496. * set/get caching is no longer supported, and is now rejected. Instead the CPU
  1497. * caching attributes(WB vs WC) will become an immutable creation time property
  1498. * for the object, along with the GTT caching level. For now we don't expose any
  1499. * new uAPI for this, instead on DG1 this is all implicit, although this largely
  1500. * shouldn't matter since DG1 is coherent by default(without any way of
  1501. * controlling it).
  1502. *
  1503. * Implicit caching rules, starting from DG1:
  1504. *
  1505. * - If any of the object placements (see &drm_i915_gem_create_ext_memory_regions)
  1506. * contain I915_MEMORY_CLASS_DEVICE then the object will be allocated and
  1507. * mapped as write-combined only.
  1508. *
  1509. * - Everything else is always allocated and mapped as write-back, with the
  1510. * guarantee that everything is also coherent with the GPU.
  1511. *
  1512. * Note that this is likely to change in the future again, where we might need
  1513. * more flexibility on future devices, so making this all explicit as part of a
  1514. * new &drm_i915_gem_create_ext extension is probable.
  1515. *
  1516. * Side note: Part of the reason for this is that changing the at-allocation-time CPU
  1517. * caching attributes for the pages might be required(and is expensive) if we
  1518. * need to then CPU map the pages later with different caching attributes. This
  1519. * inconsistent caching behaviour, while supported on x86, is not universally
  1520. * supported on other architectures. So for simplicity we opt for setting
  1521. * everything at creation time, whilst also making it immutable, on discrete
  1522. * platforms.
  1523. */
  1524. struct drm_i915_gem_caching {
  1525. /**
  1526. * @handle: Handle of the buffer to set/get the caching level.
  1527. */
  1528. __u32 handle;
  1529. /**
  1530. * @caching: The GTT caching level to apply or possible return value.
  1531. *
  1532. * The supported @caching values:
  1533. *
  1534. * I915_CACHING_NONE:
  1535. *
  1536. * GPU access is not coherent with CPU caches. Default for machines
  1537. * without an LLC. This means manual flushing might be needed, if we
  1538. * want GPU access to be coherent.
  1539. *
  1540. * I915_CACHING_CACHED:
  1541. *
  1542. * GPU access is coherent with CPU caches and furthermore the data is
  1543. * cached in last-level caches shared between CPU cores and the GPU GT.
  1544. *
  1545. * I915_CACHING_DISPLAY:
  1546. *
  1547. * Special GPU caching mode which is coherent with the scanout engines.
  1548. * Transparently falls back to I915_CACHING_NONE on platforms where no
  1549. * special cache mode (like write-through or gfdt flushing) is
  1550. * available. The kernel automatically sets this mode when using a
  1551. * buffer as a scanout target. Userspace can manually set this mode to
  1552. * avoid a costly stall and clflush in the hotpath of drawing the first
  1553. * frame.
  1554. */
  1555. #define I915_CACHING_NONE 0
  1556. #define I915_CACHING_CACHED 1
  1557. #define I915_CACHING_DISPLAY 2
  1558. __u32 caching;
  1559. };
  1560. #define I915_TILING_NONE 0
  1561. #define I915_TILING_X 1
  1562. #define I915_TILING_Y 2
  1563. /*
  1564. * Do not add new tiling types here. The I915_TILING_* values are for
  1565. * de-tiling fence registers that no longer exist on modern platforms. Although
  1566. * the hardware may support new types of tiling in general (e.g., Tile4), we
  1567. * do not need to add them to the uapi that is specific to now-defunct ioctls.
  1568. */
  1569. #define I915_TILING_LAST I915_TILING_Y
  1570. #define I915_BIT_6_SWIZZLE_NONE 0
  1571. #define I915_BIT_6_SWIZZLE_9 1
  1572. #define I915_BIT_6_SWIZZLE_9_10 2
  1573. #define I915_BIT_6_SWIZZLE_9_11 3
  1574. #define I915_BIT_6_SWIZZLE_9_10_11 4
  1575. /* Not seen by userland */
  1576. #define I915_BIT_6_SWIZZLE_UNKNOWN 5
  1577. /* Seen by userland. */
  1578. #define I915_BIT_6_SWIZZLE_9_17 6
  1579. #define I915_BIT_6_SWIZZLE_9_10_17 7
  1580. struct drm_i915_gem_set_tiling {
  1581. /** Handle of the buffer to have its tiling state updated */
  1582. __u32 handle;
  1583. /**
  1584. * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
  1585. * I915_TILING_Y).
  1586. *
  1587. * This value is to be set on request, and will be updated by the
  1588. * kernel on successful return with the actual chosen tiling layout.
  1589. *
  1590. * The tiling mode may be demoted to I915_TILING_NONE when the system
  1591. * has bit 6 swizzling that can't be managed correctly by GEM.
  1592. *
  1593. * Buffer contents become undefined when changing tiling_mode.
  1594. */
  1595. __u32 tiling_mode;
  1596. /**
  1597. * Stride in bytes for the object when in I915_TILING_X or
  1598. * I915_TILING_Y.
  1599. */
  1600. __u32 stride;
  1601. /**
  1602. * Returned address bit 6 swizzling required for CPU access through
  1603. * mmap mapping.
  1604. */
  1605. __u32 swizzle_mode;
  1606. };
  1607. struct drm_i915_gem_get_tiling {
  1608. /** Handle of the buffer to get tiling state for. */
  1609. __u32 handle;
  1610. /**
  1611. * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
  1612. * I915_TILING_Y).
  1613. */
  1614. __u32 tiling_mode;
  1615. /**
  1616. * Returned address bit 6 swizzling required for CPU access through
  1617. * mmap mapping.
  1618. */
  1619. __u32 swizzle_mode;
  1620. /**
  1621. * Returned address bit 6 swizzling required for CPU access through
  1622. * mmap mapping whilst bound.
  1623. */
  1624. __u32 phys_swizzle_mode;
  1625. };
  1626. struct drm_i915_gem_get_aperture {
  1627. /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
  1628. __u64 aper_size;
  1629. /**
  1630. * Available space in the aperture used by i915_gem_execbuffer, in
  1631. * bytes
  1632. */
  1633. __u64 aper_available_size;
  1634. };
  1635. struct drm_i915_get_pipe_from_crtc_id {
  1636. /** ID of CRTC being requested **/
  1637. __u32 crtc_id;
  1638. /** pipe of requested CRTC **/
  1639. __u32 pipe;
  1640. };
  1641. #define I915_MADV_WILLNEED 0
  1642. #define I915_MADV_DONTNEED 1
  1643. #define __I915_MADV_PURGED 2 /* internal state */
  1644. struct drm_i915_gem_madvise {
  1645. /** Handle of the buffer to change the backing store advice */
  1646. __u32 handle;
  1647. /* Advice: either the buffer will be needed again in the near future,
  1648. * or won't be and could be discarded under memory pressure.
  1649. */
  1650. __u32 madv;
  1651. /** Whether the backing store still exists. */
  1652. __u32 retained;
  1653. };
  1654. /* flags */
  1655. #define I915_OVERLAY_TYPE_MASK 0xff
  1656. #define I915_OVERLAY_YUV_PLANAR 0x01
  1657. #define I915_OVERLAY_YUV_PACKED 0x02
  1658. #define I915_OVERLAY_RGB 0x03
  1659. #define I915_OVERLAY_DEPTH_MASK 0xff00
  1660. #define I915_OVERLAY_RGB24 0x1000
  1661. #define I915_OVERLAY_RGB16 0x2000
  1662. #define I915_OVERLAY_RGB15 0x3000
  1663. #define I915_OVERLAY_YUV422 0x0100
  1664. #define I915_OVERLAY_YUV411 0x0200
  1665. #define I915_OVERLAY_YUV420 0x0300
  1666. #define I915_OVERLAY_YUV410 0x0400
  1667. #define I915_OVERLAY_SWAP_MASK 0xff0000
  1668. #define I915_OVERLAY_NO_SWAP 0x000000
  1669. #define I915_OVERLAY_UV_SWAP 0x010000
  1670. #define I915_OVERLAY_Y_SWAP 0x020000
  1671. #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
  1672. #define I915_OVERLAY_FLAGS_MASK 0xff000000
  1673. #define I915_OVERLAY_ENABLE 0x01000000
  1674. struct drm_intel_overlay_put_image {
  1675. /* various flags and src format description */
  1676. __u32 flags;
  1677. /* source picture description */
  1678. __u32 bo_handle;
  1679. /* stride values and offsets are in bytes, buffer relative */
  1680. __u16 stride_Y; /* stride for packed formats */
  1681. __u16 stride_UV;
  1682. __u32 offset_Y; /* offset for packet formats */
  1683. __u32 offset_U;
  1684. __u32 offset_V;
  1685. /* in pixels */
  1686. __u16 src_width;
  1687. __u16 src_height;
  1688. /* to compensate the scaling factors for partially covered surfaces */
  1689. __u16 src_scan_width;
  1690. __u16 src_scan_height;
  1691. /* output crtc description */
  1692. __u32 crtc_id;
  1693. __u16 dst_x;
  1694. __u16 dst_y;
  1695. __u16 dst_width;
  1696. __u16 dst_height;
  1697. };
  1698. /* flags */
  1699. #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
  1700. #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
  1701. #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2)
  1702. struct drm_intel_overlay_attrs {
  1703. __u32 flags;
  1704. __u32 color_key;
  1705. __s32 brightness;
  1706. __u32 contrast;
  1707. __u32 saturation;
  1708. __u32 gamma0;
  1709. __u32 gamma1;
  1710. __u32 gamma2;
  1711. __u32 gamma3;
  1712. __u32 gamma4;
  1713. __u32 gamma5;
  1714. };
  1715. /*
  1716. * Intel sprite handling
  1717. *
  1718. * Color keying works with a min/mask/max tuple. Both source and destination
  1719. * color keying is allowed.
  1720. *
  1721. * Source keying:
  1722. * Sprite pixels within the min & max values, masked against the color channels
  1723. * specified in the mask field, will be transparent. All other pixels will
  1724. * be displayed on top of the primary plane. For RGB surfaces, only the min
  1725. * and mask fields will be used; ranged compares are not allowed.
  1726. *
  1727. * Destination keying:
  1728. * Primary plane pixels that match the min value, masked against the color
  1729. * channels specified in the mask field, will be replaced by corresponding
  1730. * pixels from the sprite plane.
  1731. *
  1732. * Note that source & destination keying are exclusive; only one can be
  1733. * active on a given plane.
  1734. */
  1735. #define I915_SET_COLORKEY_NONE (1<<0) /* Deprecated. Instead set
  1736. * flags==0 to disable colorkeying.
  1737. */
  1738. #define I915_SET_COLORKEY_DESTINATION (1<<1)
  1739. #define I915_SET_COLORKEY_SOURCE (1<<2)
  1740. struct drm_intel_sprite_colorkey {
  1741. __u32 plane_id;
  1742. __u32 min_value;
  1743. __u32 channel_mask;
  1744. __u32 max_value;
  1745. __u32 flags;
  1746. };
  1747. struct drm_i915_gem_wait {
  1748. /** Handle of BO we shall wait on */
  1749. __u32 bo_handle;
  1750. __u32 flags;
  1751. /** Number of nanoseconds to wait, Returns time remaining. */
  1752. __s64 timeout_ns;
  1753. };
  1754. struct drm_i915_gem_context_create {
  1755. __u32 ctx_id; /* output: id of new context*/
  1756. __u32 pad;
  1757. };
  1758. /**
  1759. * struct drm_i915_gem_context_create_ext - Structure for creating contexts.
  1760. */
  1761. struct drm_i915_gem_context_create_ext {
  1762. /** @ctx_id: Id of the created context (output) */
  1763. __u32 ctx_id;
  1764. /**
  1765. * @flags: Supported flags are:
  1766. *
  1767. * I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS:
  1768. *
  1769. * Extensions may be appended to this structure and driver must check
  1770. * for those. See @extensions.
  1771. *
  1772. * I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE
  1773. *
  1774. * Created context will have single timeline.
  1775. */
  1776. __u32 flags;
  1777. #define I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS (1u << 0)
  1778. #define I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE (1u << 1)
  1779. #define I915_CONTEXT_CREATE_FLAGS_UNKNOWN \
  1780. (-(I915_CONTEXT_CREATE_FLAGS_SINGLE_TIMELINE << 1))
  1781. /**
  1782. * @extensions: Zero-terminated chain of extensions.
  1783. *
  1784. * I915_CONTEXT_CREATE_EXT_SETPARAM:
  1785. * Context parameter to set or query during context creation.
  1786. * See struct drm_i915_gem_context_create_ext_setparam.
  1787. *
  1788. * I915_CONTEXT_CREATE_EXT_CLONE:
  1789. * This extension has been removed. On the off chance someone somewhere
  1790. * has attempted to use it, never re-use this extension number.
  1791. */
  1792. __u64 extensions;
  1793. #define I915_CONTEXT_CREATE_EXT_SETPARAM 0
  1794. #define I915_CONTEXT_CREATE_EXT_CLONE 1
  1795. };
  1796. /**
  1797. * struct drm_i915_gem_context_param - Context parameter to set or query.
  1798. */
  1799. struct drm_i915_gem_context_param {
  1800. /** @ctx_id: Context id */
  1801. __u32 ctx_id;
  1802. /** @size: Size of the parameter @value */
  1803. __u32 size;
  1804. /** @param: Parameter to set or query */
  1805. __u64 param;
  1806. #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
  1807. /* I915_CONTEXT_PARAM_NO_ZEROMAP has been removed. On the off chance
  1808. * someone somewhere has attempted to use it, never re-use this context
  1809. * param number.
  1810. */
  1811. #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2
  1812. #define I915_CONTEXT_PARAM_GTT_SIZE 0x3
  1813. #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4
  1814. #define I915_CONTEXT_PARAM_BANNABLE 0x5
  1815. #define I915_CONTEXT_PARAM_PRIORITY 0x6
  1816. #define I915_CONTEXT_MAX_USER_PRIORITY 1023 /* inclusive */
  1817. #define I915_CONTEXT_DEFAULT_PRIORITY 0
  1818. #define I915_CONTEXT_MIN_USER_PRIORITY -1023 /* inclusive */
  1819. /*
  1820. * When using the following param, value should be a pointer to
  1821. * drm_i915_gem_context_param_sseu.
  1822. */
  1823. #define I915_CONTEXT_PARAM_SSEU 0x7
  1824. /*
  1825. * Not all clients may want to attempt automatic recover of a context after
  1826. * a hang (for example, some clients may only submit very small incremental
  1827. * batches relying on known logical state of previous batches which will never
  1828. * recover correctly and each attempt will hang), and so would prefer that
  1829. * the context is forever banned instead.
  1830. *
  1831. * If set to false (0), after a reset, subsequent (and in flight) rendering
  1832. * from this context is discarded, and the client will need to create a new
  1833. * context to use instead.
  1834. *
  1835. * If set to true (1), the kernel will automatically attempt to recover the
  1836. * context by skipping the hanging batch and executing the next batch starting
  1837. * from the default context state (discarding the incomplete logical context
  1838. * state lost due to the reset).
  1839. *
  1840. * On creation, all new contexts are marked as recoverable.
  1841. */
  1842. #define I915_CONTEXT_PARAM_RECOVERABLE 0x8
  1843. /*
  1844. * The id of the associated virtual memory address space (ppGTT) of
  1845. * this context. Can be retrieved and passed to another context
  1846. * (on the same fd) for both to use the same ppGTT and so share
  1847. * address layouts, and avoid reloading the page tables on context
  1848. * switches between themselves.
  1849. *
  1850. * See DRM_I915_GEM_VM_CREATE and DRM_I915_GEM_VM_DESTROY.
  1851. */
  1852. #define I915_CONTEXT_PARAM_VM 0x9
  1853. /*
  1854. * I915_CONTEXT_PARAM_ENGINES:
  1855. *
  1856. * Bind this context to operate on this subset of available engines. Henceforth,
  1857. * the I915_EXEC_RING selector for DRM_IOCTL_I915_GEM_EXECBUFFER2 operates as
  1858. * an index into this array of engines; I915_EXEC_DEFAULT selecting engine[0]
  1859. * and upwards. Slots 0...N are filled in using the specified (class, instance).
  1860. * Use
  1861. * engine_class: I915_ENGINE_CLASS_INVALID,
  1862. * engine_instance: I915_ENGINE_CLASS_INVALID_NONE
  1863. * to specify a gap in the array that can be filled in later, e.g. by a
  1864. * virtual engine used for load balancing.
  1865. *
  1866. * Setting the number of engines bound to the context to 0, by passing a zero
  1867. * sized argument, will revert back to default settings.
  1868. *
  1869. * See struct i915_context_param_engines.
  1870. *
  1871. * Extensions:
  1872. * i915_context_engines_load_balance (I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE)
  1873. * i915_context_engines_bond (I915_CONTEXT_ENGINES_EXT_BOND)
  1874. * i915_context_engines_parallel_submit (I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT)
  1875. */
  1876. #define I915_CONTEXT_PARAM_ENGINES 0xa
  1877. /*
  1878. * I915_CONTEXT_PARAM_PERSISTENCE:
  1879. *
  1880. * Allow the context and active rendering to survive the process until
  1881. * completion. Persistence allows fire-and-forget clients to queue up a
  1882. * bunch of work, hand the output over to a display server and then quit.
  1883. * If the context is marked as not persistent, upon closing (either via
  1884. * an explicit DRM_I915_GEM_CONTEXT_DESTROY or implicitly from file closure
  1885. * or process termination), the context and any outstanding requests will be
  1886. * cancelled (and exported fences for cancelled requests marked as -EIO).
  1887. *
  1888. * By default, new contexts allow persistence.
  1889. */
  1890. #define I915_CONTEXT_PARAM_PERSISTENCE 0xb
  1891. /* This API has been removed. On the off chance someone somewhere has
  1892. * attempted to use it, never re-use this context param number.
  1893. */
  1894. #define I915_CONTEXT_PARAM_RINGSIZE 0xc
  1895. /*
  1896. * I915_CONTEXT_PARAM_PROTECTED_CONTENT:
  1897. *
  1898. * Mark that the context makes use of protected content, which will result
  1899. * in the context being invalidated when the protected content session is.
  1900. * Given that the protected content session is killed on suspend, the device
  1901. * is kept awake for the lifetime of a protected context, so the user should
  1902. * make sure to dispose of them once done.
  1903. * This flag can only be set at context creation time and, when set to true,
  1904. * must be preceded by an explicit setting of I915_CONTEXT_PARAM_RECOVERABLE
  1905. * to false. This flag can't be set to true in conjunction with setting the
  1906. * I915_CONTEXT_PARAM_BANNABLE flag to false. Creation example:
  1907. *
  1908. * .. code-block:: C
  1909. *
  1910. * struct drm_i915_gem_context_create_ext_setparam p_protected = {
  1911. * .base = {
  1912. * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
  1913. * },
  1914. * .param = {
  1915. * .param = I915_CONTEXT_PARAM_PROTECTED_CONTENT,
  1916. * .value = 1,
  1917. * }
  1918. * };
  1919. * struct drm_i915_gem_context_create_ext_setparam p_norecover = {
  1920. * .base = {
  1921. * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
  1922. * .next_extension = to_user_pointer(&p_protected),
  1923. * },
  1924. * .param = {
  1925. * .param = I915_CONTEXT_PARAM_RECOVERABLE,
  1926. * .value = 0,
  1927. * }
  1928. * };
  1929. * struct drm_i915_gem_context_create_ext create = {
  1930. * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
  1931. * .extensions = to_user_pointer(&p_norecover);
  1932. * };
  1933. *
  1934. * ctx_id = gem_context_create_ext(drm_fd, &create);
  1935. *
  1936. * In addition to the normal failure cases, setting this flag during context
  1937. * creation can result in the following errors:
  1938. *
  1939. * -ENODEV: feature not available
  1940. * -EPERM: trying to mark a recoverable or not bannable context as protected
  1941. * -ENXIO: A dependency such as a component driver or firmware is not yet
  1942. * loaded so user space may need to attempt again. Depending on the
  1943. * device, this error may be reported if protected context creation is
  1944. * attempted very early after kernel start because the internal timeout
  1945. * waiting for such dependencies is not guaranteed to be larger than
  1946. * required (numbers differ depending on system and kernel config):
  1947. * - ADL/RPL: dependencies may take up to 3 seconds from kernel start
  1948. * while context creation internal timeout is 250 milisecs
  1949. * - MTL: dependencies may take up to 8 seconds from kernel start
  1950. * while context creation internal timeout is 250 milisecs
  1951. * NOTE: such dependencies happen once, so a subsequent call to create a
  1952. * protected context after a prior successful call will not experience
  1953. * such timeouts and will not return -ENXIO (unless the driver is reloaded,
  1954. * or, depending on the device, resumes from a suspended state).
  1955. * -EIO: The firmware did not succeed in creating the protected context.
  1956. */
  1957. #define I915_CONTEXT_PARAM_PROTECTED_CONTENT 0xd
  1958. /*
  1959. * I915_CONTEXT_PARAM_LOW_LATENCY:
  1960. *
  1961. * Mark this context as a low latency workload which requires aggressive GT
  1962. * frequency scaling. Use I915_PARAM_HAS_CONTEXT_FREQ_HINT to check if the kernel
  1963. * supports this per context flag.
  1964. */
  1965. #define I915_CONTEXT_PARAM_LOW_LATENCY 0xe
  1966. /*
  1967. * I915_CONTEXT_PARAM_CONTEXT_IMAGE:
  1968. *
  1969. * Allows userspace to provide own context images.
  1970. *
  1971. * Note that this is a debug API not available on production kernel builds.
  1972. */
  1973. #define I915_CONTEXT_PARAM_CONTEXT_IMAGE 0xf
  1974. /* Must be kept compact -- no holes and well documented */
  1975. /** @value: Context parameter value to be set or queried */
  1976. __u64 value;
  1977. };
  1978. /*
  1979. * Context SSEU programming
  1980. *
  1981. * It may be necessary for either functional or performance reason to configure
  1982. * a context to run with a reduced number of SSEU (where SSEU stands for Slice/
  1983. * Sub-slice/EU).
  1984. *
  1985. * This is done by configuring SSEU configuration using the below
  1986. * @struct drm_i915_gem_context_param_sseu for every supported engine which
  1987. * userspace intends to use.
  1988. *
  1989. * Not all GPUs or engines support this functionality in which case an error
  1990. * code -ENODEV will be returned.
  1991. *
  1992. * Also, flexibility of possible SSEU configuration permutations varies between
  1993. * GPU generations and software imposed limitations. Requesting such a
  1994. * combination will return an error code of -EINVAL.
  1995. *
  1996. * NOTE: When perf/OA is active the context's SSEU configuration is ignored in
  1997. * favour of a single global setting.
  1998. */
  1999. struct drm_i915_gem_context_param_sseu {
  2000. /*
  2001. * Engine class & instance to be configured or queried.
  2002. */
  2003. struct i915_engine_class_instance engine;
  2004. /*
  2005. * Unknown flags must be cleared to zero.
  2006. */
  2007. __u32 flags;
  2008. #define I915_CONTEXT_SSEU_FLAG_ENGINE_INDEX (1u << 0)
  2009. /*
  2010. * Mask of slices to enable for the context. Valid values are a subset
  2011. * of the bitmask value returned for I915_PARAM_SLICE_MASK.
  2012. */
  2013. __u64 slice_mask;
  2014. /*
  2015. * Mask of subslices to enable for the context. Valid values are a
  2016. * subset of the bitmask value return by I915_PARAM_SUBSLICE_MASK.
  2017. */
  2018. __u64 subslice_mask;
  2019. /*
  2020. * Minimum/Maximum number of EUs to enable per subslice for the
  2021. * context. min_eus_per_subslice must be inferior or equal to
  2022. * max_eus_per_subslice.
  2023. */
  2024. __u16 min_eus_per_subslice;
  2025. __u16 max_eus_per_subslice;
  2026. /*
  2027. * Unused for now. Must be cleared to zero.
  2028. */
  2029. __u32 rsvd;
  2030. };
  2031. /**
  2032. * DOC: Virtual Engine uAPI
  2033. *
  2034. * Virtual engine is a concept where userspace is able to configure a set of
  2035. * physical engines, submit a batch buffer, and let the driver execute it on any
  2036. * engine from the set as it sees fit.
  2037. *
  2038. * This is primarily useful on parts which have multiple instances of a same
  2039. * class engine, like for example GT3+ Skylake parts with their two VCS engines.
  2040. *
  2041. * For instance userspace can enumerate all engines of a certain class using the
  2042. * previously described `Engine Discovery uAPI`_. After that userspace can
  2043. * create a GEM context with a placeholder slot for the virtual engine (using
  2044. * `I915_ENGINE_CLASS_INVALID` and `I915_ENGINE_CLASS_INVALID_NONE` for class
  2045. * and instance respectively) and finally using the
  2046. * `I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE` extension place a virtual engine in
  2047. * the same reserved slot.
  2048. *
  2049. * Example of creating a virtual engine and submitting a batch buffer to it:
  2050. *
  2051. * .. code-block:: C
  2052. *
  2053. * I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(virtual, 2) = {
  2054. * .base.name = I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE,
  2055. * .engine_index = 0, // Place this virtual engine into engine map slot 0
  2056. * .num_siblings = 2,
  2057. * .engines = { { I915_ENGINE_CLASS_VIDEO, 0 },
  2058. * { I915_ENGINE_CLASS_VIDEO, 1 }, },
  2059. * };
  2060. * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 1) = {
  2061. * .engines = { { I915_ENGINE_CLASS_INVALID,
  2062. * I915_ENGINE_CLASS_INVALID_NONE } },
  2063. * .extensions = to_user_pointer(&virtual), // Chains after load_balance extension
  2064. * };
  2065. * struct drm_i915_gem_context_create_ext_setparam p_engines = {
  2066. * .base = {
  2067. * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
  2068. * },
  2069. * .param = {
  2070. * .param = I915_CONTEXT_PARAM_ENGINES,
  2071. * .value = to_user_pointer(&engines),
  2072. * .size = sizeof(engines),
  2073. * },
  2074. * };
  2075. * struct drm_i915_gem_context_create_ext create = {
  2076. * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
  2077. * .extensions = to_user_pointer(&p_engines);
  2078. * };
  2079. *
  2080. * ctx_id = gem_context_create_ext(drm_fd, &create);
  2081. *
  2082. * // Now we have created a GEM context with its engine map containing a
  2083. * // single virtual engine. Submissions to this slot can go either to
  2084. * // vcs0 or vcs1, depending on the load balancing algorithm used inside
  2085. * // the driver. The load balancing is dynamic from one batch buffer to
  2086. * // another and transparent to userspace.
  2087. *
  2088. * ...
  2089. * execbuf.rsvd1 = ctx_id;
  2090. * execbuf.flags = 0; // Submits to index 0 which is the virtual engine
  2091. * gem_execbuf(drm_fd, &execbuf);
  2092. */
  2093. /*
  2094. * i915_context_engines_load_balance:
  2095. *
  2096. * Enable load balancing across this set of engines.
  2097. *
  2098. * Into the I915_EXEC_DEFAULT slot [0], a virtual engine is created that when
  2099. * used will proxy the execbuffer request onto one of the set of engines
  2100. * in such a way as to distribute the load evenly across the set.
  2101. *
  2102. * The set of engines must be compatible (e.g. the same HW class) as they
  2103. * will share the same logical GPU context and ring.
  2104. *
  2105. * To intermix rendering with the virtual engine and direct rendering onto
  2106. * the backing engines (bypassing the load balancing proxy), the context must
  2107. * be defined to use a single timeline for all engines.
  2108. */
  2109. struct i915_context_engines_load_balance {
  2110. struct i915_user_extension base;
  2111. __u16 engine_index;
  2112. __u16 num_siblings;
  2113. __u32 flags; /* all undefined flags must be zero */
  2114. __u64 mbz64; /* reserved for future use; must be zero */
  2115. struct i915_engine_class_instance engines[];
  2116. } __attribute__((packed));
  2117. #define I915_DEFINE_CONTEXT_ENGINES_LOAD_BALANCE(name__, N__) struct { \
  2118. struct i915_user_extension base; \
  2119. __u16 engine_index; \
  2120. __u16 num_siblings; \
  2121. __u32 flags; \
  2122. __u64 mbz64; \
  2123. struct i915_engine_class_instance engines[N__]; \
  2124. } __attribute__((packed)) name__
  2125. /*
  2126. * i915_context_engines_bond:
  2127. *
  2128. * Constructed bonded pairs for execution within a virtual engine.
  2129. *
  2130. * All engines are equal, but some are more equal than others. Given
  2131. * the distribution of resources in the HW, it may be preferable to run
  2132. * a request on a given subset of engines in parallel to a request on a
  2133. * specific engine. We enable this selection of engines within a virtual
  2134. * engine by specifying bonding pairs, for any given master engine we will
  2135. * only execute on one of the corresponding siblings within the virtual engine.
  2136. *
  2137. * To execute a request in parallel on the master engine and a sibling requires
  2138. * coordination with a I915_EXEC_FENCE_SUBMIT.
  2139. */
  2140. struct i915_context_engines_bond {
  2141. struct i915_user_extension base;
  2142. struct i915_engine_class_instance master;
  2143. __u16 virtual_index; /* index of virtual engine in ctx->engines[] */
  2144. __u16 num_bonds;
  2145. __u64 flags; /* all undefined flags must be zero */
  2146. __u64 mbz64[4]; /* reserved for future use; must be zero */
  2147. struct i915_engine_class_instance engines[];
  2148. } __attribute__((packed));
  2149. #define I915_DEFINE_CONTEXT_ENGINES_BOND(name__, N__) struct { \
  2150. struct i915_user_extension base; \
  2151. struct i915_engine_class_instance master; \
  2152. __u16 virtual_index; \
  2153. __u16 num_bonds; \
  2154. __u64 flags; \
  2155. __u64 mbz64[4]; \
  2156. struct i915_engine_class_instance engines[N__]; \
  2157. } __attribute__((packed)) name__
  2158. /**
  2159. * struct i915_context_engines_parallel_submit - Configure engine for
  2160. * parallel submission.
  2161. *
  2162. * Setup a slot in the context engine map to allow multiple BBs to be submitted
  2163. * in a single execbuf IOCTL. Those BBs will then be scheduled to run on the GPU
  2164. * in parallel. Multiple hardware contexts are created internally in the i915 to
  2165. * run these BBs. Once a slot is configured for N BBs only N BBs can be
  2166. * submitted in each execbuf IOCTL and this is implicit behavior e.g. The user
  2167. * doesn't tell the execbuf IOCTL there are N BBs, the execbuf IOCTL knows how
  2168. * many BBs there are based on the slot's configuration. The N BBs are the last
  2169. * N buffer objects or first N if I915_EXEC_BATCH_FIRST is set.
  2170. *
  2171. * The default placement behavior is to create implicit bonds between each
  2172. * context if each context maps to more than 1 physical engine (e.g. context is
  2173. * a virtual engine). Also we only allow contexts of same engine class and these
  2174. * contexts must be in logically contiguous order. Examples of the placement
  2175. * behavior are described below. Lastly, the default is to not allow BBs to be
  2176. * preempted mid-batch. Rather insert coordinated preemption points on all
  2177. * hardware contexts between each set of BBs. Flags could be added in the future
  2178. * to change both of these default behaviors.
  2179. *
  2180. * Returns -EINVAL if hardware context placement configuration is invalid or if
  2181. * the placement configuration isn't supported on the platform / submission
  2182. * interface.
  2183. * Returns -ENODEV if extension isn't supported on the platform / submission
  2184. * interface.
  2185. *
  2186. * .. code-block:: none
  2187. *
  2188. * Examples syntax:
  2189. * CS[X] = generic engine of same class, logical instance X
  2190. * INVALID = I915_ENGINE_CLASS_INVALID, I915_ENGINE_CLASS_INVALID_NONE
  2191. *
  2192. * Example 1 pseudo code:
  2193. * set_engines(INVALID)
  2194. * set_parallel(engine_index=0, width=2, num_siblings=1,
  2195. * engines=CS[0],CS[1])
  2196. *
  2197. * Results in the following valid placement:
  2198. * CS[0], CS[1]
  2199. *
  2200. * Example 2 pseudo code:
  2201. * set_engines(INVALID)
  2202. * set_parallel(engine_index=0, width=2, num_siblings=2,
  2203. * engines=CS[0],CS[2],CS[1],CS[3])
  2204. *
  2205. * Results in the following valid placements:
  2206. * CS[0], CS[1]
  2207. * CS[2], CS[3]
  2208. *
  2209. * This can be thought of as two virtual engines, each containing two
  2210. * engines thereby making a 2D array. However, there are bonds tying the
  2211. * entries together and placing restrictions on how they can be scheduled.
  2212. * Specifically, the scheduler can choose only vertical columns from the 2D
  2213. * array. That is, CS[0] is bonded to CS[1] and CS[2] to CS[3]. So if the
  2214. * scheduler wants to submit to CS[0], it must also choose CS[1] and vice
  2215. * versa. Same for CS[2] requires also using CS[3].
  2216. * VE[0] = CS[0], CS[2]
  2217. * VE[1] = CS[1], CS[3]
  2218. *
  2219. * Example 3 pseudo code:
  2220. * set_engines(INVALID)
  2221. * set_parallel(engine_index=0, width=2, num_siblings=2,
  2222. * engines=CS[0],CS[1],CS[1],CS[3])
  2223. *
  2224. * Results in the following valid and invalid placements:
  2225. * CS[0], CS[1]
  2226. * CS[1], CS[3] - Not logically contiguous, return -EINVAL
  2227. */
  2228. struct i915_context_engines_parallel_submit {
  2229. /**
  2230. * @base: base user extension.
  2231. */
  2232. struct i915_user_extension base;
  2233. /**
  2234. * @engine_index: slot for parallel engine
  2235. */
  2236. __u16 engine_index;
  2237. /**
  2238. * @width: number of contexts per parallel engine or in other words the
  2239. * number of batches in each submission
  2240. */
  2241. __u16 width;
  2242. /**
  2243. * @num_siblings: number of siblings per context or in other words the
  2244. * number of possible placements for each submission
  2245. */
  2246. __u16 num_siblings;
  2247. /**
  2248. * @mbz16: reserved for future use; must be zero
  2249. */
  2250. __u16 mbz16;
  2251. /**
  2252. * @flags: all undefined flags must be zero, currently not defined flags
  2253. */
  2254. __u64 flags;
  2255. /**
  2256. * @mbz64: reserved for future use; must be zero
  2257. */
  2258. __u64 mbz64[3];
  2259. /**
  2260. * @engines: 2-d array of engine instances to configure parallel engine
  2261. *
  2262. * length = width (i) * num_siblings (j)
  2263. * index = j + i * num_siblings
  2264. */
  2265. struct i915_engine_class_instance engines[];
  2266. } __attribute__((packed));
  2267. #define I915_DEFINE_CONTEXT_ENGINES_PARALLEL_SUBMIT(name__, N__) struct { \
  2268. struct i915_user_extension base; \
  2269. __u16 engine_index; \
  2270. __u16 width; \
  2271. __u16 num_siblings; \
  2272. __u16 mbz16; \
  2273. __u64 flags; \
  2274. __u64 mbz64[3]; \
  2275. struct i915_engine_class_instance engines[N__]; \
  2276. } __attribute__((packed)) name__
  2277. /**
  2278. * DOC: Context Engine Map uAPI
  2279. *
  2280. * Context engine map is a new way of addressing engines when submitting batch-
  2281. * buffers, replacing the existing way of using identifiers like `I915_EXEC_BLT`
  2282. * inside the flags field of `struct drm_i915_gem_execbuffer2`.
  2283. *
  2284. * To use it created GEM contexts need to be configured with a list of engines
  2285. * the user is intending to submit to. This is accomplished using the
  2286. * `I915_CONTEXT_PARAM_ENGINES` parameter and `struct
  2287. * i915_context_param_engines`.
  2288. *
  2289. * For such contexts the `I915_EXEC_RING_MASK` field becomes an index into the
  2290. * configured map.
  2291. *
  2292. * Example of creating such context and submitting against it:
  2293. *
  2294. * .. code-block:: C
  2295. *
  2296. * I915_DEFINE_CONTEXT_PARAM_ENGINES(engines, 2) = {
  2297. * .engines = { { I915_ENGINE_CLASS_RENDER, 0 },
  2298. * { I915_ENGINE_CLASS_COPY, 0 } }
  2299. * };
  2300. * struct drm_i915_gem_context_create_ext_setparam p_engines = {
  2301. * .base = {
  2302. * .name = I915_CONTEXT_CREATE_EXT_SETPARAM,
  2303. * },
  2304. * .param = {
  2305. * .param = I915_CONTEXT_PARAM_ENGINES,
  2306. * .value = to_user_pointer(&engines),
  2307. * .size = sizeof(engines),
  2308. * },
  2309. * };
  2310. * struct drm_i915_gem_context_create_ext create = {
  2311. * .flags = I915_CONTEXT_CREATE_FLAGS_USE_EXTENSIONS,
  2312. * .extensions = to_user_pointer(&p_engines);
  2313. * };
  2314. *
  2315. * ctx_id = gem_context_create_ext(drm_fd, &create);
  2316. *
  2317. * // We have now created a GEM context with two engines in the map:
  2318. * // Index 0 points to rcs0 while index 1 points to bcs0. Other engines
  2319. * // will not be accessible from this context.
  2320. *
  2321. * ...
  2322. * execbuf.rsvd1 = ctx_id;
  2323. * execbuf.flags = 0; // Submits to index 0, which is rcs0 for this context
  2324. * gem_execbuf(drm_fd, &execbuf);
  2325. *
  2326. * ...
  2327. * execbuf.rsvd1 = ctx_id;
  2328. * execbuf.flags = 1; // Submits to index 0, which is bcs0 for this context
  2329. * gem_execbuf(drm_fd, &execbuf);
  2330. */
  2331. struct i915_context_param_engines {
  2332. __u64 extensions; /* linked chain of extension blocks, 0 terminates */
  2333. #define I915_CONTEXT_ENGINES_EXT_LOAD_BALANCE 0 /* see i915_context_engines_load_balance */
  2334. #define I915_CONTEXT_ENGINES_EXT_BOND 1 /* see i915_context_engines_bond */
  2335. #define I915_CONTEXT_ENGINES_EXT_PARALLEL_SUBMIT 2 /* see i915_context_engines_parallel_submit */
  2336. struct i915_engine_class_instance engines[];
  2337. } __attribute__((packed));
  2338. #define I915_DEFINE_CONTEXT_PARAM_ENGINES(name__, N__) struct { \
  2339. __u64 extensions; \
  2340. struct i915_engine_class_instance engines[N__]; \
  2341. } __attribute__((packed)) name__
  2342. struct i915_gem_context_param_context_image {
  2343. /** @engine: Engine class & instance to be configured. */
  2344. struct i915_engine_class_instance engine;
  2345. /** @flags: One of the supported flags or zero. */
  2346. __u32 flags;
  2347. #define I915_CONTEXT_IMAGE_FLAG_ENGINE_INDEX (1u << 0)
  2348. /** @size: Size of the image blob pointed to by @image. */
  2349. __u32 size;
  2350. /** @mbz: Must be zero. */
  2351. __u32 mbz;
  2352. /** @image: Userspace memory containing the context image. */
  2353. __u64 image;
  2354. } __attribute__((packed));
  2355. /**
  2356. * struct drm_i915_gem_context_create_ext_setparam - Context parameter
  2357. * to set or query during context creation.
  2358. */
  2359. struct drm_i915_gem_context_create_ext_setparam {
  2360. /** @base: Extension link. See struct i915_user_extension. */
  2361. struct i915_user_extension base;
  2362. /**
  2363. * @param: Context parameter to set or query.
  2364. * See struct drm_i915_gem_context_param.
  2365. */
  2366. struct drm_i915_gem_context_param param;
  2367. };
  2368. struct drm_i915_gem_context_destroy {
  2369. __u32 ctx_id;
  2370. __u32 pad;
  2371. };
  2372. /**
  2373. * struct drm_i915_gem_vm_control - Structure to create or destroy VM.
  2374. *
  2375. * DRM_I915_GEM_VM_CREATE -
  2376. *
  2377. * Create a new virtual memory address space (ppGTT) for use within a context
  2378. * on the same file. Extensions can be provided to configure exactly how the
  2379. * address space is setup upon creation.
  2380. *
  2381. * The id of new VM (bound to the fd) for use with I915_CONTEXT_PARAM_VM is
  2382. * returned in the outparam @id.
  2383. *
  2384. * An extension chain maybe provided, starting with @extensions, and terminated
  2385. * by the @next_extension being 0. Currently, no extensions are defined.
  2386. *
  2387. * DRM_I915_GEM_VM_DESTROY -
  2388. *
  2389. * Destroys a previously created VM id, specified in @vm_id.
  2390. *
  2391. * No extensions or flags are allowed currently, and so must be zero.
  2392. */
  2393. struct drm_i915_gem_vm_control {
  2394. /** @extensions: Zero-terminated chain of extensions. */
  2395. __u64 extensions;
  2396. /** @flags: reserved for future usage, currently MBZ */
  2397. __u32 flags;
  2398. /** @vm_id: Id of the VM created or to be destroyed */
  2399. __u32 vm_id;
  2400. };
  2401. struct drm_i915_reg_read {
  2402. /*
  2403. * Register offset.
  2404. * For 64bit wide registers where the upper 32bits don't immediately
  2405. * follow the lower 32bits, the offset of the lower 32bits must
  2406. * be specified
  2407. */
  2408. __u64 offset;
  2409. #define I915_REG_READ_8B_WA (1ul << 0)
  2410. __u64 val; /* Return value */
  2411. };
  2412. /* Known registers:
  2413. *
  2414. * Render engine timestamp - 0x2358 + 64bit - gen7+
  2415. * - Note this register returns an invalid value if using the default
  2416. * single instruction 8byte read, in order to workaround that pass
  2417. * flag I915_REG_READ_8B_WA in offset field.
  2418. *
  2419. */
  2420. /*
  2421. * struct drm_i915_reset_stats - Return global reset and other context stats
  2422. *
  2423. * Driver keeps few stats for each contexts and also global reset count.
  2424. * This struct can be used to query those stats.
  2425. */
  2426. struct drm_i915_reset_stats {
  2427. /** @ctx_id: ID of the requested context */
  2428. __u32 ctx_id;
  2429. /** @flags: MBZ */
  2430. __u32 flags;
  2431. /** @reset_count: All resets since boot/module reload, for all contexts */
  2432. __u32 reset_count;
  2433. /** @batch_active: Number of batches lost when active in GPU, for this context */
  2434. __u32 batch_active;
  2435. /** @batch_pending: Number of batches lost pending for execution, for this context */
  2436. __u32 batch_pending;
  2437. /** @pad: MBZ */
  2438. __u32 pad;
  2439. };
  2440. /**
  2441. * struct drm_i915_gem_userptr - Create GEM object from user allocated memory.
  2442. *
  2443. * Userptr objects have several restrictions on what ioctls can be used with the
  2444. * object handle.
  2445. */
  2446. struct drm_i915_gem_userptr {
  2447. /**
  2448. * @user_ptr: The pointer to the allocated memory.
  2449. *
  2450. * Needs to be aligned to PAGE_SIZE.
  2451. */
  2452. __u64 user_ptr;
  2453. /**
  2454. * @user_size:
  2455. *
  2456. * The size in bytes for the allocated memory. This will also become the
  2457. * object size.
  2458. *
  2459. * Needs to be aligned to PAGE_SIZE, and should be at least PAGE_SIZE,
  2460. * or larger.
  2461. */
  2462. __u64 user_size;
  2463. /**
  2464. * @flags:
  2465. *
  2466. * Supported flags:
  2467. *
  2468. * I915_USERPTR_READ_ONLY:
  2469. *
  2470. * Mark the object as readonly, this also means GPU access can only be
  2471. * readonly. This is only supported on HW which supports readonly access
  2472. * through the GTT. If the HW can't support readonly access, an error is
  2473. * returned.
  2474. *
  2475. * I915_USERPTR_PROBE:
  2476. *
  2477. * Probe the provided @user_ptr range and validate that the @user_ptr is
  2478. * indeed pointing to normal memory and that the range is also valid.
  2479. * For example if some garbage address is given to the kernel, then this
  2480. * should complain.
  2481. *
  2482. * Returns -EFAULT if the probe failed.
  2483. *
  2484. * Note that this doesn't populate the backing pages, and also doesn't
  2485. * guarantee that the object will remain valid when the object is
  2486. * eventually used.
  2487. *
  2488. * The kernel supports this feature if I915_PARAM_HAS_USERPTR_PROBE
  2489. * returns a non-zero value.
  2490. *
  2491. * I915_USERPTR_UNSYNCHRONIZED:
  2492. *
  2493. * NOT USED. Setting this flag will result in an error.
  2494. */
  2495. __u32 flags;
  2496. #define I915_USERPTR_READ_ONLY 0x1
  2497. #define I915_USERPTR_PROBE 0x2
  2498. #define I915_USERPTR_UNSYNCHRONIZED 0x80000000
  2499. /**
  2500. * @handle: Returned handle for the object.
  2501. *
  2502. * Object handles are nonzero.
  2503. */
  2504. __u32 handle;
  2505. };
  2506. enum drm_i915_oa_format {
  2507. I915_OA_FORMAT_A13 = 1, /* HSW only */
  2508. I915_OA_FORMAT_A29, /* HSW only */
  2509. I915_OA_FORMAT_A13_B8_C8, /* HSW only */
  2510. I915_OA_FORMAT_B4_C8, /* HSW only */
  2511. I915_OA_FORMAT_A45_B8_C8, /* HSW only */
  2512. I915_OA_FORMAT_B4_C8_A16, /* HSW only */
  2513. I915_OA_FORMAT_C4_B8, /* HSW+ */
  2514. /* Gen8+ */
  2515. I915_OA_FORMAT_A12,
  2516. I915_OA_FORMAT_A12_B8_C8,
  2517. I915_OA_FORMAT_A32u40_A4u32_B8_C8,
  2518. /* DG2 */
  2519. I915_OAR_FORMAT_A32u40_A4u32_B8_C8,
  2520. I915_OA_FORMAT_A24u40_A14u32_B8_C8,
  2521. /* MTL OAM */
  2522. I915_OAM_FORMAT_MPEC8u64_B8_C8,
  2523. I915_OAM_FORMAT_MPEC8u32_B8_C8,
  2524. I915_OA_FORMAT_MAX /* non-ABI */
  2525. };
  2526. enum drm_i915_perf_property_id {
  2527. /**
  2528. * Open the stream for a specific context handle (as used with
  2529. * execbuffer2). A stream opened for a specific context this way
  2530. * won't typically require root privileges.
  2531. *
  2532. * This property is available in perf revision 1.
  2533. */
  2534. DRM_I915_PERF_PROP_CTX_HANDLE = 1,
  2535. /**
  2536. * A value of 1 requests the inclusion of raw OA unit reports as
  2537. * part of stream samples.
  2538. *
  2539. * This property is available in perf revision 1.
  2540. */
  2541. DRM_I915_PERF_PROP_SAMPLE_OA,
  2542. /**
  2543. * The value specifies which set of OA unit metrics should be
  2544. * configured, defining the contents of any OA unit reports.
  2545. *
  2546. * This property is available in perf revision 1.
  2547. */
  2548. DRM_I915_PERF_PROP_OA_METRICS_SET,
  2549. /**
  2550. * The value specifies the size and layout of OA unit reports.
  2551. *
  2552. * This property is available in perf revision 1.
  2553. */
  2554. DRM_I915_PERF_PROP_OA_FORMAT,
  2555. /**
  2556. * Specifying this property implicitly requests periodic OA unit
  2557. * sampling and (at least on Haswell) the sampling frequency is derived
  2558. * from this exponent as follows:
  2559. *
  2560. * 80ns * 2^(period_exponent + 1)
  2561. *
  2562. * This property is available in perf revision 1.
  2563. */
  2564. DRM_I915_PERF_PROP_OA_EXPONENT,
  2565. /**
  2566. * Specifying this property is only valid when specify a context to
  2567. * filter with DRM_I915_PERF_PROP_CTX_HANDLE. Specifying this property
  2568. * will hold preemption of the particular context we want to gather
  2569. * performance data about. The execbuf2 submissions must include a
  2570. * drm_i915_gem_execbuffer_ext_perf parameter for this to apply.
  2571. *
  2572. * This property is available in perf revision 3.
  2573. */
  2574. DRM_I915_PERF_PROP_HOLD_PREEMPTION,
  2575. /**
  2576. * Specifying this pins all contexts to the specified SSEU power
  2577. * configuration for the duration of the recording.
  2578. *
  2579. * This parameter's value is a pointer to a struct
  2580. * drm_i915_gem_context_param_sseu.
  2581. *
  2582. * This property is available in perf revision 4.
  2583. */
  2584. DRM_I915_PERF_PROP_GLOBAL_SSEU,
  2585. /**
  2586. * This optional parameter specifies the timer interval in nanoseconds
  2587. * at which the i915 driver will check the OA buffer for available data.
  2588. * Minimum allowed value is 100 microseconds. A default value is used by
  2589. * the driver if this parameter is not specified. Note that larger timer
  2590. * values will reduce cpu consumption during OA perf captures. However,
  2591. * excessively large values would potentially result in OA buffer
  2592. * overwrites as captures reach end of the OA buffer.
  2593. *
  2594. * This property is available in perf revision 5.
  2595. */
  2596. DRM_I915_PERF_PROP_POLL_OA_PERIOD,
  2597. /**
  2598. * Multiple engines may be mapped to the same OA unit. The OA unit is
  2599. * identified by class:instance of any engine mapped to it.
  2600. *
  2601. * This parameter specifies the engine class and must be passed along
  2602. * with DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE.
  2603. *
  2604. * This property is available in perf revision 6.
  2605. */
  2606. DRM_I915_PERF_PROP_OA_ENGINE_CLASS,
  2607. /**
  2608. * This parameter specifies the engine instance and must be passed along
  2609. * with DRM_I915_PERF_PROP_OA_ENGINE_CLASS.
  2610. *
  2611. * This property is available in perf revision 6.
  2612. */
  2613. DRM_I915_PERF_PROP_OA_ENGINE_INSTANCE,
  2614. DRM_I915_PERF_PROP_MAX /* non-ABI */
  2615. };
  2616. struct drm_i915_perf_open_param {
  2617. __u32 flags;
  2618. #define I915_PERF_FLAG_FD_CLOEXEC (1<<0)
  2619. #define I915_PERF_FLAG_FD_NONBLOCK (1<<1)
  2620. #define I915_PERF_FLAG_DISABLED (1<<2)
  2621. /** The number of u64 (id, value) pairs */
  2622. __u32 num_properties;
  2623. /**
  2624. * Pointer to array of u64 (id, value) pairs configuring the stream
  2625. * to open.
  2626. */
  2627. __u64 properties_ptr;
  2628. };
  2629. /*
  2630. * Enable data capture for a stream that was either opened in a disabled state
  2631. * via I915_PERF_FLAG_DISABLED or was later disabled via
  2632. * I915_PERF_IOCTL_DISABLE.
  2633. *
  2634. * It is intended to be cheaper to disable and enable a stream than it may be
  2635. * to close and re-open a stream with the same configuration.
  2636. *
  2637. * It's undefined whether any pending data for the stream will be lost.
  2638. *
  2639. * This ioctl is available in perf revision 1.
  2640. */
  2641. #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0)
  2642. /*
  2643. * Disable data capture for a stream.
  2644. *
  2645. * It is an error to try and read a stream that is disabled.
  2646. *
  2647. * This ioctl is available in perf revision 1.
  2648. */
  2649. #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1)
  2650. /*
  2651. * Change metrics_set captured by a stream.
  2652. *
  2653. * If the stream is bound to a specific context, the configuration change
  2654. * will performed __inline__ with that context such that it takes effect before
  2655. * the next execbuf submission.
  2656. *
  2657. * Returns the previously bound metrics set id, or a negative error code.
  2658. *
  2659. * This ioctl is available in perf revision 2.
  2660. */
  2661. #define I915_PERF_IOCTL_CONFIG _IO('i', 0x2)
  2662. /*
  2663. * Common to all i915 perf records
  2664. */
  2665. struct drm_i915_perf_record_header {
  2666. __u32 type;
  2667. __u16 pad;
  2668. __u16 size;
  2669. };
  2670. enum drm_i915_perf_record_type {
  2671. /**
  2672. * Samples are the work horse record type whose contents are extensible
  2673. * and defined when opening an i915 perf stream based on the given
  2674. * properties.
  2675. *
  2676. * Boolean properties following the naming convention
  2677. * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in
  2678. * every sample.
  2679. *
  2680. * The order of these sample properties given by userspace has no
  2681. * affect on the ordering of data within a sample. The order is
  2682. * documented here.
  2683. *
  2684. * struct {
  2685. * struct drm_i915_perf_record_header header;
  2686. *
  2687. * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA
  2688. * };
  2689. */
  2690. DRM_I915_PERF_RECORD_SAMPLE = 1,
  2691. /*
  2692. * Indicates that one or more OA reports were not written by the
  2693. * hardware. This can happen for example if an MI_REPORT_PERF_COUNT
  2694. * command collides with periodic sampling - which would be more likely
  2695. * at higher sampling frequencies.
  2696. */
  2697. DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2,
  2698. /**
  2699. * An error occurred that resulted in all pending OA reports being lost.
  2700. */
  2701. DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3,
  2702. DRM_I915_PERF_RECORD_MAX /* non-ABI */
  2703. };
  2704. /**
  2705. * struct drm_i915_perf_oa_config
  2706. *
  2707. * Structure to upload perf dynamic configuration into the kernel.
  2708. */
  2709. struct drm_i915_perf_oa_config {
  2710. /**
  2711. * @uuid:
  2712. *
  2713. * String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x"
  2714. */
  2715. char uuid[36];
  2716. /**
  2717. * @n_mux_regs:
  2718. *
  2719. * Number of mux regs in &mux_regs_ptr.
  2720. */
  2721. __u32 n_mux_regs;
  2722. /**
  2723. * @n_boolean_regs:
  2724. *
  2725. * Number of boolean regs in &boolean_regs_ptr.
  2726. */
  2727. __u32 n_boolean_regs;
  2728. /**
  2729. * @n_flex_regs:
  2730. *
  2731. * Number of flex regs in &flex_regs_ptr.
  2732. */
  2733. __u32 n_flex_regs;
  2734. /**
  2735. * @mux_regs_ptr:
  2736. *
  2737. * Pointer to tuples of u32 values (register address, value) for mux
  2738. * registers. Expected length of buffer is (2 * sizeof(u32) *
  2739. * &n_mux_regs).
  2740. */
  2741. __u64 mux_regs_ptr;
  2742. /**
  2743. * @boolean_regs_ptr:
  2744. *
  2745. * Pointer to tuples of u32 values (register address, value) for mux
  2746. * registers. Expected length of buffer is (2 * sizeof(u32) *
  2747. * &n_boolean_regs).
  2748. */
  2749. __u64 boolean_regs_ptr;
  2750. /**
  2751. * @flex_regs_ptr:
  2752. *
  2753. * Pointer to tuples of u32 values (register address, value) for mux
  2754. * registers. Expected length of buffer is (2 * sizeof(u32) *
  2755. * &n_flex_regs).
  2756. */
  2757. __u64 flex_regs_ptr;
  2758. };
  2759. /**
  2760. * struct drm_i915_query_item - An individual query for the kernel to process.
  2761. *
  2762. * The behaviour is determined by the @query_id. Note that exactly what
  2763. * @data_ptr is also depends on the specific @query_id.
  2764. */
  2765. struct drm_i915_query_item {
  2766. /**
  2767. * @query_id:
  2768. *
  2769. * The id for this query. Currently accepted query IDs are:
  2770. * - %DRM_I915_QUERY_TOPOLOGY_INFO (see struct drm_i915_query_topology_info)
  2771. * - %DRM_I915_QUERY_ENGINE_INFO (see struct drm_i915_engine_info)
  2772. * - %DRM_I915_QUERY_PERF_CONFIG (see struct drm_i915_query_perf_config)
  2773. * - %DRM_I915_QUERY_MEMORY_REGIONS (see struct drm_i915_query_memory_regions)
  2774. * - %DRM_I915_QUERY_HWCONFIG_BLOB (see `GuC HWCONFIG blob uAPI`)
  2775. * - %DRM_I915_QUERY_GEOMETRY_SUBSLICES (see struct drm_i915_query_topology_info)
  2776. * - %DRM_I915_QUERY_GUC_SUBMISSION_VERSION (see struct drm_i915_query_guc_submission_version)
  2777. */
  2778. __u64 query_id;
  2779. #define DRM_I915_QUERY_TOPOLOGY_INFO 1
  2780. #define DRM_I915_QUERY_ENGINE_INFO 2
  2781. #define DRM_I915_QUERY_PERF_CONFIG 3
  2782. #define DRM_I915_QUERY_MEMORY_REGIONS 4
  2783. #define DRM_I915_QUERY_HWCONFIG_BLOB 5
  2784. #define DRM_I915_QUERY_GEOMETRY_SUBSLICES 6
  2785. #define DRM_I915_QUERY_GUC_SUBMISSION_VERSION 7
  2786. /* Must be kept compact -- no holes and well documented */
  2787. /**
  2788. * @length:
  2789. *
  2790. * When set to zero by userspace, this is filled with the size of the
  2791. * data to be written at the @data_ptr pointer. The kernel sets this
  2792. * value to a negative value to signal an error on a particular query
  2793. * item.
  2794. */
  2795. __s32 length;
  2796. /**
  2797. * @flags:
  2798. *
  2799. * When &query_id == %DRM_I915_QUERY_TOPOLOGY_INFO, must be 0.
  2800. *
  2801. * When &query_id == %DRM_I915_QUERY_PERF_CONFIG, must be one of the
  2802. * following:
  2803. *
  2804. * - %DRM_I915_QUERY_PERF_CONFIG_LIST
  2805. * - %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID
  2806. * - %DRM_I915_QUERY_PERF_CONFIG_FOR_UUID
  2807. *
  2808. * When &query_id == %DRM_I915_QUERY_GEOMETRY_SUBSLICES must contain
  2809. * a struct i915_engine_class_instance that references a render engine.
  2810. */
  2811. __u32 flags;
  2812. #define DRM_I915_QUERY_PERF_CONFIG_LIST 1
  2813. #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID 2
  2814. #define DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID 3
  2815. /**
  2816. * @data_ptr:
  2817. *
  2818. * Data will be written at the location pointed by @data_ptr when the
  2819. * value of @length matches the length of the data to be written by the
  2820. * kernel.
  2821. */
  2822. __u64 data_ptr;
  2823. };
  2824. /**
  2825. * struct drm_i915_query - Supply an array of struct drm_i915_query_item for the
  2826. * kernel to fill out.
  2827. *
  2828. * Note that this is generally a two step process for each struct
  2829. * drm_i915_query_item in the array:
  2830. *
  2831. * 1. Call the DRM_IOCTL_I915_QUERY, giving it our array of struct
  2832. * drm_i915_query_item, with &drm_i915_query_item.length set to zero. The
  2833. * kernel will then fill in the size, in bytes, which tells userspace how
  2834. * memory it needs to allocate for the blob(say for an array of properties).
  2835. *
  2836. * 2. Next we call DRM_IOCTL_I915_QUERY again, this time with the
  2837. * &drm_i915_query_item.data_ptr equal to our newly allocated blob. Note that
  2838. * the &drm_i915_query_item.length should still be the same as what the
  2839. * kernel previously set. At this point the kernel can fill in the blob.
  2840. *
  2841. * Note that for some query items it can make sense for userspace to just pass
  2842. * in a buffer/blob equal to or larger than the required size. In this case only
  2843. * a single ioctl call is needed. For some smaller query items this can work
  2844. * quite well.
  2845. *
  2846. */
  2847. struct drm_i915_query {
  2848. /** @num_items: The number of elements in the @items_ptr array */
  2849. __u32 num_items;
  2850. /**
  2851. * @flags: Unused for now. Must be cleared to zero.
  2852. */
  2853. __u32 flags;
  2854. /**
  2855. * @items_ptr:
  2856. *
  2857. * Pointer to an array of struct drm_i915_query_item. The number of
  2858. * array elements is @num_items.
  2859. */
  2860. __u64 items_ptr;
  2861. };
  2862. /**
  2863. * struct drm_i915_query_topology_info
  2864. *
  2865. * Describes slice/subslice/EU information queried by
  2866. * %DRM_I915_QUERY_TOPOLOGY_INFO
  2867. */
  2868. struct drm_i915_query_topology_info {
  2869. /**
  2870. * @flags:
  2871. *
  2872. * Unused for now. Must be cleared to zero.
  2873. */
  2874. __u16 flags;
  2875. /**
  2876. * @max_slices:
  2877. *
  2878. * The number of bits used to express the slice mask.
  2879. */
  2880. __u16 max_slices;
  2881. /**
  2882. * @max_subslices:
  2883. *
  2884. * The number of bits used to express the subslice mask.
  2885. */
  2886. __u16 max_subslices;
  2887. /**
  2888. * @max_eus_per_subslice:
  2889. *
  2890. * The number of bits in the EU mask that correspond to a single
  2891. * subslice's EUs.
  2892. */
  2893. __u16 max_eus_per_subslice;
  2894. /**
  2895. * @subslice_offset:
  2896. *
  2897. * Offset in data[] at which the subslice masks are stored.
  2898. */
  2899. __u16 subslice_offset;
  2900. /**
  2901. * @subslice_stride:
  2902. *
  2903. * Stride at which each of the subslice masks for each slice are
  2904. * stored.
  2905. */
  2906. __u16 subslice_stride;
  2907. /**
  2908. * @eu_offset:
  2909. *
  2910. * Offset in data[] at which the EU masks are stored.
  2911. */
  2912. __u16 eu_offset;
  2913. /**
  2914. * @eu_stride:
  2915. *
  2916. * Stride at which each of the EU masks for each subslice are stored.
  2917. */
  2918. __u16 eu_stride;
  2919. /**
  2920. * @data:
  2921. *
  2922. * Contains 3 pieces of information :
  2923. *
  2924. * - The slice mask with one bit per slice telling whether a slice is
  2925. * available. The availability of slice X can be queried with the
  2926. * following formula :
  2927. *
  2928. * .. code:: c
  2929. *
  2930. * (data[X / 8] >> (X % 8)) & 1
  2931. *
  2932. * Starting with Xe_HP platforms, Intel hardware no longer has
  2933. * traditional slices so i915 will always report a single slice
  2934. * (hardcoded slicemask = 0x1) which contains all of the platform's
  2935. * subslices. I.e., the mask here does not reflect any of the newer
  2936. * hardware concepts such as "gslices" or "cslices" since userspace
  2937. * is capable of inferring those from the subslice mask.
  2938. *
  2939. * - The subslice mask for each slice with one bit per subslice telling
  2940. * whether a subslice is available. Starting with Gen12 we use the
  2941. * term "subslice" to refer to what the hardware documentation
  2942. * describes as a "dual-subslices." The availability of subslice Y
  2943. * in slice X can be queried with the following formula :
  2944. *
  2945. * .. code:: c
  2946. *
  2947. * (data[subslice_offset + X * subslice_stride + Y / 8] >> (Y % 8)) & 1
  2948. *
  2949. * - The EU mask for each subslice in each slice, with one bit per EU
  2950. * telling whether an EU is available. The availability of EU Z in
  2951. * subslice Y in slice X can be queried with the following formula :
  2952. *
  2953. * .. code:: c
  2954. *
  2955. * (data[eu_offset +
  2956. * (X * max_subslices + Y) * eu_stride +
  2957. * Z / 8
  2958. * ] >> (Z % 8)) & 1
  2959. */
  2960. __u8 data[];
  2961. };
  2962. /**
  2963. * DOC: Engine Discovery uAPI
  2964. *
  2965. * Engine discovery uAPI is a way of enumerating physical engines present in a
  2966. * GPU associated with an open i915 DRM file descriptor. This supersedes the old
  2967. * way of using `DRM_IOCTL_I915_GETPARAM` and engine identifiers like
  2968. * `I915_PARAM_HAS_BLT`.
  2969. *
  2970. * The need for this interface came starting with Icelake and newer GPUs, which
  2971. * started to establish a pattern of having multiple engines of a same class,
  2972. * where not all instances were always completely functionally equivalent.
  2973. *
  2974. * Entry point for this uapi is `DRM_IOCTL_I915_QUERY` with the
  2975. * `DRM_I915_QUERY_ENGINE_INFO` as the queried item id.
  2976. *
  2977. * Example for getting the list of engines:
  2978. *
  2979. * .. code-block:: C
  2980. *
  2981. * struct drm_i915_query_engine_info *info;
  2982. * struct drm_i915_query_item item = {
  2983. * .query_id = DRM_I915_QUERY_ENGINE_INFO;
  2984. * };
  2985. * struct drm_i915_query query = {
  2986. * .num_items = 1,
  2987. * .items_ptr = (uintptr_t)&item,
  2988. * };
  2989. * int err, i;
  2990. *
  2991. * // First query the size of the blob we need, this needs to be large
  2992. * // enough to hold our array of engines. The kernel will fill out the
  2993. * // item.length for us, which is the number of bytes we need.
  2994. * //
  2995. * // Alternatively a large buffer can be allocated straightaway enabling
  2996. * // querying in one pass, in which case item.length should contain the
  2997. * // length of the provided buffer.
  2998. * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
  2999. * if (err) ...
  3000. *
  3001. * info = calloc(1, item.length);
  3002. * // Now that we allocated the required number of bytes, we call the ioctl
  3003. * // again, this time with the data_ptr pointing to our newly allocated
  3004. * // blob, which the kernel can then populate with info on all engines.
  3005. * item.data_ptr = (uintptr_t)&info;
  3006. *
  3007. * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
  3008. * if (err) ...
  3009. *
  3010. * // We can now access each engine in the array
  3011. * for (i = 0; i < info->num_engines; i++) {
  3012. * struct drm_i915_engine_info einfo = info->engines[i];
  3013. * u16 class = einfo.engine.class;
  3014. * u16 instance = einfo.engine.instance;
  3015. * ....
  3016. * }
  3017. *
  3018. * free(info);
  3019. *
  3020. * Each of the enumerated engines, apart from being defined by its class and
  3021. * instance (see `struct i915_engine_class_instance`), also can have flags and
  3022. * capabilities defined as documented in i915_drm.h.
  3023. *
  3024. * For instance video engines which support HEVC encoding will have the
  3025. * `I915_VIDEO_CLASS_CAPABILITY_HEVC` capability bit set.
  3026. *
  3027. * Engine discovery only fully comes to its own when combined with the new way
  3028. * of addressing engines when submitting batch buffers using contexts with
  3029. * engine maps configured.
  3030. */
  3031. /**
  3032. * struct drm_i915_engine_info
  3033. *
  3034. * Describes one engine and its capabilities as known to the driver.
  3035. */
  3036. struct drm_i915_engine_info {
  3037. /** @engine: Engine class and instance. */
  3038. struct i915_engine_class_instance engine;
  3039. /** @rsvd0: Reserved field. */
  3040. __u32 rsvd0;
  3041. /** @flags: Engine flags. */
  3042. __u64 flags;
  3043. #define I915_ENGINE_INFO_HAS_LOGICAL_INSTANCE (1 << 0)
  3044. /** @capabilities: Capabilities of this engine. */
  3045. __u64 capabilities;
  3046. #define I915_VIDEO_CLASS_CAPABILITY_HEVC (1 << 0)
  3047. #define I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC (1 << 1)
  3048. /** @logical_instance: Logical instance of engine */
  3049. __u16 logical_instance;
  3050. /** @rsvd1: Reserved fields. */
  3051. __u16 rsvd1[3];
  3052. /** @rsvd2: Reserved fields. */
  3053. __u64 rsvd2[3];
  3054. };
  3055. /**
  3056. * struct drm_i915_query_engine_info
  3057. *
  3058. * Engine info query enumerates all engines known to the driver by filling in
  3059. * an array of struct drm_i915_engine_info structures.
  3060. */
  3061. struct drm_i915_query_engine_info {
  3062. /** @num_engines: Number of struct drm_i915_engine_info structs following. */
  3063. __u32 num_engines;
  3064. /** @rsvd: MBZ */
  3065. __u32 rsvd[3];
  3066. /** @engines: Marker for drm_i915_engine_info structures. */
  3067. struct drm_i915_engine_info engines[];
  3068. };
  3069. /**
  3070. * struct drm_i915_query_perf_config
  3071. *
  3072. * Data written by the kernel with query %DRM_I915_QUERY_PERF_CONFIG and
  3073. * %DRM_I915_QUERY_GEOMETRY_SUBSLICES.
  3074. */
  3075. struct drm_i915_query_perf_config {
  3076. union {
  3077. /**
  3078. * @n_configs:
  3079. *
  3080. * When &drm_i915_query_item.flags ==
  3081. * %DRM_I915_QUERY_PERF_CONFIG_LIST, i915 sets this fields to
  3082. * the number of configurations available.
  3083. */
  3084. __u64 n_configs;
  3085. /**
  3086. * @config:
  3087. *
  3088. * When &drm_i915_query_item.flags ==
  3089. * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_ID, i915 will use the
  3090. * value in this field as configuration identifier to decide
  3091. * what data to write into config_ptr.
  3092. */
  3093. __u64 config;
  3094. /**
  3095. * @uuid:
  3096. *
  3097. * When &drm_i915_query_item.flags ==
  3098. * %DRM_I915_QUERY_PERF_CONFIG_DATA_FOR_UUID, i915 will use the
  3099. * value in this field as configuration identifier to decide
  3100. * what data to write into config_ptr.
  3101. *
  3102. * String formatted like "%08x-%04x-%04x-%04x-%012x"
  3103. */
  3104. char uuid[36];
  3105. };
  3106. /**
  3107. * @flags:
  3108. *
  3109. * Unused for now. Must be cleared to zero.
  3110. */
  3111. __u32 flags;
  3112. /**
  3113. * @data:
  3114. *
  3115. * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_LIST,
  3116. * i915 will write an array of __u64 of configuration identifiers.
  3117. *
  3118. * When &drm_i915_query_item.flags == %DRM_I915_QUERY_PERF_CONFIG_DATA,
  3119. * i915 will write a struct drm_i915_perf_oa_config. If the following
  3120. * fields of struct drm_i915_perf_oa_config are not set to 0, i915 will
  3121. * write into the associated pointers the values of submitted when the
  3122. * configuration was created :
  3123. *
  3124. * - &drm_i915_perf_oa_config.n_mux_regs
  3125. * - &drm_i915_perf_oa_config.n_boolean_regs
  3126. * - &drm_i915_perf_oa_config.n_flex_regs
  3127. */
  3128. __u8 data[];
  3129. };
  3130. /**
  3131. * enum drm_i915_gem_memory_class - Supported memory classes
  3132. */
  3133. enum drm_i915_gem_memory_class {
  3134. /** @I915_MEMORY_CLASS_SYSTEM: System memory */
  3135. I915_MEMORY_CLASS_SYSTEM = 0,
  3136. /** @I915_MEMORY_CLASS_DEVICE: Device local-memory */
  3137. I915_MEMORY_CLASS_DEVICE,
  3138. };
  3139. /**
  3140. * struct drm_i915_gem_memory_class_instance - Identify particular memory region
  3141. */
  3142. struct drm_i915_gem_memory_class_instance {
  3143. /** @memory_class: See enum drm_i915_gem_memory_class */
  3144. __u16 memory_class;
  3145. /** @memory_instance: Which instance */
  3146. __u16 memory_instance;
  3147. };
  3148. /**
  3149. * struct drm_i915_memory_region_info - Describes one region as known to the
  3150. * driver.
  3151. *
  3152. * Note this is using both struct drm_i915_query_item and struct drm_i915_query.
  3153. * For this new query we are adding the new query id DRM_I915_QUERY_MEMORY_REGIONS
  3154. * at &drm_i915_query_item.query_id.
  3155. */
  3156. struct drm_i915_memory_region_info {
  3157. /** @region: The class:instance pair encoding */
  3158. struct drm_i915_gem_memory_class_instance region;
  3159. /** @rsvd0: MBZ */
  3160. __u32 rsvd0;
  3161. /**
  3162. * @probed_size: Memory probed by the driver
  3163. *
  3164. * Note that it should not be possible to ever encounter a zero value
  3165. * here, also note that no current region type will ever return -1 here.
  3166. * Although for future region types, this might be a possibility. The
  3167. * same applies to the other size fields.
  3168. */
  3169. __u64 probed_size;
  3170. /**
  3171. * @unallocated_size: Estimate of memory remaining
  3172. *
  3173. * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable accounting.
  3174. * Without this (or if this is an older kernel) the value here will
  3175. * always equal the @probed_size. Note this is only currently tracked
  3176. * for I915_MEMORY_CLASS_DEVICE regions (for other types the value here
  3177. * will always equal the @probed_size).
  3178. */
  3179. __u64 unallocated_size;
  3180. union {
  3181. /** @rsvd1: MBZ */
  3182. __u64 rsvd1[8];
  3183. struct {
  3184. /**
  3185. * @probed_cpu_visible_size: Memory probed by the driver
  3186. * that is CPU accessible.
  3187. *
  3188. * This will be always be <= @probed_size, and the
  3189. * remainder (if there is any) will not be CPU
  3190. * accessible.
  3191. *
  3192. * On systems without small BAR, the @probed_size will
  3193. * always equal the @probed_cpu_visible_size, since all
  3194. * of it will be CPU accessible.
  3195. *
  3196. * Note this is only tracked for
  3197. * I915_MEMORY_CLASS_DEVICE regions (for other types the
  3198. * value here will always equal the @probed_size).
  3199. *
  3200. * Note that if the value returned here is zero, then
  3201. * this must be an old kernel which lacks the relevant
  3202. * small-bar uAPI support (including
  3203. * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS), but on
  3204. * such systems we should never actually end up with a
  3205. * small BAR configuration, assuming we are able to load
  3206. * the kernel module. Hence it should be safe to treat
  3207. * this the same as when @probed_cpu_visible_size ==
  3208. * @probed_size.
  3209. */
  3210. __u64 probed_cpu_visible_size;
  3211. /**
  3212. * @unallocated_cpu_visible_size: Estimate of CPU
  3213. * visible memory remaining.
  3214. *
  3215. * Note this is only tracked for
  3216. * I915_MEMORY_CLASS_DEVICE regions (for other types the
  3217. * value here will always equal the
  3218. * @probed_cpu_visible_size).
  3219. *
  3220. * Requires CAP_PERFMON or CAP_SYS_ADMIN to get reliable
  3221. * accounting. Without this the value here will always
  3222. * equal the @probed_cpu_visible_size. Note this is only
  3223. * currently tracked for I915_MEMORY_CLASS_DEVICE
  3224. * regions (for other types the value here will also
  3225. * always equal the @probed_cpu_visible_size).
  3226. *
  3227. * If this is an older kernel the value here will be
  3228. * zero, see also @probed_cpu_visible_size.
  3229. */
  3230. __u64 unallocated_cpu_visible_size;
  3231. };
  3232. };
  3233. };
  3234. /**
  3235. * struct drm_i915_query_memory_regions
  3236. *
  3237. * The region info query enumerates all regions known to the driver by filling
  3238. * in an array of struct drm_i915_memory_region_info structures.
  3239. *
  3240. * Example for getting the list of supported regions:
  3241. *
  3242. * .. code-block:: C
  3243. *
  3244. * struct drm_i915_query_memory_regions *info;
  3245. * struct drm_i915_query_item item = {
  3246. * .query_id = DRM_I915_QUERY_MEMORY_REGIONS;
  3247. * };
  3248. * struct drm_i915_query query = {
  3249. * .num_items = 1,
  3250. * .items_ptr = (uintptr_t)&item,
  3251. * };
  3252. * int err, i;
  3253. *
  3254. * // First query the size of the blob we need, this needs to be large
  3255. * // enough to hold our array of regions. The kernel will fill out the
  3256. * // item.length for us, which is the number of bytes we need.
  3257. * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
  3258. * if (err) ...
  3259. *
  3260. * info = calloc(1, item.length);
  3261. * // Now that we allocated the required number of bytes, we call the ioctl
  3262. * // again, this time with the data_ptr pointing to our newly allocated
  3263. * // blob, which the kernel can then populate with the all the region info.
  3264. * item.data_ptr = (uintptr_t)&info,
  3265. *
  3266. * err = ioctl(fd, DRM_IOCTL_I915_QUERY, &query);
  3267. * if (err) ...
  3268. *
  3269. * // We can now access each region in the array
  3270. * for (i = 0; i < info->num_regions; i++) {
  3271. * struct drm_i915_memory_region_info mr = info->regions[i];
  3272. * u16 class = mr.region.class;
  3273. * u16 instance = mr.region.instance;
  3274. *
  3275. * ....
  3276. * }
  3277. *
  3278. * free(info);
  3279. */
  3280. struct drm_i915_query_memory_regions {
  3281. /** @num_regions: Number of supported regions */
  3282. __u32 num_regions;
  3283. /** @rsvd: MBZ */
  3284. __u32 rsvd[3];
  3285. /** @regions: Info about each supported region */
  3286. struct drm_i915_memory_region_info regions[];
  3287. };
  3288. /**
  3289. * struct drm_i915_query_guc_submission_version - query GuC submission interface version
  3290. */
  3291. struct drm_i915_query_guc_submission_version {
  3292. /** @branch: Firmware branch version. */
  3293. __u32 branch;
  3294. /** @major: Firmware major version. */
  3295. __u32 major;
  3296. /** @minor: Firmware minor version. */
  3297. __u32 minor;
  3298. /** @patch: Firmware patch version. */
  3299. __u32 patch;
  3300. };
  3301. /**
  3302. * DOC: GuC HWCONFIG blob uAPI
  3303. *
  3304. * The GuC produces a blob with information about the current device.
  3305. * i915 reads this blob from GuC and makes it available via this uAPI.
  3306. *
  3307. * The format and meaning of the blob content are documented in the
  3308. * Programmer's Reference Manual.
  3309. */
  3310. /**
  3311. * struct drm_i915_gem_create_ext - Existing gem_create behaviour, with added
  3312. * extension support using struct i915_user_extension.
  3313. *
  3314. * Note that new buffer flags should be added here, at least for the stuff that
  3315. * is immutable. Previously we would have two ioctls, one to create the object
  3316. * with gem_create, and another to apply various parameters, however this
  3317. * creates some ambiguity for the params which are considered immutable. Also in
  3318. * general we're phasing out the various SET/GET ioctls.
  3319. */
  3320. struct drm_i915_gem_create_ext {
  3321. /**
  3322. * @size: Requested size for the object.
  3323. *
  3324. * The (page-aligned) allocated size for the object will be returned.
  3325. *
  3326. * On platforms like DG2/ATS the kernel will always use 64K or larger
  3327. * pages for I915_MEMORY_CLASS_DEVICE. The kernel also requires a
  3328. * minimum of 64K GTT alignment for such objects.
  3329. *
  3330. * NOTE: Previously the ABI here required a minimum GTT alignment of 2M
  3331. * on DG2/ATS, due to how the hardware implemented 64K GTT page support,
  3332. * where we had the following complications:
  3333. *
  3334. * 1) The entire PDE (which covers a 2MB virtual address range), must
  3335. * contain only 64K PTEs, i.e mixing 4K and 64K PTEs in the same
  3336. * PDE is forbidden by the hardware.
  3337. *
  3338. * 2) We still need to support 4K PTEs for I915_MEMORY_CLASS_SYSTEM
  3339. * objects.
  3340. *
  3341. * However on actual production HW this was completely changed to now
  3342. * allow setting a TLB hint at the PTE level (see PS64), which is a lot
  3343. * more flexible than the above. With this the 2M restriction was
  3344. * dropped where we now only require 64K.
  3345. */
  3346. __u64 size;
  3347. /**
  3348. * @handle: Returned handle for the object.
  3349. *
  3350. * Object handles are nonzero.
  3351. */
  3352. __u32 handle;
  3353. /**
  3354. * @flags: Optional flags.
  3355. *
  3356. * Supported values:
  3357. *
  3358. * I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS - Signal to the kernel that
  3359. * the object will need to be accessed via the CPU.
  3360. *
  3361. * Only valid when placing objects in I915_MEMORY_CLASS_DEVICE, and only
  3362. * strictly required on configurations where some subset of the device
  3363. * memory is directly visible/mappable through the CPU (which we also
  3364. * call small BAR), like on some DG2+ systems. Note that this is quite
  3365. * undesirable, but due to various factors like the client CPU, BIOS etc
  3366. * it's something we can expect to see in the wild. See
  3367. * &drm_i915_memory_region_info.probed_cpu_visible_size for how to
  3368. * determine if this system applies.
  3369. *
  3370. * Note that one of the placements MUST be I915_MEMORY_CLASS_SYSTEM, to
  3371. * ensure the kernel can always spill the allocation to system memory,
  3372. * if the object can't be allocated in the mappable part of
  3373. * I915_MEMORY_CLASS_DEVICE.
  3374. *
  3375. * Also note that since the kernel only supports flat-CCS on objects
  3376. * that can *only* be placed in I915_MEMORY_CLASS_DEVICE, we therefore
  3377. * don't support I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS together with
  3378. * flat-CCS.
  3379. *
  3380. * Without this hint, the kernel will assume that non-mappable
  3381. * I915_MEMORY_CLASS_DEVICE is preferred for this object. Note that the
  3382. * kernel can still migrate the object to the mappable part, as a last
  3383. * resort, if userspace ever CPU faults this object, but this might be
  3384. * expensive, and so ideally should be avoided.
  3385. *
  3386. * On older kernels which lack the relevant small-bar uAPI support (see
  3387. * also &drm_i915_memory_region_info.probed_cpu_visible_size),
  3388. * usage of the flag will result in an error, but it should NEVER be
  3389. * possible to end up with a small BAR configuration, assuming we can
  3390. * also successfully load the i915 kernel module. In such cases the
  3391. * entire I915_MEMORY_CLASS_DEVICE region will be CPU accessible, and as
  3392. * such there are zero restrictions on where the object can be placed.
  3393. */
  3394. #define I915_GEM_CREATE_EXT_FLAG_NEEDS_CPU_ACCESS (1 << 0)
  3395. __u32 flags;
  3396. /**
  3397. * @extensions: The chain of extensions to apply to this object.
  3398. *
  3399. * This will be useful in the future when we need to support several
  3400. * different extensions, and we need to apply more than one when
  3401. * creating the object. See struct i915_user_extension.
  3402. *
  3403. * If we don't supply any extensions then we get the same old gem_create
  3404. * behaviour.
  3405. *
  3406. * For I915_GEM_CREATE_EXT_MEMORY_REGIONS usage see
  3407. * struct drm_i915_gem_create_ext_memory_regions.
  3408. *
  3409. * For I915_GEM_CREATE_EXT_PROTECTED_CONTENT usage see
  3410. * struct drm_i915_gem_create_ext_protected_content.
  3411. *
  3412. * For I915_GEM_CREATE_EXT_SET_PAT usage see
  3413. * struct drm_i915_gem_create_ext_set_pat.
  3414. */
  3415. #define I915_GEM_CREATE_EXT_MEMORY_REGIONS 0
  3416. #define I915_GEM_CREATE_EXT_PROTECTED_CONTENT 1
  3417. #define I915_GEM_CREATE_EXT_SET_PAT 2
  3418. __u64 extensions;
  3419. };
  3420. /**
  3421. * struct drm_i915_gem_create_ext_memory_regions - The
  3422. * I915_GEM_CREATE_EXT_MEMORY_REGIONS extension.
  3423. *
  3424. * Set the object with the desired set of placements/regions in priority
  3425. * order. Each entry must be unique and supported by the device.
  3426. *
  3427. * This is provided as an array of struct drm_i915_gem_memory_class_instance, or
  3428. * an equivalent layout of class:instance pair encodings. See struct
  3429. * drm_i915_query_memory_regions and DRM_I915_QUERY_MEMORY_REGIONS for how to
  3430. * query the supported regions for a device.
  3431. *
  3432. * As an example, on discrete devices, if we wish to set the placement as
  3433. * device local-memory we can do something like:
  3434. *
  3435. * .. code-block:: C
  3436. *
  3437. * struct drm_i915_gem_memory_class_instance region_lmem = {
  3438. * .memory_class = I915_MEMORY_CLASS_DEVICE,
  3439. * .memory_instance = 0,
  3440. * };
  3441. * struct drm_i915_gem_create_ext_memory_regions regions = {
  3442. * .base = { .name = I915_GEM_CREATE_EXT_MEMORY_REGIONS },
  3443. * .regions = (uintptr_t)&region_lmem,
  3444. * .num_regions = 1,
  3445. * };
  3446. * struct drm_i915_gem_create_ext create_ext = {
  3447. * .size = 16 * PAGE_SIZE,
  3448. * .extensions = (uintptr_t)&regions,
  3449. * };
  3450. *
  3451. * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
  3452. * if (err) ...
  3453. *
  3454. * At which point we get the object handle in &drm_i915_gem_create_ext.handle,
  3455. * along with the final object size in &drm_i915_gem_create_ext.size, which
  3456. * should account for any rounding up, if required.
  3457. *
  3458. * Note that userspace has no means of knowing the current backing region
  3459. * for objects where @num_regions is larger than one. The kernel will only
  3460. * ensure that the priority order of the @regions array is honoured, either
  3461. * when initially placing the object, or when moving memory around due to
  3462. * memory pressure
  3463. *
  3464. * On Flat-CCS capable HW, compression is supported for the objects residing
  3465. * in I915_MEMORY_CLASS_DEVICE. When such objects (compressed) have other
  3466. * memory class in @regions and migrated (by i915, due to memory
  3467. * constraints) to the non I915_MEMORY_CLASS_DEVICE region, then i915 needs to
  3468. * decompress the content. But i915 doesn't have the required information to
  3469. * decompress the userspace compressed objects.
  3470. *
  3471. * So i915 supports Flat-CCS, on the objects which can reside only on
  3472. * I915_MEMORY_CLASS_DEVICE regions.
  3473. */
  3474. struct drm_i915_gem_create_ext_memory_regions {
  3475. /** @base: Extension link. See struct i915_user_extension. */
  3476. struct i915_user_extension base;
  3477. /** @pad: MBZ */
  3478. __u32 pad;
  3479. /** @num_regions: Number of elements in the @regions array. */
  3480. __u32 num_regions;
  3481. /**
  3482. * @regions: The regions/placements array.
  3483. *
  3484. * An array of struct drm_i915_gem_memory_class_instance.
  3485. */
  3486. __u64 regions;
  3487. };
  3488. /**
  3489. * struct drm_i915_gem_create_ext_protected_content - The
  3490. * I915_OBJECT_PARAM_PROTECTED_CONTENT extension.
  3491. *
  3492. * If this extension is provided, buffer contents are expected to be protected
  3493. * by PXP encryption and require decryption for scan out and processing. This
  3494. * is only possible on platforms that have PXP enabled, on all other scenarios
  3495. * using this extension will cause the ioctl to fail and return -ENODEV. The
  3496. * flags parameter is reserved for future expansion and must currently be set
  3497. * to zero.
  3498. *
  3499. * The buffer contents are considered invalid after a PXP session teardown.
  3500. *
  3501. * The encryption is guaranteed to be processed correctly only if the object
  3502. * is submitted with a context created using the
  3503. * I915_CONTEXT_PARAM_PROTECTED_CONTENT flag. This will also enable extra checks
  3504. * at submission time on the validity of the objects involved.
  3505. *
  3506. * Below is an example on how to create a protected object:
  3507. *
  3508. * .. code-block:: C
  3509. *
  3510. * struct drm_i915_gem_create_ext_protected_content protected_ext = {
  3511. * .base = { .name = I915_GEM_CREATE_EXT_PROTECTED_CONTENT },
  3512. * .flags = 0,
  3513. * };
  3514. * struct drm_i915_gem_create_ext create_ext = {
  3515. * .size = PAGE_SIZE,
  3516. * .extensions = (uintptr_t)&protected_ext,
  3517. * };
  3518. *
  3519. * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
  3520. * if (err) ...
  3521. */
  3522. struct drm_i915_gem_create_ext_protected_content {
  3523. /** @base: Extension link. See struct i915_user_extension. */
  3524. struct i915_user_extension base;
  3525. /** @flags: reserved for future usage, currently MBZ */
  3526. __u32 flags;
  3527. };
  3528. /**
  3529. * struct drm_i915_gem_create_ext_set_pat - The
  3530. * I915_GEM_CREATE_EXT_SET_PAT extension.
  3531. *
  3532. * If this extension is provided, the specified caching policy (PAT index) is
  3533. * applied to the buffer object.
  3534. *
  3535. * Below is an example on how to create an object with specific caching policy:
  3536. *
  3537. * .. code-block:: C
  3538. *
  3539. * struct drm_i915_gem_create_ext_set_pat set_pat_ext = {
  3540. * .base = { .name = I915_GEM_CREATE_EXT_SET_PAT },
  3541. * .pat_index = 0,
  3542. * };
  3543. * struct drm_i915_gem_create_ext create_ext = {
  3544. * .size = PAGE_SIZE,
  3545. * .extensions = (uintptr_t)&set_pat_ext,
  3546. * };
  3547. *
  3548. * int err = ioctl(fd, DRM_IOCTL_I915_GEM_CREATE_EXT, &create_ext);
  3549. * if (err) ...
  3550. */
  3551. struct drm_i915_gem_create_ext_set_pat {
  3552. /** @base: Extension link. See struct i915_user_extension. */
  3553. struct i915_user_extension base;
  3554. /**
  3555. * @pat_index: PAT index to be set
  3556. * PAT index is a bit field in Page Table Entry to control caching
  3557. * behaviors for GPU accesses. The definition of PAT index is
  3558. * platform dependent and can be found in hardware specifications,
  3559. */
  3560. __u32 pat_index;
  3561. /** @rsvd: reserved for future use */
  3562. __u32 rsvd;
  3563. };
  3564. /* ID of the protected content session managed by i915 when PXP is active */
  3565. #define I915_PROTECTED_CONTENT_DEFAULT_SESSION 0xf
  3566. #if defined(__cplusplus)
  3567. }
  3568. #endif
  3569. #endif /* _I915_DRM_H_ */