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oasis-root

Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

habanalabs_accel.h (81516B)


  1. /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
  2. *
  3. * Copyright 2016-2023 HabanaLabs, Ltd.
  4. * All Rights Reserved.
  5. *
  6. */
  7. #ifndef HABANALABS_H_
  8. #define HABANALABS_H_
  9. #include <drm/drm.h>
  10. /*
  11. * Defines that are asic-specific but constitutes as ABI between kernel driver
  12. * and userspace
  13. */
  14. #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */
  15. #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */
  16. /*
  17. * 128 SOBs reserved for collective wait
  18. * 16 SOBs reserved for sync stream
  19. */
  20. #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144
  21. /*
  22. * 64 monitors reserved for collective wait
  23. * 8 monitors reserved for sync stream
  24. */
  25. #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72
  26. /* Max number of elements in timestamps registration buffers */
  27. #define TS_MAX_ELEMENTS_NUM (1 << 20) /* 1MB */
  28. /*
  29. * Goya queue Numbering
  30. *
  31. * The external queues (PCI DMA channels) MUST be before the internal queues
  32. * and each group (PCI DMA channels and internal) must be contiguous inside
  33. * itself but there can be a gap between the two groups (although not
  34. * recommended)
  35. */
  36. enum goya_queue_id {
  37. GOYA_QUEUE_ID_DMA_0 = 0,
  38. GOYA_QUEUE_ID_DMA_1 = 1,
  39. GOYA_QUEUE_ID_DMA_2 = 2,
  40. GOYA_QUEUE_ID_DMA_3 = 3,
  41. GOYA_QUEUE_ID_DMA_4 = 4,
  42. GOYA_QUEUE_ID_CPU_PQ = 5,
  43. GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */
  44. GOYA_QUEUE_ID_TPC0 = 7,
  45. GOYA_QUEUE_ID_TPC1 = 8,
  46. GOYA_QUEUE_ID_TPC2 = 9,
  47. GOYA_QUEUE_ID_TPC3 = 10,
  48. GOYA_QUEUE_ID_TPC4 = 11,
  49. GOYA_QUEUE_ID_TPC5 = 12,
  50. GOYA_QUEUE_ID_TPC6 = 13,
  51. GOYA_QUEUE_ID_TPC7 = 14,
  52. GOYA_QUEUE_ID_SIZE
  53. };
  54. /*
  55. * Gaudi queue Numbering
  56. * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*.
  57. * Except one CPU queue, all the rest are internal queues.
  58. */
  59. enum gaudi_queue_id {
  60. GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */
  61. GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */
  62. GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */
  63. GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */
  64. GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */
  65. GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */
  66. GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */
  67. GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */
  68. GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */
  69. GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */
  70. GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */
  71. GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */
  72. GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */
  73. GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */
  74. GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */
  75. GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */
  76. GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */
  77. GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */
  78. GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */
  79. GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */
  80. GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */
  81. GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */
  82. GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */
  83. GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */
  84. GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */
  85. GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */
  86. GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */
  87. GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */
  88. GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */
  89. GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */
  90. GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */
  91. GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */
  92. GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */
  93. GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */
  94. GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */
  95. GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */
  96. GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */
  97. GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */
  98. GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */
  99. GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */
  100. GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */
  101. GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */
  102. GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */
  103. GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */
  104. GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */
  105. GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */
  106. GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */
  107. GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */
  108. GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */
  109. GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */
  110. GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */
  111. GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */
  112. GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */
  113. GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */
  114. GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */
  115. GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */
  116. GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */
  117. GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */
  118. GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */
  119. GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */
  120. GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */
  121. GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */
  122. GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */
  123. GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */
  124. GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */
  125. GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */
  126. GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */
  127. GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */
  128. GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */
  129. GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */
  130. GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */
  131. GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */
  132. GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */
  133. GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */
  134. GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */
  135. GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */
  136. GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */
  137. GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */
  138. GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */
  139. GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */
  140. GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */
  141. GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */
  142. GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */
  143. GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */
  144. GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */
  145. GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */
  146. GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */
  147. GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */
  148. GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */
  149. GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */
  150. GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */
  151. GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */
  152. GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */
  153. GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */
  154. GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */
  155. GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */
  156. GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */
  157. GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */
  158. GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */
  159. GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */
  160. GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */
  161. GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */
  162. GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */
  163. GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */
  164. GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */
  165. GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */
  166. GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */
  167. GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */
  168. GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */
  169. GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */
  170. GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */
  171. GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */
  172. GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */
  173. GAUDI_QUEUE_ID_SIZE
  174. };
  175. /*
  176. * In GAUDI2 we have two modes of operation in regard to queues:
  177. * 1. Legacy mode, where each QMAN exposes 4 streams to the user
  178. * 2. F/W mode, where we use F/W to schedule the JOBS to the different queues.
  179. *
  180. * When in legacy mode, the user sends the queue id per JOB according to
  181. * enum gaudi2_queue_id below.
  182. *
  183. * When in F/W mode, the user sends a stream id per Command Submission. The
  184. * stream id is a running number from 0 up to (N-1), where N is the number
  185. * of streams the F/W exposes and is passed to the user in
  186. * struct hl_info_hw_ip_info
  187. */
  188. enum gaudi2_queue_id {
  189. GAUDI2_QUEUE_ID_PDMA_0_0 = 0,
  190. GAUDI2_QUEUE_ID_PDMA_0_1 = 1,
  191. GAUDI2_QUEUE_ID_PDMA_0_2 = 2,
  192. GAUDI2_QUEUE_ID_PDMA_0_3 = 3,
  193. GAUDI2_QUEUE_ID_PDMA_1_0 = 4,
  194. GAUDI2_QUEUE_ID_PDMA_1_1 = 5,
  195. GAUDI2_QUEUE_ID_PDMA_1_2 = 6,
  196. GAUDI2_QUEUE_ID_PDMA_1_3 = 7,
  197. GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0 = 8,
  198. GAUDI2_QUEUE_ID_DCORE0_EDMA_0_1 = 9,
  199. GAUDI2_QUEUE_ID_DCORE0_EDMA_0_2 = 10,
  200. GAUDI2_QUEUE_ID_DCORE0_EDMA_0_3 = 11,
  201. GAUDI2_QUEUE_ID_DCORE0_EDMA_1_0 = 12,
  202. GAUDI2_QUEUE_ID_DCORE0_EDMA_1_1 = 13,
  203. GAUDI2_QUEUE_ID_DCORE0_EDMA_1_2 = 14,
  204. GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3 = 15,
  205. GAUDI2_QUEUE_ID_DCORE0_MME_0_0 = 16,
  206. GAUDI2_QUEUE_ID_DCORE0_MME_0_1 = 17,
  207. GAUDI2_QUEUE_ID_DCORE0_MME_0_2 = 18,
  208. GAUDI2_QUEUE_ID_DCORE0_MME_0_3 = 19,
  209. GAUDI2_QUEUE_ID_DCORE0_TPC_0_0 = 20,
  210. GAUDI2_QUEUE_ID_DCORE0_TPC_0_1 = 21,
  211. GAUDI2_QUEUE_ID_DCORE0_TPC_0_2 = 22,
  212. GAUDI2_QUEUE_ID_DCORE0_TPC_0_3 = 23,
  213. GAUDI2_QUEUE_ID_DCORE0_TPC_1_0 = 24,
  214. GAUDI2_QUEUE_ID_DCORE0_TPC_1_1 = 25,
  215. GAUDI2_QUEUE_ID_DCORE0_TPC_1_2 = 26,
  216. GAUDI2_QUEUE_ID_DCORE0_TPC_1_3 = 27,
  217. GAUDI2_QUEUE_ID_DCORE0_TPC_2_0 = 28,
  218. GAUDI2_QUEUE_ID_DCORE0_TPC_2_1 = 29,
  219. GAUDI2_QUEUE_ID_DCORE0_TPC_2_2 = 30,
  220. GAUDI2_QUEUE_ID_DCORE0_TPC_2_3 = 31,
  221. GAUDI2_QUEUE_ID_DCORE0_TPC_3_0 = 32,
  222. GAUDI2_QUEUE_ID_DCORE0_TPC_3_1 = 33,
  223. GAUDI2_QUEUE_ID_DCORE0_TPC_3_2 = 34,
  224. GAUDI2_QUEUE_ID_DCORE0_TPC_3_3 = 35,
  225. GAUDI2_QUEUE_ID_DCORE0_TPC_4_0 = 36,
  226. GAUDI2_QUEUE_ID_DCORE0_TPC_4_1 = 37,
  227. GAUDI2_QUEUE_ID_DCORE0_TPC_4_2 = 38,
  228. GAUDI2_QUEUE_ID_DCORE0_TPC_4_3 = 39,
  229. GAUDI2_QUEUE_ID_DCORE0_TPC_5_0 = 40,
  230. GAUDI2_QUEUE_ID_DCORE0_TPC_5_1 = 41,
  231. GAUDI2_QUEUE_ID_DCORE0_TPC_5_2 = 42,
  232. GAUDI2_QUEUE_ID_DCORE0_TPC_5_3 = 43,
  233. GAUDI2_QUEUE_ID_DCORE0_TPC_6_0 = 44,
  234. GAUDI2_QUEUE_ID_DCORE0_TPC_6_1 = 45,
  235. GAUDI2_QUEUE_ID_DCORE0_TPC_6_2 = 46,
  236. GAUDI2_QUEUE_ID_DCORE0_TPC_6_3 = 47,
  237. GAUDI2_QUEUE_ID_DCORE1_EDMA_0_0 = 48,
  238. GAUDI2_QUEUE_ID_DCORE1_EDMA_0_1 = 49,
  239. GAUDI2_QUEUE_ID_DCORE1_EDMA_0_2 = 50,
  240. GAUDI2_QUEUE_ID_DCORE1_EDMA_0_3 = 51,
  241. GAUDI2_QUEUE_ID_DCORE1_EDMA_1_0 = 52,
  242. GAUDI2_QUEUE_ID_DCORE1_EDMA_1_1 = 53,
  243. GAUDI2_QUEUE_ID_DCORE1_EDMA_1_2 = 54,
  244. GAUDI2_QUEUE_ID_DCORE1_EDMA_1_3 = 55,
  245. GAUDI2_QUEUE_ID_DCORE1_MME_0_0 = 56,
  246. GAUDI2_QUEUE_ID_DCORE1_MME_0_1 = 57,
  247. GAUDI2_QUEUE_ID_DCORE1_MME_0_2 = 58,
  248. GAUDI2_QUEUE_ID_DCORE1_MME_0_3 = 59,
  249. GAUDI2_QUEUE_ID_DCORE1_TPC_0_0 = 60,
  250. GAUDI2_QUEUE_ID_DCORE1_TPC_0_1 = 61,
  251. GAUDI2_QUEUE_ID_DCORE1_TPC_0_2 = 62,
  252. GAUDI2_QUEUE_ID_DCORE1_TPC_0_3 = 63,
  253. GAUDI2_QUEUE_ID_DCORE1_TPC_1_0 = 64,
  254. GAUDI2_QUEUE_ID_DCORE1_TPC_1_1 = 65,
  255. GAUDI2_QUEUE_ID_DCORE1_TPC_1_2 = 66,
  256. GAUDI2_QUEUE_ID_DCORE1_TPC_1_3 = 67,
  257. GAUDI2_QUEUE_ID_DCORE1_TPC_2_0 = 68,
  258. GAUDI2_QUEUE_ID_DCORE1_TPC_2_1 = 69,
  259. GAUDI2_QUEUE_ID_DCORE1_TPC_2_2 = 70,
  260. GAUDI2_QUEUE_ID_DCORE1_TPC_2_3 = 71,
  261. GAUDI2_QUEUE_ID_DCORE1_TPC_3_0 = 72,
  262. GAUDI2_QUEUE_ID_DCORE1_TPC_3_1 = 73,
  263. GAUDI2_QUEUE_ID_DCORE1_TPC_3_2 = 74,
  264. GAUDI2_QUEUE_ID_DCORE1_TPC_3_3 = 75,
  265. GAUDI2_QUEUE_ID_DCORE1_TPC_4_0 = 76,
  266. GAUDI2_QUEUE_ID_DCORE1_TPC_4_1 = 77,
  267. GAUDI2_QUEUE_ID_DCORE1_TPC_4_2 = 78,
  268. GAUDI2_QUEUE_ID_DCORE1_TPC_4_3 = 79,
  269. GAUDI2_QUEUE_ID_DCORE1_TPC_5_0 = 80,
  270. GAUDI2_QUEUE_ID_DCORE1_TPC_5_1 = 81,
  271. GAUDI2_QUEUE_ID_DCORE1_TPC_5_2 = 82,
  272. GAUDI2_QUEUE_ID_DCORE1_TPC_5_3 = 83,
  273. GAUDI2_QUEUE_ID_DCORE2_EDMA_0_0 = 84,
  274. GAUDI2_QUEUE_ID_DCORE2_EDMA_0_1 = 85,
  275. GAUDI2_QUEUE_ID_DCORE2_EDMA_0_2 = 86,
  276. GAUDI2_QUEUE_ID_DCORE2_EDMA_0_3 = 87,
  277. GAUDI2_QUEUE_ID_DCORE2_EDMA_1_0 = 88,
  278. GAUDI2_QUEUE_ID_DCORE2_EDMA_1_1 = 89,
  279. GAUDI2_QUEUE_ID_DCORE2_EDMA_1_2 = 90,
  280. GAUDI2_QUEUE_ID_DCORE2_EDMA_1_3 = 91,
  281. GAUDI2_QUEUE_ID_DCORE2_MME_0_0 = 92,
  282. GAUDI2_QUEUE_ID_DCORE2_MME_0_1 = 93,
  283. GAUDI2_QUEUE_ID_DCORE2_MME_0_2 = 94,
  284. GAUDI2_QUEUE_ID_DCORE2_MME_0_3 = 95,
  285. GAUDI2_QUEUE_ID_DCORE2_TPC_0_0 = 96,
  286. GAUDI2_QUEUE_ID_DCORE2_TPC_0_1 = 97,
  287. GAUDI2_QUEUE_ID_DCORE2_TPC_0_2 = 98,
  288. GAUDI2_QUEUE_ID_DCORE2_TPC_0_3 = 99,
  289. GAUDI2_QUEUE_ID_DCORE2_TPC_1_0 = 100,
  290. GAUDI2_QUEUE_ID_DCORE2_TPC_1_1 = 101,
  291. GAUDI2_QUEUE_ID_DCORE2_TPC_1_2 = 102,
  292. GAUDI2_QUEUE_ID_DCORE2_TPC_1_3 = 103,
  293. GAUDI2_QUEUE_ID_DCORE2_TPC_2_0 = 104,
  294. GAUDI2_QUEUE_ID_DCORE2_TPC_2_1 = 105,
  295. GAUDI2_QUEUE_ID_DCORE2_TPC_2_2 = 106,
  296. GAUDI2_QUEUE_ID_DCORE2_TPC_2_3 = 107,
  297. GAUDI2_QUEUE_ID_DCORE2_TPC_3_0 = 108,
  298. GAUDI2_QUEUE_ID_DCORE2_TPC_3_1 = 109,
  299. GAUDI2_QUEUE_ID_DCORE2_TPC_3_2 = 110,
  300. GAUDI2_QUEUE_ID_DCORE2_TPC_3_3 = 111,
  301. GAUDI2_QUEUE_ID_DCORE2_TPC_4_0 = 112,
  302. GAUDI2_QUEUE_ID_DCORE2_TPC_4_1 = 113,
  303. GAUDI2_QUEUE_ID_DCORE2_TPC_4_2 = 114,
  304. GAUDI2_QUEUE_ID_DCORE2_TPC_4_3 = 115,
  305. GAUDI2_QUEUE_ID_DCORE2_TPC_5_0 = 116,
  306. GAUDI2_QUEUE_ID_DCORE2_TPC_5_1 = 117,
  307. GAUDI2_QUEUE_ID_DCORE2_TPC_5_2 = 118,
  308. GAUDI2_QUEUE_ID_DCORE2_TPC_5_3 = 119,
  309. GAUDI2_QUEUE_ID_DCORE3_EDMA_0_0 = 120,
  310. GAUDI2_QUEUE_ID_DCORE3_EDMA_0_1 = 121,
  311. GAUDI2_QUEUE_ID_DCORE3_EDMA_0_2 = 122,
  312. GAUDI2_QUEUE_ID_DCORE3_EDMA_0_3 = 123,
  313. GAUDI2_QUEUE_ID_DCORE3_EDMA_1_0 = 124,
  314. GAUDI2_QUEUE_ID_DCORE3_EDMA_1_1 = 125,
  315. GAUDI2_QUEUE_ID_DCORE3_EDMA_1_2 = 126,
  316. GAUDI2_QUEUE_ID_DCORE3_EDMA_1_3 = 127,
  317. GAUDI2_QUEUE_ID_DCORE3_MME_0_0 = 128,
  318. GAUDI2_QUEUE_ID_DCORE3_MME_0_1 = 129,
  319. GAUDI2_QUEUE_ID_DCORE3_MME_0_2 = 130,
  320. GAUDI2_QUEUE_ID_DCORE3_MME_0_3 = 131,
  321. GAUDI2_QUEUE_ID_DCORE3_TPC_0_0 = 132,
  322. GAUDI2_QUEUE_ID_DCORE3_TPC_0_1 = 133,
  323. GAUDI2_QUEUE_ID_DCORE3_TPC_0_2 = 134,
  324. GAUDI2_QUEUE_ID_DCORE3_TPC_0_3 = 135,
  325. GAUDI2_QUEUE_ID_DCORE3_TPC_1_0 = 136,
  326. GAUDI2_QUEUE_ID_DCORE3_TPC_1_1 = 137,
  327. GAUDI2_QUEUE_ID_DCORE3_TPC_1_2 = 138,
  328. GAUDI2_QUEUE_ID_DCORE3_TPC_1_3 = 139,
  329. GAUDI2_QUEUE_ID_DCORE3_TPC_2_0 = 140,
  330. GAUDI2_QUEUE_ID_DCORE3_TPC_2_1 = 141,
  331. GAUDI2_QUEUE_ID_DCORE3_TPC_2_2 = 142,
  332. GAUDI2_QUEUE_ID_DCORE3_TPC_2_3 = 143,
  333. GAUDI2_QUEUE_ID_DCORE3_TPC_3_0 = 144,
  334. GAUDI2_QUEUE_ID_DCORE3_TPC_3_1 = 145,
  335. GAUDI2_QUEUE_ID_DCORE3_TPC_3_2 = 146,
  336. GAUDI2_QUEUE_ID_DCORE3_TPC_3_3 = 147,
  337. GAUDI2_QUEUE_ID_DCORE3_TPC_4_0 = 148,
  338. GAUDI2_QUEUE_ID_DCORE3_TPC_4_1 = 149,
  339. GAUDI2_QUEUE_ID_DCORE3_TPC_4_2 = 150,
  340. GAUDI2_QUEUE_ID_DCORE3_TPC_4_3 = 151,
  341. GAUDI2_QUEUE_ID_DCORE3_TPC_5_0 = 152,
  342. GAUDI2_QUEUE_ID_DCORE3_TPC_5_1 = 153,
  343. GAUDI2_QUEUE_ID_DCORE3_TPC_5_2 = 154,
  344. GAUDI2_QUEUE_ID_DCORE3_TPC_5_3 = 155,
  345. GAUDI2_QUEUE_ID_NIC_0_0 = 156,
  346. GAUDI2_QUEUE_ID_NIC_0_1 = 157,
  347. GAUDI2_QUEUE_ID_NIC_0_2 = 158,
  348. GAUDI2_QUEUE_ID_NIC_0_3 = 159,
  349. GAUDI2_QUEUE_ID_NIC_1_0 = 160,
  350. GAUDI2_QUEUE_ID_NIC_1_1 = 161,
  351. GAUDI2_QUEUE_ID_NIC_1_2 = 162,
  352. GAUDI2_QUEUE_ID_NIC_1_3 = 163,
  353. GAUDI2_QUEUE_ID_NIC_2_0 = 164,
  354. GAUDI2_QUEUE_ID_NIC_2_1 = 165,
  355. GAUDI2_QUEUE_ID_NIC_2_2 = 166,
  356. GAUDI2_QUEUE_ID_NIC_2_3 = 167,
  357. GAUDI2_QUEUE_ID_NIC_3_0 = 168,
  358. GAUDI2_QUEUE_ID_NIC_3_1 = 169,
  359. GAUDI2_QUEUE_ID_NIC_3_2 = 170,
  360. GAUDI2_QUEUE_ID_NIC_3_3 = 171,
  361. GAUDI2_QUEUE_ID_NIC_4_0 = 172,
  362. GAUDI2_QUEUE_ID_NIC_4_1 = 173,
  363. GAUDI2_QUEUE_ID_NIC_4_2 = 174,
  364. GAUDI2_QUEUE_ID_NIC_4_3 = 175,
  365. GAUDI2_QUEUE_ID_NIC_5_0 = 176,
  366. GAUDI2_QUEUE_ID_NIC_5_1 = 177,
  367. GAUDI2_QUEUE_ID_NIC_5_2 = 178,
  368. GAUDI2_QUEUE_ID_NIC_5_3 = 179,
  369. GAUDI2_QUEUE_ID_NIC_6_0 = 180,
  370. GAUDI2_QUEUE_ID_NIC_6_1 = 181,
  371. GAUDI2_QUEUE_ID_NIC_6_2 = 182,
  372. GAUDI2_QUEUE_ID_NIC_6_3 = 183,
  373. GAUDI2_QUEUE_ID_NIC_7_0 = 184,
  374. GAUDI2_QUEUE_ID_NIC_7_1 = 185,
  375. GAUDI2_QUEUE_ID_NIC_7_2 = 186,
  376. GAUDI2_QUEUE_ID_NIC_7_3 = 187,
  377. GAUDI2_QUEUE_ID_NIC_8_0 = 188,
  378. GAUDI2_QUEUE_ID_NIC_8_1 = 189,
  379. GAUDI2_QUEUE_ID_NIC_8_2 = 190,
  380. GAUDI2_QUEUE_ID_NIC_8_3 = 191,
  381. GAUDI2_QUEUE_ID_NIC_9_0 = 192,
  382. GAUDI2_QUEUE_ID_NIC_9_1 = 193,
  383. GAUDI2_QUEUE_ID_NIC_9_2 = 194,
  384. GAUDI2_QUEUE_ID_NIC_9_3 = 195,
  385. GAUDI2_QUEUE_ID_NIC_10_0 = 196,
  386. GAUDI2_QUEUE_ID_NIC_10_1 = 197,
  387. GAUDI2_QUEUE_ID_NIC_10_2 = 198,
  388. GAUDI2_QUEUE_ID_NIC_10_3 = 199,
  389. GAUDI2_QUEUE_ID_NIC_11_0 = 200,
  390. GAUDI2_QUEUE_ID_NIC_11_1 = 201,
  391. GAUDI2_QUEUE_ID_NIC_11_2 = 202,
  392. GAUDI2_QUEUE_ID_NIC_11_3 = 203,
  393. GAUDI2_QUEUE_ID_NIC_12_0 = 204,
  394. GAUDI2_QUEUE_ID_NIC_12_1 = 205,
  395. GAUDI2_QUEUE_ID_NIC_12_2 = 206,
  396. GAUDI2_QUEUE_ID_NIC_12_3 = 207,
  397. GAUDI2_QUEUE_ID_NIC_13_0 = 208,
  398. GAUDI2_QUEUE_ID_NIC_13_1 = 209,
  399. GAUDI2_QUEUE_ID_NIC_13_2 = 210,
  400. GAUDI2_QUEUE_ID_NIC_13_3 = 211,
  401. GAUDI2_QUEUE_ID_NIC_14_0 = 212,
  402. GAUDI2_QUEUE_ID_NIC_14_1 = 213,
  403. GAUDI2_QUEUE_ID_NIC_14_2 = 214,
  404. GAUDI2_QUEUE_ID_NIC_14_3 = 215,
  405. GAUDI2_QUEUE_ID_NIC_15_0 = 216,
  406. GAUDI2_QUEUE_ID_NIC_15_1 = 217,
  407. GAUDI2_QUEUE_ID_NIC_15_2 = 218,
  408. GAUDI2_QUEUE_ID_NIC_15_3 = 219,
  409. GAUDI2_QUEUE_ID_NIC_16_0 = 220,
  410. GAUDI2_QUEUE_ID_NIC_16_1 = 221,
  411. GAUDI2_QUEUE_ID_NIC_16_2 = 222,
  412. GAUDI2_QUEUE_ID_NIC_16_3 = 223,
  413. GAUDI2_QUEUE_ID_NIC_17_0 = 224,
  414. GAUDI2_QUEUE_ID_NIC_17_1 = 225,
  415. GAUDI2_QUEUE_ID_NIC_17_2 = 226,
  416. GAUDI2_QUEUE_ID_NIC_17_3 = 227,
  417. GAUDI2_QUEUE_ID_NIC_18_0 = 228,
  418. GAUDI2_QUEUE_ID_NIC_18_1 = 229,
  419. GAUDI2_QUEUE_ID_NIC_18_2 = 230,
  420. GAUDI2_QUEUE_ID_NIC_18_3 = 231,
  421. GAUDI2_QUEUE_ID_NIC_19_0 = 232,
  422. GAUDI2_QUEUE_ID_NIC_19_1 = 233,
  423. GAUDI2_QUEUE_ID_NIC_19_2 = 234,
  424. GAUDI2_QUEUE_ID_NIC_19_3 = 235,
  425. GAUDI2_QUEUE_ID_NIC_20_0 = 236,
  426. GAUDI2_QUEUE_ID_NIC_20_1 = 237,
  427. GAUDI2_QUEUE_ID_NIC_20_2 = 238,
  428. GAUDI2_QUEUE_ID_NIC_20_3 = 239,
  429. GAUDI2_QUEUE_ID_NIC_21_0 = 240,
  430. GAUDI2_QUEUE_ID_NIC_21_1 = 241,
  431. GAUDI2_QUEUE_ID_NIC_21_2 = 242,
  432. GAUDI2_QUEUE_ID_NIC_21_3 = 243,
  433. GAUDI2_QUEUE_ID_NIC_22_0 = 244,
  434. GAUDI2_QUEUE_ID_NIC_22_1 = 245,
  435. GAUDI2_QUEUE_ID_NIC_22_2 = 246,
  436. GAUDI2_QUEUE_ID_NIC_22_3 = 247,
  437. GAUDI2_QUEUE_ID_NIC_23_0 = 248,
  438. GAUDI2_QUEUE_ID_NIC_23_1 = 249,
  439. GAUDI2_QUEUE_ID_NIC_23_2 = 250,
  440. GAUDI2_QUEUE_ID_NIC_23_3 = 251,
  441. GAUDI2_QUEUE_ID_ROT_0_0 = 252,
  442. GAUDI2_QUEUE_ID_ROT_0_1 = 253,
  443. GAUDI2_QUEUE_ID_ROT_0_2 = 254,
  444. GAUDI2_QUEUE_ID_ROT_0_3 = 255,
  445. GAUDI2_QUEUE_ID_ROT_1_0 = 256,
  446. GAUDI2_QUEUE_ID_ROT_1_1 = 257,
  447. GAUDI2_QUEUE_ID_ROT_1_2 = 258,
  448. GAUDI2_QUEUE_ID_ROT_1_3 = 259,
  449. GAUDI2_QUEUE_ID_CPU_PQ = 260,
  450. GAUDI2_QUEUE_ID_SIZE
  451. };
  452. /*
  453. * Engine Numbering
  454. *
  455. * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle'
  456. */
  457. enum goya_engine_id {
  458. GOYA_ENGINE_ID_DMA_0 = 0,
  459. GOYA_ENGINE_ID_DMA_1,
  460. GOYA_ENGINE_ID_DMA_2,
  461. GOYA_ENGINE_ID_DMA_3,
  462. GOYA_ENGINE_ID_DMA_4,
  463. GOYA_ENGINE_ID_MME_0,
  464. GOYA_ENGINE_ID_TPC_0,
  465. GOYA_ENGINE_ID_TPC_1,
  466. GOYA_ENGINE_ID_TPC_2,
  467. GOYA_ENGINE_ID_TPC_3,
  468. GOYA_ENGINE_ID_TPC_4,
  469. GOYA_ENGINE_ID_TPC_5,
  470. GOYA_ENGINE_ID_TPC_6,
  471. GOYA_ENGINE_ID_TPC_7,
  472. GOYA_ENGINE_ID_SIZE
  473. };
  474. enum gaudi_engine_id {
  475. GAUDI_ENGINE_ID_DMA_0 = 0,
  476. GAUDI_ENGINE_ID_DMA_1,
  477. GAUDI_ENGINE_ID_DMA_2,
  478. GAUDI_ENGINE_ID_DMA_3,
  479. GAUDI_ENGINE_ID_DMA_4,
  480. GAUDI_ENGINE_ID_DMA_5,
  481. GAUDI_ENGINE_ID_DMA_6,
  482. GAUDI_ENGINE_ID_DMA_7,
  483. GAUDI_ENGINE_ID_MME_0,
  484. GAUDI_ENGINE_ID_MME_1,
  485. GAUDI_ENGINE_ID_MME_2,
  486. GAUDI_ENGINE_ID_MME_3,
  487. GAUDI_ENGINE_ID_TPC_0,
  488. GAUDI_ENGINE_ID_TPC_1,
  489. GAUDI_ENGINE_ID_TPC_2,
  490. GAUDI_ENGINE_ID_TPC_3,
  491. GAUDI_ENGINE_ID_TPC_4,
  492. GAUDI_ENGINE_ID_TPC_5,
  493. GAUDI_ENGINE_ID_TPC_6,
  494. GAUDI_ENGINE_ID_TPC_7,
  495. GAUDI_ENGINE_ID_NIC_0,
  496. GAUDI_ENGINE_ID_NIC_1,
  497. GAUDI_ENGINE_ID_NIC_2,
  498. GAUDI_ENGINE_ID_NIC_3,
  499. GAUDI_ENGINE_ID_NIC_4,
  500. GAUDI_ENGINE_ID_NIC_5,
  501. GAUDI_ENGINE_ID_NIC_6,
  502. GAUDI_ENGINE_ID_NIC_7,
  503. GAUDI_ENGINE_ID_NIC_8,
  504. GAUDI_ENGINE_ID_NIC_9,
  505. GAUDI_ENGINE_ID_SIZE
  506. };
  507. enum gaudi2_engine_id {
  508. GAUDI2_DCORE0_ENGINE_ID_EDMA_0 = 0,
  509. GAUDI2_DCORE0_ENGINE_ID_EDMA_1,
  510. GAUDI2_DCORE0_ENGINE_ID_MME,
  511. GAUDI2_DCORE0_ENGINE_ID_TPC_0,
  512. GAUDI2_DCORE0_ENGINE_ID_TPC_1,
  513. GAUDI2_DCORE0_ENGINE_ID_TPC_2,
  514. GAUDI2_DCORE0_ENGINE_ID_TPC_3,
  515. GAUDI2_DCORE0_ENGINE_ID_TPC_4,
  516. GAUDI2_DCORE0_ENGINE_ID_TPC_5,
  517. GAUDI2_DCORE0_ENGINE_ID_DEC_0,
  518. GAUDI2_DCORE0_ENGINE_ID_DEC_1,
  519. GAUDI2_DCORE1_ENGINE_ID_EDMA_0,
  520. GAUDI2_DCORE1_ENGINE_ID_EDMA_1,
  521. GAUDI2_DCORE1_ENGINE_ID_MME,
  522. GAUDI2_DCORE1_ENGINE_ID_TPC_0,
  523. GAUDI2_DCORE1_ENGINE_ID_TPC_1,
  524. GAUDI2_DCORE1_ENGINE_ID_TPC_2,
  525. GAUDI2_DCORE1_ENGINE_ID_TPC_3,
  526. GAUDI2_DCORE1_ENGINE_ID_TPC_4,
  527. GAUDI2_DCORE1_ENGINE_ID_TPC_5,
  528. GAUDI2_DCORE1_ENGINE_ID_DEC_0,
  529. GAUDI2_DCORE1_ENGINE_ID_DEC_1,
  530. GAUDI2_DCORE2_ENGINE_ID_EDMA_0,
  531. GAUDI2_DCORE2_ENGINE_ID_EDMA_1,
  532. GAUDI2_DCORE2_ENGINE_ID_MME,
  533. GAUDI2_DCORE2_ENGINE_ID_TPC_0,
  534. GAUDI2_DCORE2_ENGINE_ID_TPC_1,
  535. GAUDI2_DCORE2_ENGINE_ID_TPC_2,
  536. GAUDI2_DCORE2_ENGINE_ID_TPC_3,
  537. GAUDI2_DCORE2_ENGINE_ID_TPC_4,
  538. GAUDI2_DCORE2_ENGINE_ID_TPC_5,
  539. GAUDI2_DCORE2_ENGINE_ID_DEC_0,
  540. GAUDI2_DCORE2_ENGINE_ID_DEC_1,
  541. GAUDI2_DCORE3_ENGINE_ID_EDMA_0,
  542. GAUDI2_DCORE3_ENGINE_ID_EDMA_1,
  543. GAUDI2_DCORE3_ENGINE_ID_MME,
  544. GAUDI2_DCORE3_ENGINE_ID_TPC_0,
  545. GAUDI2_DCORE3_ENGINE_ID_TPC_1,
  546. GAUDI2_DCORE3_ENGINE_ID_TPC_2,
  547. GAUDI2_DCORE3_ENGINE_ID_TPC_3,
  548. GAUDI2_DCORE3_ENGINE_ID_TPC_4,
  549. GAUDI2_DCORE3_ENGINE_ID_TPC_5,
  550. GAUDI2_DCORE3_ENGINE_ID_DEC_0,
  551. GAUDI2_DCORE3_ENGINE_ID_DEC_1,
  552. GAUDI2_DCORE0_ENGINE_ID_TPC_6,
  553. GAUDI2_ENGINE_ID_PDMA_0,
  554. GAUDI2_ENGINE_ID_PDMA_1,
  555. GAUDI2_ENGINE_ID_ROT_0,
  556. GAUDI2_ENGINE_ID_ROT_1,
  557. GAUDI2_PCIE_ENGINE_ID_DEC_0,
  558. GAUDI2_PCIE_ENGINE_ID_DEC_1,
  559. GAUDI2_ENGINE_ID_NIC0_0,
  560. GAUDI2_ENGINE_ID_NIC0_1,
  561. GAUDI2_ENGINE_ID_NIC1_0,
  562. GAUDI2_ENGINE_ID_NIC1_1,
  563. GAUDI2_ENGINE_ID_NIC2_0,
  564. GAUDI2_ENGINE_ID_NIC2_1,
  565. GAUDI2_ENGINE_ID_NIC3_0,
  566. GAUDI2_ENGINE_ID_NIC3_1,
  567. GAUDI2_ENGINE_ID_NIC4_0,
  568. GAUDI2_ENGINE_ID_NIC4_1,
  569. GAUDI2_ENGINE_ID_NIC5_0,
  570. GAUDI2_ENGINE_ID_NIC5_1,
  571. GAUDI2_ENGINE_ID_NIC6_0,
  572. GAUDI2_ENGINE_ID_NIC6_1,
  573. GAUDI2_ENGINE_ID_NIC7_0,
  574. GAUDI2_ENGINE_ID_NIC7_1,
  575. GAUDI2_ENGINE_ID_NIC8_0,
  576. GAUDI2_ENGINE_ID_NIC8_1,
  577. GAUDI2_ENGINE_ID_NIC9_0,
  578. GAUDI2_ENGINE_ID_NIC9_1,
  579. GAUDI2_ENGINE_ID_NIC10_0,
  580. GAUDI2_ENGINE_ID_NIC10_1,
  581. GAUDI2_ENGINE_ID_NIC11_0,
  582. GAUDI2_ENGINE_ID_NIC11_1,
  583. GAUDI2_ENGINE_ID_PCIE,
  584. GAUDI2_ENGINE_ID_PSOC,
  585. GAUDI2_ENGINE_ID_ARC_FARM,
  586. GAUDI2_ENGINE_ID_KDMA,
  587. GAUDI2_ENGINE_ID_SIZE
  588. };
  589. /*
  590. * ASIC specific PLL index
  591. *
  592. * Used to retrieve in frequency info of different IPs via HL_INFO_PLL_FREQUENCY under
  593. * DRM_IOCTL_HL_INFO IOCTL.
  594. * The enums need to be used as an index in struct hl_pll_frequency_info.
  595. */
  596. enum hl_goya_pll_index {
  597. HL_GOYA_CPU_PLL = 0,
  598. HL_GOYA_IC_PLL,
  599. HL_GOYA_MC_PLL,
  600. HL_GOYA_MME_PLL,
  601. HL_GOYA_PCI_PLL,
  602. HL_GOYA_EMMC_PLL,
  603. HL_GOYA_TPC_PLL,
  604. HL_GOYA_PLL_MAX
  605. };
  606. enum hl_gaudi_pll_index {
  607. HL_GAUDI_CPU_PLL = 0,
  608. HL_GAUDI_PCI_PLL,
  609. HL_GAUDI_SRAM_PLL,
  610. HL_GAUDI_HBM_PLL,
  611. HL_GAUDI_NIC_PLL,
  612. HL_GAUDI_DMA_PLL,
  613. HL_GAUDI_MESH_PLL,
  614. HL_GAUDI_MME_PLL,
  615. HL_GAUDI_TPC_PLL,
  616. HL_GAUDI_IF_PLL,
  617. HL_GAUDI_PLL_MAX
  618. };
  619. enum hl_gaudi2_pll_index {
  620. HL_GAUDI2_CPU_PLL = 0,
  621. HL_GAUDI2_PCI_PLL,
  622. HL_GAUDI2_SRAM_PLL,
  623. HL_GAUDI2_HBM_PLL,
  624. HL_GAUDI2_NIC_PLL,
  625. HL_GAUDI2_DMA_PLL,
  626. HL_GAUDI2_MESH_PLL,
  627. HL_GAUDI2_MME_PLL,
  628. HL_GAUDI2_TPC_PLL,
  629. HL_GAUDI2_IF_PLL,
  630. HL_GAUDI2_VID_PLL,
  631. HL_GAUDI2_MSS_PLL,
  632. HL_GAUDI2_PLL_MAX
  633. };
  634. /**
  635. * enum hl_goya_dma_direction - Direction of DMA operation inside a LIN_DMA packet that is
  636. * submitted to the GOYA's DMA QMAN. This attribute is not relevant
  637. * to the H/W but the kernel driver use it to parse the packet's
  638. * addresses and patch/validate them.
  639. * @HL_DMA_HOST_TO_DRAM: DMA operation from Host memory to GOYA's DDR.
  640. * @HL_DMA_HOST_TO_SRAM: DMA operation from Host memory to GOYA's SRAM.
  641. * @HL_DMA_DRAM_TO_SRAM: DMA operation from GOYA's DDR to GOYA's SRAM.
  642. * @HL_DMA_SRAM_TO_DRAM: DMA operation from GOYA's SRAM to GOYA's DDR.
  643. * @HL_DMA_SRAM_TO_HOST: DMA operation from GOYA's SRAM to Host memory.
  644. * @HL_DMA_DRAM_TO_HOST: DMA operation from GOYA's DDR to Host memory.
  645. * @HL_DMA_DRAM_TO_DRAM: DMA operation from GOYA's DDR to GOYA's DDR.
  646. * @HL_DMA_SRAM_TO_SRAM: DMA operation from GOYA's SRAM to GOYA's SRAM.
  647. * @HL_DMA_ENUM_MAX: number of values in enum
  648. */
  649. enum hl_goya_dma_direction {
  650. HL_DMA_HOST_TO_DRAM,
  651. HL_DMA_HOST_TO_SRAM,
  652. HL_DMA_DRAM_TO_SRAM,
  653. HL_DMA_SRAM_TO_DRAM,
  654. HL_DMA_SRAM_TO_HOST,
  655. HL_DMA_DRAM_TO_HOST,
  656. HL_DMA_DRAM_TO_DRAM,
  657. HL_DMA_SRAM_TO_SRAM,
  658. HL_DMA_ENUM_MAX
  659. };
  660. /**
  661. * enum hl_device_status - Device status information.
  662. * @HL_DEVICE_STATUS_OPERATIONAL: Device is operational.
  663. * @HL_DEVICE_STATUS_IN_RESET: Device is currently during reset.
  664. * @HL_DEVICE_STATUS_MALFUNCTION: Device is unusable.
  665. * @HL_DEVICE_STATUS_NEEDS_RESET: Device needs reset because auto reset was disabled.
  666. * @HL_DEVICE_STATUS_IN_DEVICE_CREATION: Device is operational but its creation is still in
  667. * progress.
  668. * @HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE: Device is currently during reset that was
  669. * triggered because the user released the device
  670. * @HL_DEVICE_STATUS_LAST: Last status.
  671. */
  672. enum hl_device_status {
  673. HL_DEVICE_STATUS_OPERATIONAL,
  674. HL_DEVICE_STATUS_IN_RESET,
  675. HL_DEVICE_STATUS_MALFUNCTION,
  676. HL_DEVICE_STATUS_NEEDS_RESET,
  677. HL_DEVICE_STATUS_IN_DEVICE_CREATION,
  678. HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE,
  679. HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_RESET_AFTER_DEVICE_RELEASE
  680. };
  681. enum hl_server_type {
  682. HL_SERVER_TYPE_UNKNOWN = 0,
  683. HL_SERVER_GAUDI_HLS1 = 1,
  684. HL_SERVER_GAUDI_HLS1H = 2,
  685. HL_SERVER_GAUDI_TYPE1 = 3,
  686. HL_SERVER_GAUDI_TYPE2 = 4,
  687. HL_SERVER_GAUDI2_HLS2 = 5,
  688. HL_SERVER_GAUDI2_TYPE1 = 7
  689. };
  690. /*
  691. * Notifier event values - for the notification mechanism and the HL_INFO_GET_EVENTS command
  692. *
  693. * HL_NOTIFIER_EVENT_TPC_ASSERT - Indicates TPC assert event
  694. * HL_NOTIFIER_EVENT_UNDEFINED_OPCODE - Indicates undefined operation code
  695. * HL_NOTIFIER_EVENT_DEVICE_RESET - Indicates device requires a reset
  696. * HL_NOTIFIER_EVENT_CS_TIMEOUT - Indicates CS timeout error
  697. * HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE - Indicates device is unavailable
  698. * HL_NOTIFIER_EVENT_USER_ENGINE_ERR - Indicates device engine in error state
  699. * HL_NOTIFIER_EVENT_GENERAL_HW_ERR - Indicates device HW error
  700. * HL_NOTIFIER_EVENT_RAZWI - Indicates razwi happened
  701. * HL_NOTIFIER_EVENT_PAGE_FAULT - Indicates page fault happened
  702. * HL_NOTIFIER_EVENT_CRITICAL_HW_ERR - Indicates a HW error that requires SW abort and
  703. * HW reset
  704. * HL_NOTIFIER_EVENT_CRITICAL_FW_ERR - Indicates a FW error that requires SW abort and
  705. * HW reset
  706. */
  707. #define HL_NOTIFIER_EVENT_TPC_ASSERT (1ULL << 0)
  708. #define HL_NOTIFIER_EVENT_UNDEFINED_OPCODE (1ULL << 1)
  709. #define HL_NOTIFIER_EVENT_DEVICE_RESET (1ULL << 2)
  710. #define HL_NOTIFIER_EVENT_CS_TIMEOUT (1ULL << 3)
  711. #define HL_NOTIFIER_EVENT_DEVICE_UNAVAILABLE (1ULL << 4)
  712. #define HL_NOTIFIER_EVENT_USER_ENGINE_ERR (1ULL << 5)
  713. #define HL_NOTIFIER_EVENT_GENERAL_HW_ERR (1ULL << 6)
  714. #define HL_NOTIFIER_EVENT_RAZWI (1ULL << 7)
  715. #define HL_NOTIFIER_EVENT_PAGE_FAULT (1ULL << 8)
  716. #define HL_NOTIFIER_EVENT_CRITICL_HW_ERR (1ULL << 9)
  717. #define HL_NOTIFIER_EVENT_CRITICL_FW_ERR (1ULL << 10)
  718. /* Opcode for management ioctl
  719. *
  720. * HW_IP_INFO - Receive information about different IP blocks in the
  721. * device.
  722. * HL_INFO_HW_EVENTS - Receive an array describing how many times each event
  723. * occurred since the last hard reset.
  724. * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the
  725. * specific context. This is relevant only for devices
  726. * where the dram is managed by the kernel driver
  727. * HL_INFO_HW_IDLE - Retrieve information about the idle status of each
  728. * internal engine.
  729. * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't
  730. * require an open context.
  731. * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device
  732. * over the last period specified by the user.
  733. * The period can be between 100ms to 1s, in
  734. * resolution of 100ms. The return value is a
  735. * percentage of the utilization rate.
  736. * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each
  737. * event occurred since the driver was loaded.
  738. * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate
  739. * of the device in MHz. The maximum clock rate is
  740. * configurable via sysfs parameter
  741. * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset
  742. * operations performed on the device since the last
  743. * time the driver was loaded.
  744. * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time
  745. * for synchronization.
  746. * HL_INFO_CS_COUNTERS - Retrieve command submission counters
  747. * HL_INFO_PCI_COUNTERS - Retrieve PCI counters
  748. * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason
  749. * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore
  750. * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption
  751. * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency
  752. * HL_INFO_POWER - Retrieve power information
  753. * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls
  754. * HL_INFO_DRAM_REPLACED_ROWS - Retrieve DRAM replaced rows info
  755. * HL_INFO_DRAM_PENDING_ROWS - Retrieve DRAM pending rows num
  756. * HL_INFO_LAST_ERR_OPEN_DEV_TIME - Retrieve timestamp of the last time the device was opened
  757. * and CS timeout or razwi error occurred.
  758. * HL_INFO_CS_TIMEOUT_EVENT - Retrieve CS timeout timestamp and its related CS sequence number.
  759. * HL_INFO_RAZWI_EVENT - Retrieve parameters of razwi:
  760. * Timestamp of razwi.
  761. * The address which accessing it caused the razwi.
  762. * Razwi initiator.
  763. * Razwi cause, was it a page fault or MMU access error.
  764. * May return 0 even though no new data is available, in that case
  765. * timestamp will be 0.
  766. * HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES - Retrieve valid page sizes for device memory allocation
  767. * HL_INFO_SECURED_ATTESTATION - Retrieve attestation report of the boot.
  768. * HL_INFO_REGISTER_EVENTFD - Register eventfd for event notifications.
  769. * HL_INFO_UNREGISTER_EVENTFD - Unregister eventfd
  770. * HL_INFO_GET_EVENTS - Retrieve the last occurred events
  771. * HL_INFO_UNDEFINED_OPCODE_EVENT - Retrieve last undefined opcode error information.
  772. * May return 0 even though no new data is available, in that case
  773. * timestamp will be 0.
  774. * HL_INFO_ENGINE_STATUS - Retrieve the status of all the h/w engines in the asic.
  775. * HL_INFO_PAGE_FAULT_EVENT - Retrieve parameters of captured page fault.
  776. * May return 0 even though no new data is available, in that case
  777. * timestamp will be 0.
  778. * HL_INFO_USER_MAPPINGS - Retrieve user mappings, captured after page fault event.
  779. * HL_INFO_FW_GENERIC_REQ - Send generic request to FW.
  780. * HL_INFO_HW_ERR_EVENT - Retrieve information on the reported HW error.
  781. * May return 0 even though no new data is available, in that case
  782. * timestamp will be 0.
  783. * HL_INFO_FW_ERR_EVENT - Retrieve information on the reported FW error.
  784. * May return 0 even though no new data is available, in that case
  785. * timestamp will be 0.
  786. * HL_INFO_USER_ENGINE_ERR_EVENT - Retrieve the last engine id that reported an error.
  787. */
  788. #define HL_INFO_HW_IP_INFO 0
  789. #define HL_INFO_HW_EVENTS 1
  790. #define HL_INFO_DRAM_USAGE 2
  791. #define HL_INFO_HW_IDLE 3
  792. #define HL_INFO_DEVICE_STATUS 4
  793. #define HL_INFO_DEVICE_UTILIZATION 6
  794. #define HL_INFO_HW_EVENTS_AGGREGATE 7
  795. #define HL_INFO_CLK_RATE 8
  796. #define HL_INFO_RESET_COUNT 9
  797. #define HL_INFO_TIME_SYNC 10
  798. #define HL_INFO_CS_COUNTERS 11
  799. #define HL_INFO_PCI_COUNTERS 12
  800. #define HL_INFO_CLK_THROTTLE_REASON 13
  801. #define HL_INFO_SYNC_MANAGER 14
  802. #define HL_INFO_TOTAL_ENERGY 15
  803. #define HL_INFO_PLL_FREQUENCY 16
  804. #define HL_INFO_POWER 17
  805. #define HL_INFO_OPEN_STATS 18
  806. #define HL_INFO_DRAM_REPLACED_ROWS 21
  807. #define HL_INFO_DRAM_PENDING_ROWS 22
  808. #define HL_INFO_LAST_ERR_OPEN_DEV_TIME 23
  809. #define HL_INFO_CS_TIMEOUT_EVENT 24
  810. #define HL_INFO_RAZWI_EVENT 25
  811. #define HL_INFO_DEV_MEM_ALLOC_PAGE_SIZES 26
  812. #define HL_INFO_SECURED_ATTESTATION 27
  813. #define HL_INFO_REGISTER_EVENTFD 28
  814. #define HL_INFO_UNREGISTER_EVENTFD 29
  815. #define HL_INFO_GET_EVENTS 30
  816. #define HL_INFO_UNDEFINED_OPCODE_EVENT 31
  817. #define HL_INFO_ENGINE_STATUS 32
  818. #define HL_INFO_PAGE_FAULT_EVENT 33
  819. #define HL_INFO_USER_MAPPINGS 34
  820. #define HL_INFO_FW_GENERIC_REQ 35
  821. #define HL_INFO_HW_ERR_EVENT 36
  822. #define HL_INFO_FW_ERR_EVENT 37
  823. #define HL_INFO_USER_ENGINE_ERR_EVENT 38
  824. #define HL_INFO_DEV_SIGNED 40
  825. #define HL_INFO_VERSION_MAX_LEN 128
  826. #define HL_INFO_CARD_NAME_MAX_LEN 16
  827. /* Maximum buffer size for retrieving engines status */
  828. #define HL_ENGINES_DATA_MAX_SIZE SZ_1M
  829. /**
  830. * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC
  831. * @sram_base_address: The first SRAM physical base address that is free to be
  832. * used by the user.
  833. * @dram_base_address: The first DRAM virtual or physical base address that is
  834. * free to be used by the user.
  835. * @dram_size: The DRAM size that is available to the user.
  836. * @sram_size: The SRAM size that is available to the user.
  837. * @num_of_events: The number of events that can be received from the f/w. This
  838. * is needed so the user can what is the size of the h/w events
  839. * array he needs to pass to the kernel when he wants to fetch
  840. * the event counters.
  841. * @device_id: PCI device ID of the ASIC.
  842. * @module_id: Module ID of the ASIC for mezzanine cards in servers
  843. * (From OCP spec).
  844. * @decoder_enabled_mask: Bit-mask that represents which decoders are enabled.
  845. * @first_available_interrupt_id: The first available interrupt ID for the user
  846. * to be used when it works with user interrupts.
  847. * Relevant for Gaudi2 and later.
  848. * @server_type: Server type that the Gaudi ASIC is currently installed in.
  849. * The value is according to enum hl_server_type
  850. * @cpld_version: CPLD version on the board.
  851. * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs.
  852. * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs.
  853. * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs.
  854. * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler
  855. * in some ASICs.
  856. * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant
  857. * for Goya/Gaudi only.
  858. * @dram_enabled: Whether the DRAM is enabled.
  859. * @security_enabled: Whether security is enabled on device.
  860. * @mme_master_slave_mode: Indicate whether the MME is working in master/slave
  861. * configuration. Relevant for Gaudi2 and later.
  862. * @cpucp_version: The CPUCP f/w version.
  863. * @card_name: The card name as passed by the f/w.
  864. * @tpc_enabled_mask_ext: Bit-mask that represents which TPCs are enabled.
  865. * Relevant for Gaudi2 and later.
  866. * @dram_page_size: The DRAM physical page size.
  867. * @edma_enabled_mask: Bit-mask that represents which EDMAs are enabled.
  868. * Relevant for Gaudi2 and later.
  869. * @number_of_user_interrupts: The number of interrupts that are available to the userspace
  870. * application to use. Relevant for Gaudi2 and later.
  871. * @device_mem_alloc_default_page_size: default page size used in device memory allocation.
  872. * @revision_id: PCI revision ID of the ASIC.
  873. * @tpc_interrupt_id: interrupt id for TPC to use in order to raise events towards the host.
  874. * @rotator_enabled_mask: Bit-mask that represents which rotators are enabled.
  875. * Relevant for Gaudi3 and later.
  876. * @engine_core_interrupt_reg_addr: interrupt register address for engine core to use
  877. * in order to raise events toward FW.
  878. * @reserved_dram_size: DRAM size reserved for driver and firmware.
  879. */
  880. struct hl_info_hw_ip_info {
  881. __u64 sram_base_address;
  882. __u64 dram_base_address;
  883. __u64 dram_size;
  884. __u32 sram_size;
  885. __u32 num_of_events;
  886. __u32 device_id;
  887. __u32 module_id;
  888. __u32 decoder_enabled_mask;
  889. __u16 first_available_interrupt_id;
  890. __u16 server_type;
  891. __u32 cpld_version;
  892. __u32 psoc_pci_pll_nr;
  893. __u32 psoc_pci_pll_nf;
  894. __u32 psoc_pci_pll_od;
  895. __u32 psoc_pci_pll_div_factor;
  896. __u8 tpc_enabled_mask;
  897. __u8 dram_enabled;
  898. __u8 security_enabled;
  899. __u8 mme_master_slave_mode;
  900. __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN];
  901. __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN];
  902. __u64 tpc_enabled_mask_ext;
  903. __u64 dram_page_size;
  904. __u32 edma_enabled_mask;
  905. __u16 number_of_user_interrupts;
  906. __u8 reserved1;
  907. __u8 reserved2;
  908. __u64 reserved3;
  909. __u64 device_mem_alloc_default_page_size;
  910. __u64 reserved4;
  911. __u64 reserved5;
  912. __u32 reserved6;
  913. __u8 reserved7;
  914. __u8 revision_id;
  915. __u16 tpc_interrupt_id;
  916. __u32 rotator_enabled_mask;
  917. __u32 reserved9;
  918. __u64 engine_core_interrupt_reg_addr;
  919. __u64 reserved_dram_size;
  920. };
  921. struct hl_info_dram_usage {
  922. __u64 dram_free_mem;
  923. __u64 ctx_dram_mem;
  924. };
  925. #define HL_BUSY_ENGINES_MASK_EXT_SIZE 4
  926. struct hl_info_hw_idle {
  927. __u32 is_idle;
  928. /*
  929. * Bitmask of busy engines.
  930. * Bits definition is according to `enum <chip>_engine_id'.
  931. */
  932. __u32 busy_engines_mask;
  933. /*
  934. * Extended Bitmask of busy engines.
  935. * Bits definition is according to `enum <chip>_engine_id'.
  936. */
  937. __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE];
  938. };
  939. struct hl_info_device_status {
  940. __u32 status;
  941. __u32 pad;
  942. };
  943. struct hl_info_device_utilization {
  944. __u32 utilization;
  945. __u32 pad;
  946. };
  947. struct hl_info_clk_rate {
  948. __u32 cur_clk_rate_mhz;
  949. __u32 max_clk_rate_mhz;
  950. };
  951. struct hl_info_reset_count {
  952. __u32 hard_reset_cnt;
  953. __u32 soft_reset_cnt;
  954. };
  955. struct hl_info_time_sync {
  956. __u64 device_time;
  957. __u64 host_time;
  958. __u64 tsc_time;
  959. };
  960. /**
  961. * struct hl_info_pci_counters - pci counters
  962. * @rx_throughput: PCI rx throughput KBps
  963. * @tx_throughput: PCI tx throughput KBps
  964. * @replay_cnt: PCI replay counter
  965. */
  966. struct hl_info_pci_counters {
  967. __u64 rx_throughput;
  968. __u64 tx_throughput;
  969. __u64 replay_cnt;
  970. };
  971. enum hl_clk_throttling_type {
  972. HL_CLK_THROTTLE_TYPE_POWER,
  973. HL_CLK_THROTTLE_TYPE_THERMAL,
  974. HL_CLK_THROTTLE_TYPE_MAX
  975. };
  976. /* clk_throttling_reason masks */
  977. #define HL_CLK_THROTTLE_POWER (1 << HL_CLK_THROTTLE_TYPE_POWER)
  978. #define HL_CLK_THROTTLE_THERMAL (1 << HL_CLK_THROTTLE_TYPE_THERMAL)
  979. /**
  980. * struct hl_info_clk_throttle - clock throttling reason
  981. * @clk_throttling_reason: each bit represents a clk throttling reason
  982. * @clk_throttling_timestamp_us: represents CPU timestamp in microseconds of the start-event
  983. * @clk_throttling_duration_ns: the clock throttle time in nanosec
  984. */
  985. struct hl_info_clk_throttle {
  986. __u32 clk_throttling_reason;
  987. __u32 pad;
  988. __u64 clk_throttling_timestamp_us[HL_CLK_THROTTLE_TYPE_MAX];
  989. __u64 clk_throttling_duration_ns[HL_CLK_THROTTLE_TYPE_MAX];
  990. };
  991. /**
  992. * struct hl_info_energy - device energy information
  993. * @total_energy_consumption: total device energy consumption
  994. */
  995. struct hl_info_energy {
  996. __u64 total_energy_consumption;
  997. };
  998. #define HL_PLL_NUM_OUTPUTS 4
  999. struct hl_pll_frequency_info {
  1000. __u16 output[HL_PLL_NUM_OUTPUTS];
  1001. };
  1002. /**
  1003. * struct hl_open_stats_info - device open statistics information
  1004. * @open_counter: ever growing counter, increased on each successful dev open
  1005. * @last_open_period_ms: duration (ms) device was open last time
  1006. * @is_compute_ctx_active: Whether there is an active compute context executing
  1007. * @compute_ctx_in_release: true if the current compute context is being released
  1008. */
  1009. struct hl_open_stats_info {
  1010. __u64 open_counter;
  1011. __u64 last_open_period_ms;
  1012. __u8 is_compute_ctx_active;
  1013. __u8 compute_ctx_in_release;
  1014. __u8 pad[6];
  1015. };
  1016. /**
  1017. * struct hl_power_info - power information
  1018. * @power: power consumption
  1019. */
  1020. struct hl_power_info {
  1021. __u64 power;
  1022. };
  1023. /**
  1024. * struct hl_info_sync_manager - sync manager information
  1025. * @first_available_sync_object: first available sob
  1026. * @first_available_monitor: first available monitor
  1027. * @first_available_cq: first available cq
  1028. */
  1029. struct hl_info_sync_manager {
  1030. __u32 first_available_sync_object;
  1031. __u32 first_available_monitor;
  1032. __u32 first_available_cq;
  1033. __u32 reserved;
  1034. };
  1035. /**
  1036. * struct hl_info_cs_counters - command submission counters
  1037. * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue
  1038. * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue
  1039. * @total_parsing_drop_cnt: total dropped due to error in packet parsing
  1040. * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing
  1041. * @total_queue_full_drop_cnt: total dropped due to queue full
  1042. * @ctx_queue_full_drop_cnt: context dropped due to queue full
  1043. * @total_device_in_reset_drop_cnt: total dropped due to device in reset
  1044. * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset
  1045. * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight
  1046. * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight
  1047. * @total_validation_drop_cnt: total dropped due to validation error
  1048. * @ctx_validation_drop_cnt: context dropped due to validation error
  1049. */
  1050. struct hl_info_cs_counters {
  1051. __u64 total_out_of_mem_drop_cnt;
  1052. __u64 ctx_out_of_mem_drop_cnt;
  1053. __u64 total_parsing_drop_cnt;
  1054. __u64 ctx_parsing_drop_cnt;
  1055. __u64 total_queue_full_drop_cnt;
  1056. __u64 ctx_queue_full_drop_cnt;
  1057. __u64 total_device_in_reset_drop_cnt;
  1058. __u64 ctx_device_in_reset_drop_cnt;
  1059. __u64 total_max_cs_in_flight_drop_cnt;
  1060. __u64 ctx_max_cs_in_flight_drop_cnt;
  1061. __u64 total_validation_drop_cnt;
  1062. __u64 ctx_validation_drop_cnt;
  1063. };
  1064. /**
  1065. * struct hl_info_last_err_open_dev_time - last error boot information.
  1066. * @timestamp: timestamp of last time the device was opened and error occurred.
  1067. */
  1068. struct hl_info_last_err_open_dev_time {
  1069. __s64 timestamp;
  1070. };
  1071. /**
  1072. * struct hl_info_cs_timeout_event - last CS timeout information.
  1073. * @timestamp: timestamp when last CS timeout event occurred.
  1074. * @seq: sequence number of last CS timeout event.
  1075. */
  1076. struct hl_info_cs_timeout_event {
  1077. __s64 timestamp;
  1078. __u64 seq;
  1079. };
  1080. #define HL_RAZWI_NA_ENG_ID U16_MAX
  1081. #define HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR 128
  1082. #define HL_RAZWI_READ BIT(0)
  1083. #define HL_RAZWI_WRITE BIT(1)
  1084. #define HL_RAZWI_LBW BIT(2)
  1085. #define HL_RAZWI_HBW BIT(3)
  1086. #define HL_RAZWI_RR BIT(4)
  1087. #define HL_RAZWI_ADDR_DEC BIT(5)
  1088. /**
  1089. * struct hl_info_razwi_event - razwi information.
  1090. * @timestamp: timestamp of razwi.
  1091. * @addr: address which accessing it caused razwi.
  1092. * @engine_id: engine id of the razwi initiator, if it was initiated by engine that does not
  1093. * have engine id it will be set to HL_RAZWI_NA_ENG_ID. If there are several possible
  1094. * engines which caused the razwi, it will hold all of them.
  1095. * @num_of_possible_engines: contains number of possible engine ids. In some asics, razwi indication
  1096. * might be common for several engines and there is no way to get the
  1097. * exact engine. In this way, engine_id array will be filled with all
  1098. * possible engines caused this razwi. Also, there might be possibility
  1099. * in gaudi, where we don't indication on specific engine, in that case
  1100. * the value of this parameter will be zero.
  1101. * @flags: bitmask for additional data: HL_RAZWI_READ - razwi caused by read operation
  1102. * HL_RAZWI_WRITE - razwi caused by write operation
  1103. * HL_RAZWI_LBW - razwi caused by lbw fabric transaction
  1104. * HL_RAZWI_HBW - razwi caused by hbw fabric transaction
  1105. * HL_RAZWI_RR - razwi caused by range register
  1106. * HL_RAZWI_ADDR_DEC - razwi caused by address decode error
  1107. * Note: this data is not supported by all asics, in that case the relevant bits will not
  1108. * be set.
  1109. */
  1110. struct hl_info_razwi_event {
  1111. __s64 timestamp;
  1112. __u64 addr;
  1113. __u16 engine_id[HL_RAZWI_MAX_NUM_OF_ENGINES_PER_RTR];
  1114. __u16 num_of_possible_engines;
  1115. __u8 flags;
  1116. __u8 pad[5];
  1117. };
  1118. #define MAX_QMAN_STREAMS_INFO 4
  1119. #define OPCODE_INFO_MAX_ADDR_SIZE 8
  1120. /**
  1121. * struct hl_info_undefined_opcode_event - info about last undefined opcode error
  1122. * @timestamp: timestamp of the undefined opcode error
  1123. * @cb_addr_streams: CB addresses (per stream) that are currently exists in the PQ
  1124. * entries. In case all streams array entries are
  1125. * filled with values, it means the execution was in Lower-CP.
  1126. * @cq_addr: the address of the current handled command buffer
  1127. * @cq_size: the size of the current handled command buffer
  1128. * @cb_addr_streams_len: num of streams - actual len of cb_addr_streams array.
  1129. * should be equal to 1 in case of undefined opcode
  1130. * in Upper-CP (specific stream) and equal to 4 incase
  1131. * of undefined opcode in Lower-CP.
  1132. * @engine_id: engine-id that the error occurred on
  1133. * @stream_id: the stream id the error occurred on. In case the stream equals to
  1134. * MAX_QMAN_STREAMS_INFO it means the error occurred on a Lower-CP.
  1135. */
  1136. struct hl_info_undefined_opcode_event {
  1137. __s64 timestamp;
  1138. __u64 cb_addr_streams[MAX_QMAN_STREAMS_INFO][OPCODE_INFO_MAX_ADDR_SIZE];
  1139. __u64 cq_addr;
  1140. __u32 cq_size;
  1141. __u32 cb_addr_streams_len;
  1142. __u32 engine_id;
  1143. __u32 stream_id;
  1144. };
  1145. /**
  1146. * struct hl_info_hw_err_event - info about HW error
  1147. * @timestamp: timestamp of error occurrence
  1148. * @event_id: The async event ID (specific to each device type).
  1149. * @pad: size padding for u64 granularity.
  1150. */
  1151. struct hl_info_hw_err_event {
  1152. __s64 timestamp;
  1153. __u16 event_id;
  1154. __u16 pad[3];
  1155. };
  1156. /* FW error definition for event_type in struct hl_info_fw_err_event */
  1157. enum hl_info_fw_err_type {
  1158. HL_INFO_FW_HEARTBEAT_ERR,
  1159. HL_INFO_FW_REPORTED_ERR,
  1160. };
  1161. /**
  1162. * struct hl_info_fw_err_event - info about FW error
  1163. * @timestamp: time-stamp of error occurrence
  1164. * @err_type: The type of event as defined in hl_info_fw_err_type.
  1165. * @event_id: The async event ID (specific to each device type, applicable only when event type is
  1166. * HL_INFO_FW_REPORTED_ERR).
  1167. * @pad: size padding for u64 granularity.
  1168. */
  1169. struct hl_info_fw_err_event {
  1170. __s64 timestamp;
  1171. __u16 err_type;
  1172. __u16 event_id;
  1173. __u32 pad;
  1174. };
  1175. /**
  1176. * struct hl_info_engine_err_event - engine error info
  1177. * @timestamp: time-stamp of error occurrence
  1178. * @engine_id: engine id who reported the error.
  1179. * @error_count: Amount of errors reported.
  1180. * @pad: size padding for u64 granularity.
  1181. */
  1182. struct hl_info_engine_err_event {
  1183. __s64 timestamp;
  1184. __u16 engine_id;
  1185. __u16 error_count;
  1186. __u32 pad;
  1187. };
  1188. /**
  1189. * struct hl_info_dev_memalloc_page_sizes - valid page sizes in device mem alloc information.
  1190. * @page_order_bitmask: bitmap in which a set bit represents the order of the supported page size
  1191. * (e.g. 0x2100000 means that 1MB and 32MB pages are supported).
  1192. */
  1193. struct hl_info_dev_memalloc_page_sizes {
  1194. __u64 page_order_bitmask;
  1195. };
  1196. #define SEC_PCR_DATA_BUF_SZ 256
  1197. #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */
  1198. #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */
  1199. #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */
  1200. #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */
  1201. #define SEC_DEV_INFO_BUF_SZ 5120
  1202. /*
  1203. * struct hl_info_sec_attest - attestation report of the boot
  1204. * @nonce: number only used once. random number provided by host. this also passed to the quote
  1205. * command as a qualifying data.
  1206. * @pcr_quote_len: length of the attestation quote data (bytes)
  1207. * @pub_data_len: length of the public data (bytes)
  1208. * @certificate_len: length of the certificate (bytes)
  1209. * @pcr_num_reg: number of PCR registers in the pcr_data array
  1210. * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes)
  1211. * @quote_sig_len: length of the attestation report signature (bytes)
  1212. * @pcr_data: raw values of the PCR registers
  1213. * @pcr_quote: attestation report data structure
  1214. * @quote_sig: signature structure of the attestation report
  1215. * @public_data: public key for the signed attestation
  1216. * (outPublic + name + qualifiedName)
  1217. * @certificate: certificate for the attestation signing key
  1218. */
  1219. struct hl_info_sec_attest {
  1220. __u32 nonce;
  1221. __u16 pcr_quote_len;
  1222. __u16 pub_data_len;
  1223. __u16 certificate_len;
  1224. __u8 pcr_num_reg;
  1225. __u8 pcr_reg_len;
  1226. __u8 quote_sig_len;
  1227. __u8 pcr_data[SEC_PCR_DATA_BUF_SZ];
  1228. __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ];
  1229. __u8 quote_sig[SEC_SIGNATURE_BUF_SZ];
  1230. __u8 public_data[SEC_PUB_DATA_BUF_SZ];
  1231. __u8 certificate[SEC_CERTIFICATE_BUF_SZ];
  1232. __u8 pad0[2];
  1233. };
  1234. /*
  1235. * struct hl_info_signed - device information signed by a secured device.
  1236. * @nonce: number only used once. random number provided by host. this also passed to the quote
  1237. * command as a qualifying data.
  1238. * @pub_data_len: length of the public data (bytes)
  1239. * @certificate_len: length of the certificate (bytes)
  1240. * @info_sig_len: length of the attestation signature (bytes)
  1241. * @public_data: public key info signed info data (outPublic + name + qualifiedName)
  1242. * @certificate: certificate for the signing key
  1243. * @info_sig: signature of the info + nonce data.
  1244. * @dev_info_len: length of device info (bytes)
  1245. * @dev_info: device info as byte array.
  1246. */
  1247. struct hl_info_signed {
  1248. __u32 nonce;
  1249. __u16 pub_data_len;
  1250. __u16 certificate_len;
  1251. __u8 info_sig_len;
  1252. __u8 public_data[SEC_PUB_DATA_BUF_SZ];
  1253. __u8 certificate[SEC_CERTIFICATE_BUF_SZ];
  1254. __u8 info_sig[SEC_SIGNATURE_BUF_SZ];
  1255. __u16 dev_info_len;
  1256. __u8 dev_info[SEC_DEV_INFO_BUF_SZ];
  1257. __u8 pad[2];
  1258. };
  1259. /**
  1260. * struct hl_page_fault_info - page fault information.
  1261. * @timestamp: timestamp of page fault.
  1262. * @addr: address which accessing it caused page fault.
  1263. * @engine_id: engine id which caused the page fault, supported only in gaudi3.
  1264. */
  1265. struct hl_page_fault_info {
  1266. __s64 timestamp;
  1267. __u64 addr;
  1268. __u16 engine_id;
  1269. __u8 pad[6];
  1270. };
  1271. /**
  1272. * struct hl_user_mapping - user mapping information.
  1273. * @dev_va: device virtual address.
  1274. * @size: virtual address mapping size.
  1275. */
  1276. struct hl_user_mapping {
  1277. __u64 dev_va;
  1278. __u64 size;
  1279. };
  1280. enum gaudi_dcores {
  1281. HL_GAUDI_WS_DCORE,
  1282. HL_GAUDI_WN_DCORE,
  1283. HL_GAUDI_EN_DCORE,
  1284. HL_GAUDI_ES_DCORE
  1285. };
  1286. /**
  1287. * struct hl_info_args - Main structure to retrieve device related information.
  1288. * @return_pointer: User space address of the relevant structure related to HL_INFO_* operation
  1289. * mentioned in @op.
  1290. * @return_size: Size of the structure used in @return_pointer, just like "size" in "snprintf", it
  1291. * limits how many bytes the kernel can write. For hw_events array, the size should be
  1292. * hl_info_hw_ip_info.num_of_events * sizeof(__u32).
  1293. * @op: Defines which type of information to be retrieved. Refer HL_INFO_* for details.
  1294. * @dcore_id: DCORE id for which the information is relevant (for Gaudi refer to enum gaudi_dcores).
  1295. * @ctx_id: Context ID of the user. Currently not in use.
  1296. * @period_ms: Period value, in milliseconds, for utilization rate in range 100ms - 1000ms in 100 ms
  1297. * resolution. Currently not in use.
  1298. * @pll_index: Index as defined in hl_<asic type>_pll_index enumeration.
  1299. * @eventfd: event file descriptor for event notifications.
  1300. * @user_buffer_actual_size: Actual data size which was copied to user allocated buffer by the
  1301. * driver. It is possible for the user to allocate buffer larger than
  1302. * needed, hence updating this variable so user will know the exact amount
  1303. * of bytes copied by the kernel to the buffer.
  1304. * @sec_attest_nonce: Nonce number used for attestation report.
  1305. * @array_size: Number of array members copied to user buffer.
  1306. * Relevant for HL_INFO_USER_MAPPINGS info ioctl.
  1307. * @fw_sub_opcode: generic requests sub opcodes.
  1308. * @pad: Padding to 64 bit.
  1309. */
  1310. struct hl_info_args {
  1311. __u64 return_pointer;
  1312. __u32 return_size;
  1313. __u32 op;
  1314. union {
  1315. __u32 dcore_id;
  1316. __u32 ctx_id;
  1317. __u32 period_ms;
  1318. __u32 pll_index;
  1319. __u32 eventfd;
  1320. __u32 user_buffer_actual_size;
  1321. __u32 sec_attest_nonce;
  1322. __u32 array_size;
  1323. __u32 fw_sub_opcode;
  1324. };
  1325. __u32 pad;
  1326. };
  1327. /* Opcode to create a new command buffer */
  1328. #define HL_CB_OP_CREATE 0
  1329. /* Opcode to destroy previously created command buffer */
  1330. #define HL_CB_OP_DESTROY 1
  1331. /* Opcode to retrieve information about a command buffer */
  1332. #define HL_CB_OP_INFO 2
  1333. /* 2MB minus 32 bytes for 2xMSG_PROT */
  1334. #define HL_MAX_CB_SIZE (0x200000 - 32)
  1335. /* Indicates whether the command buffer should be mapped to the device's MMU */
  1336. #define HL_CB_FLAGS_MAP 0x1
  1337. /* Used with HL_CB_OP_INFO opcode to get the device va address for kernel mapped CB */
  1338. #define HL_CB_FLAGS_GET_DEVICE_VA 0x2
  1339. struct hl_cb_in {
  1340. /* Handle of CB or 0 if we want to create one */
  1341. __u64 cb_handle;
  1342. /* HL_CB_OP_* */
  1343. __u32 op;
  1344. /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that
  1345. * will be allocated, regardless of this parameter's value, is PAGE_SIZE
  1346. */
  1347. __u32 cb_size;
  1348. /* Context ID - Currently not in use */
  1349. __u32 ctx_id;
  1350. /* HL_CB_FLAGS_* */
  1351. __u32 flags;
  1352. };
  1353. struct hl_cb_out {
  1354. union {
  1355. /* Handle of CB */
  1356. __u64 cb_handle;
  1357. union {
  1358. /* Information about CB */
  1359. struct {
  1360. /* Usage count of CB */
  1361. __u32 usage_cnt;
  1362. __u32 pad;
  1363. };
  1364. /* CB mapped address to device MMU */
  1365. __u64 device_va;
  1366. };
  1367. };
  1368. };
  1369. union hl_cb_args {
  1370. struct hl_cb_in in;
  1371. struct hl_cb_out out;
  1372. };
  1373. /* HL_CS_CHUNK_FLAGS_ values
  1374. *
  1375. * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB:
  1376. * Indicates if the CB was allocated and mapped by userspace
  1377. * (relevant to Gaudi2 and later). User allocated CB is a command buffer,
  1378. * allocated by the user, via malloc (or similar). After allocating the
  1379. * CB, the user invokes - “memory ioctl” to map the user memory into a
  1380. * device virtual address. The user provides this address via the
  1381. * cb_handle field. The interface provides the ability to create a
  1382. * large CBs, Which aren’t limited to “HL_MAX_CB_SIZE”. Therefore, it
  1383. * increases the PCI-DMA queues throughput. This CB allocation method
  1384. * also reduces the use of Linux DMA-able memory pool. Which are limited
  1385. * and used by other Linux sub-systems.
  1386. */
  1387. #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1
  1388. /*
  1389. * This structure size must always be fixed to 64-bytes for backward
  1390. * compatibility
  1391. */
  1392. struct hl_cs_chunk {
  1393. union {
  1394. /* Goya/Gaudi:
  1395. * For external queue, this represents a Handle of CB on the
  1396. * Host.
  1397. * For internal queue in Goya, this represents an SRAM or
  1398. * a DRAM address of the internal CB. In Gaudi, this might also
  1399. * represent a mapped host address of the CB.
  1400. *
  1401. * Gaudi2 onwards:
  1402. * For H/W queue, this represents either a Handle of CB on the
  1403. * Host, or an SRAM, a DRAM, or a mapped host address of the CB.
  1404. *
  1405. * A mapped host address is in the device address space, after
  1406. * a host address was mapped by the device MMU.
  1407. */
  1408. __u64 cb_handle;
  1409. /* Relevant only when HL_CS_FLAGS_WAIT or
  1410. * HL_CS_FLAGS_COLLECTIVE_WAIT is set
  1411. * This holds address of array of u64 values that contain
  1412. * signal CS sequence numbers. The wait described by
  1413. * this job will listen on all those signals
  1414. * (wait event per signal)
  1415. */
  1416. __u64 signal_seq_arr;
  1417. /*
  1418. * Relevant only when HL_CS_FLAGS_WAIT or
  1419. * HL_CS_FLAGS_COLLECTIVE_WAIT is set
  1420. * along with HL_CS_FLAGS_ENCAP_SIGNALS.
  1421. * This is the CS sequence which has the encapsulated signals.
  1422. */
  1423. __u64 encaps_signal_seq;
  1424. };
  1425. /* Index of queue to put the CB on */
  1426. __u32 queue_index;
  1427. union {
  1428. /*
  1429. * Size of command buffer with valid packets
  1430. * Can be smaller then actual CB size
  1431. */
  1432. __u32 cb_size;
  1433. /* Relevant only when HL_CS_FLAGS_WAIT or
  1434. * HL_CS_FLAGS_COLLECTIVE_WAIT is set.
  1435. * Number of entries in signal_seq_arr
  1436. */
  1437. __u32 num_signal_seq_arr;
  1438. /* Relevant only when HL_CS_FLAGS_WAIT or
  1439. * HL_CS_FLAGS_COLLECTIVE_WAIT is set along
  1440. * with HL_CS_FLAGS_ENCAP_SIGNALS
  1441. * This set the signals range that the user want to wait for
  1442. * out of the whole reserved signals range.
  1443. * e.g if the signals range is 20, and user don't want
  1444. * to wait for signal 8, so he set this offset to 7, then
  1445. * he call the API again with 9 and so on till 20.
  1446. */
  1447. __u32 encaps_signal_offset;
  1448. };
  1449. /* HL_CS_CHUNK_FLAGS_* */
  1450. __u32 cs_chunk_flags;
  1451. /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set.
  1452. * This holds the collective engine ID. The wait described by this job
  1453. * will sync with this engine and with all NICs before completion.
  1454. */
  1455. __u32 collective_engine_id;
  1456. /* Align structure to 64 bytes */
  1457. __u32 pad[10];
  1458. };
  1459. /* SIGNAL/WAIT/COLLECTIVE_WAIT flags are mutually exclusive */
  1460. #define HL_CS_FLAGS_FORCE_RESTORE 0x1
  1461. #define HL_CS_FLAGS_SIGNAL 0x2
  1462. #define HL_CS_FLAGS_WAIT 0x4
  1463. #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8
  1464. #define HL_CS_FLAGS_TIMESTAMP 0x20
  1465. #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40
  1466. #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80
  1467. #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100
  1468. #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200
  1469. #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400
  1470. /*
  1471. * The encapsulated signals CS is merged into the existing CS ioctls.
  1472. * In order to use this feature need to follow the below procedure:
  1473. * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY
  1474. * the output of this API will be the SOB offset from CFG_BASE.
  1475. * this address will be used to patch CB cmds to do the signaling for this
  1476. * SOB by incrementing it's value.
  1477. * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY
  1478. * CS type, note that this might fail if out-of-sync happened to the SOB
  1479. * value, in case other signaling request to the same SOB occurred between
  1480. * reserve-unreserve calls.
  1481. * 2. Use the staged CS to do the encapsulated signaling jobs.
  1482. * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
  1483. * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset
  1484. * field. This offset allows app to wait on part of the reserved signals.
  1485. * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag
  1486. * to wait for the encapsulated signals.
  1487. */
  1488. #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800
  1489. #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000
  1490. #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000
  1491. /*
  1492. * The engine cores CS is merged into the existing CS ioctls.
  1493. * Use it to control the engine cores mode.
  1494. */
  1495. #define HL_CS_FLAGS_ENGINE_CORE_COMMAND 0x4000
  1496. /*
  1497. * The flush HBW PCI writes is merged into the existing CS ioctls.
  1498. * Used to flush all HBW PCI writes.
  1499. * This is a blocking operation and for this reason the user shall not use
  1500. * the return sequence number (which will be invalid anyway)
  1501. */
  1502. #define HL_CS_FLAGS_FLUSH_PCI_HBW_WRITES 0x8000
  1503. /*
  1504. * The engines CS is merged into the existing CS ioctls.
  1505. * Use it to control engines modes.
  1506. */
  1507. #define HL_CS_FLAGS_ENGINES_COMMAND 0x10000
  1508. #define HL_CS_STATUS_SUCCESS 0
  1509. #define HL_MAX_JOBS_PER_CS 512
  1510. /*
  1511. * enum hl_engine_command - engine command
  1512. *
  1513. * @HL_ENGINE_CORE_HALT: engine core halt
  1514. * @HL_ENGINE_CORE_RUN: engine core run
  1515. * @HL_ENGINE_STALL: user engine/s stall
  1516. * @HL_ENGINE_RESUME: user engine/s resume
  1517. */
  1518. enum hl_engine_command {
  1519. HL_ENGINE_CORE_HALT = 1,
  1520. HL_ENGINE_CORE_RUN = 2,
  1521. HL_ENGINE_STALL = 3,
  1522. HL_ENGINE_RESUME = 4,
  1523. HL_ENGINE_COMMAND_MAX
  1524. };
  1525. struct hl_cs_in {
  1526. union {
  1527. struct {
  1528. /* this holds address of array of hl_cs_chunk for restore phase */
  1529. __u64 chunks_restore;
  1530. /* holds address of array of hl_cs_chunk for execution phase */
  1531. __u64 chunks_execute;
  1532. };
  1533. /* Valid only when HL_CS_FLAGS_ENGINE_CORE_COMMAND is set */
  1534. struct {
  1535. /* this holds address of array of uint32 for engine_cores */
  1536. __u64 engine_cores;
  1537. /* number of engine cores in engine_cores array */
  1538. __u32 num_engine_cores;
  1539. /* the core command to be sent towards engine cores */
  1540. __u32 core_command;
  1541. };
  1542. /* Valid only when HL_CS_FLAGS_ENGINES_COMMAND is set */
  1543. struct {
  1544. /* this holds address of array of uint32 for engines */
  1545. __u64 engines;
  1546. /* number of engines in engines array */
  1547. __u32 num_engines;
  1548. /* the engine command to be sent towards engines */
  1549. __u32 engine_command;
  1550. };
  1551. };
  1552. union {
  1553. /*
  1554. * Sequence number of a staged submission CS
  1555. * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and
  1556. * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset.
  1557. */
  1558. __u64 seq;
  1559. /*
  1560. * Encapsulated signals handle id
  1561. * Valid for two flows:
  1562. * 1. CS with encapsulated signals:
  1563. * when HL_CS_FLAGS_STAGED_SUBMISSION and
  1564. * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST
  1565. * and HL_CS_FLAGS_ENCAP_SIGNALS are set.
  1566. * 2. unreserve signals:
  1567. * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set.
  1568. */
  1569. __u32 encaps_sig_handle_id;
  1570. /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
  1571. struct {
  1572. /* Encapsulated signals number */
  1573. __u32 encaps_signals_count;
  1574. /* Encapsulated signals queue index (stream) */
  1575. __u32 encaps_signals_q_idx;
  1576. };
  1577. };
  1578. /* Number of chunks in restore phase array. Maximum number is
  1579. * HL_MAX_JOBS_PER_CS
  1580. */
  1581. __u32 num_chunks_restore;
  1582. /* Number of chunks in execution array. Maximum number is
  1583. * HL_MAX_JOBS_PER_CS
  1584. */
  1585. __u32 num_chunks_execute;
  1586. /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT
  1587. * is set
  1588. */
  1589. __u32 timeout;
  1590. /* HL_CS_FLAGS_* */
  1591. __u32 cs_flags;
  1592. /* Context ID - Currently not in use */
  1593. __u32 ctx_id;
  1594. __u8 pad[4];
  1595. };
  1596. struct hl_cs_out {
  1597. union {
  1598. /*
  1599. * seq holds the sequence number of the CS to pass to wait
  1600. * ioctl. All values are valid except for 0 and ULLONG_MAX
  1601. */
  1602. __u64 seq;
  1603. /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */
  1604. struct {
  1605. /* This is the reserved signal handle id */
  1606. __u32 handle_id;
  1607. /* This is the signals count */
  1608. __u32 count;
  1609. };
  1610. };
  1611. /* HL_CS_STATUS */
  1612. __u32 status;
  1613. /*
  1614. * SOB base address offset
  1615. * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY or HL_CS_FLAGS_SIGNAL is set
  1616. */
  1617. __u32 sob_base_addr_offset;
  1618. /*
  1619. * Count of completed signals in SOB before current signal submission.
  1620. * Valid only when (HL_CS_FLAGS_ENCAP_SIGNALS & HL_CS_FLAGS_STAGED_SUBMISSION)
  1621. * or HL_CS_FLAGS_SIGNAL is set
  1622. */
  1623. __u16 sob_count_before_submission;
  1624. __u16 pad[3];
  1625. };
  1626. union hl_cs_args {
  1627. struct hl_cs_in in;
  1628. struct hl_cs_out out;
  1629. };
  1630. #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2
  1631. #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000
  1632. #define HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT 0xFFF00000
  1633. #define HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT 0xFFE00000
  1634. #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4
  1635. #define HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ 0x10
  1636. #define HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT 0x20
  1637. #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32
  1638. struct hl_wait_cs_in {
  1639. union {
  1640. struct {
  1641. /*
  1642. * In case of wait_cs holds the CS sequence number.
  1643. * In case of wait for multi CS hold a user pointer to
  1644. * an array of CS sequence numbers
  1645. */
  1646. __u64 seq;
  1647. /* Absolute timeout to wait for command submission
  1648. * in microseconds
  1649. */
  1650. __u64 timeout_us;
  1651. };
  1652. struct {
  1653. union {
  1654. /* User address for completion comparison.
  1655. * upon interrupt, driver will compare the value pointed
  1656. * by this address with the supplied target value.
  1657. * in order not to perform any comparison, set address
  1658. * to all 1s.
  1659. * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
  1660. */
  1661. __u64 addr;
  1662. /* cq_counters_handle to a kernel mapped cb which contains
  1663. * cq counters.
  1664. * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
  1665. */
  1666. __u64 cq_counters_handle;
  1667. };
  1668. /* Target value for completion comparison */
  1669. __u64 target;
  1670. };
  1671. };
  1672. /* Context ID - Currently not in use */
  1673. __u32 ctx_id;
  1674. /* HL_WAIT_CS_FLAGS_*
  1675. * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include
  1676. * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK
  1677. *
  1678. * in order to wait for any CQ interrupt, set interrupt value to
  1679. * HL_WAIT_CS_FLAGS_ANY_CQ_INTERRUPT.
  1680. *
  1681. * in order to wait for any decoder interrupt, set interrupt value to
  1682. * HL_WAIT_CS_FLAGS_ANY_DEC_INTERRUPT.
  1683. */
  1684. __u32 flags;
  1685. union {
  1686. struct {
  1687. /* Multi CS API info- valid entries in multi-CS array */
  1688. __u8 seq_arr_len;
  1689. __u8 pad[7];
  1690. };
  1691. /* Absolute timeout to wait for an interrupt in microseconds.
  1692. * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set
  1693. */
  1694. __u64 interrupt_timeout_us;
  1695. };
  1696. /*
  1697. * cq counter offset inside the counters cb pointed by cq_counters_handle above.
  1698. * upon interrupt, driver will compare the value pointed
  1699. * by this address (cq_counters_handle + cq_counters_offset)
  1700. * with the supplied target value.
  1701. * relevant only when HL_WAIT_CS_FLAGS_INTERRUPT_KERNEL_CQ is set
  1702. */
  1703. __u64 cq_counters_offset;
  1704. /*
  1705. * Timestamp_handle timestamps buffer handle.
  1706. * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set
  1707. */
  1708. __u64 timestamp_handle;
  1709. /*
  1710. * Timestamp_offset is offset inside the timestamp buffer pointed by timestamp_handle above.
  1711. * upon interrupt, if the cq reached the target value then driver will write
  1712. * timestamp to this offset.
  1713. * relevant only when HL_WAIT_CS_FLAGS_REGISTER_INTERRUPT is set
  1714. */
  1715. __u64 timestamp_offset;
  1716. };
  1717. #define HL_WAIT_CS_STATUS_COMPLETED 0
  1718. #define HL_WAIT_CS_STATUS_BUSY 1
  1719. #define HL_WAIT_CS_STATUS_TIMEDOUT 2
  1720. #define HL_WAIT_CS_STATUS_ABORTED 3
  1721. #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1
  1722. #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2
  1723. struct hl_wait_cs_out {
  1724. /* HL_WAIT_CS_STATUS_* */
  1725. __u32 status;
  1726. /* HL_WAIT_CS_STATUS_FLAG* */
  1727. __u32 flags;
  1728. /*
  1729. * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set
  1730. * for wait_cs: timestamp of CS completion
  1731. * for wait_multi_cs: timestamp of FIRST CS completion
  1732. */
  1733. __s64 timestamp_nsec;
  1734. /* multi CS completion bitmap */
  1735. __u32 cs_completion_map;
  1736. __u32 pad;
  1737. };
  1738. union hl_wait_cs_args {
  1739. struct hl_wait_cs_in in;
  1740. struct hl_wait_cs_out out;
  1741. };
  1742. /* Opcode to allocate device memory */
  1743. #define HL_MEM_OP_ALLOC 0
  1744. /* Opcode to free previously allocated device memory */
  1745. #define HL_MEM_OP_FREE 1
  1746. /* Opcode to map host and device memory */
  1747. #define HL_MEM_OP_MAP 2
  1748. /* Opcode to unmap previously mapped host and device memory */
  1749. #define HL_MEM_OP_UNMAP 3
  1750. /* Opcode to map a hw block */
  1751. #define HL_MEM_OP_MAP_BLOCK 4
  1752. /* Opcode to create DMA-BUF object for an existing device memory allocation
  1753. * and to export an FD of that DMA-BUF back to the caller
  1754. */
  1755. #define HL_MEM_OP_EXPORT_DMABUF_FD 5
  1756. /* Opcode to create timestamps pool for user interrupts registration support
  1757. * The memory will be allocated by the kernel driver, A timestamp buffer which the user
  1758. * will get handle to it for mmap, and another internal buffer used by the
  1759. * driver for registration management
  1760. * The memory will be freed when the user closes the file descriptor(ctx close)
  1761. */
  1762. #define HL_MEM_OP_TS_ALLOC 6
  1763. /* Memory flags */
  1764. #define HL_MEM_CONTIGUOUS 0x1
  1765. #define HL_MEM_SHARED 0x2
  1766. #define HL_MEM_USERPTR 0x4
  1767. #define HL_MEM_FORCE_HINT 0x8
  1768. #define HL_MEM_PREFETCH 0x40
  1769. /**
  1770. * structure hl_mem_in - structure that handle input args for memory IOCTL
  1771. * @union arg: union of structures to be used based on the input operation
  1772. * @op: specify the requested memory operation (one of the HL_MEM_OP_* definitions).
  1773. * @flags: flags for the memory operation (one of the HL_MEM_* definitions).
  1774. * For the HL_MEM_OP_EXPORT_DMABUF_FD opcode, this field holds the DMA-BUF file/FD flags.
  1775. * @ctx_id: context ID - currently not in use.
  1776. * @num_of_elements: number of timestamp elements used only with HL_MEM_OP_TS_ALLOC opcode.
  1777. */
  1778. struct hl_mem_in {
  1779. union {
  1780. /**
  1781. * structure for device memory allocation (used with the HL_MEM_OP_ALLOC op)
  1782. * @mem_size: memory size to allocate
  1783. * @page_size: page size to use on allocation. when the value is 0 the default page
  1784. * size will be taken.
  1785. */
  1786. struct {
  1787. __u64 mem_size;
  1788. __u64 page_size;
  1789. } alloc;
  1790. /**
  1791. * structure for free-ing device memory (used with the HL_MEM_OP_FREE op)
  1792. * @handle: handle returned from HL_MEM_OP_ALLOC
  1793. */
  1794. struct {
  1795. __u64 handle;
  1796. } free;
  1797. /**
  1798. * structure for mapping device memory (used with the HL_MEM_OP_MAP op)
  1799. * @hint_addr: requested virtual address of mapped memory.
  1800. * the driver will try to map the requested region to this hint
  1801. * address, as long as the address is valid and not already mapped.
  1802. * the user should check the returned address of the IOCTL to make
  1803. * sure he got the hint address.
  1804. * passing 0 here means that the driver will choose the address itself.
  1805. * @handle: handle returned from HL_MEM_OP_ALLOC.
  1806. */
  1807. struct {
  1808. __u64 hint_addr;
  1809. __u64 handle;
  1810. } map_device;
  1811. /**
  1812. * structure for mapping host memory (used with the HL_MEM_OP_MAP op)
  1813. * @host_virt_addr: address of allocated host memory.
  1814. * @hint_addr: requested virtual address of mapped memory.
  1815. * the driver will try to map the requested region to this hint
  1816. * address, as long as the address is valid and not already mapped.
  1817. * the user should check the returned address of the IOCTL to make
  1818. * sure he got the hint address.
  1819. * passing 0 here means that the driver will choose the address itself.
  1820. * @size: size of allocated host memory.
  1821. */
  1822. struct {
  1823. __u64 host_virt_addr;
  1824. __u64 hint_addr;
  1825. __u64 mem_size;
  1826. } map_host;
  1827. /**
  1828. * structure for mapping hw block (used with the HL_MEM_OP_MAP_BLOCK op)
  1829. * @block_addr:HW block address to map, a handle and size will be returned
  1830. * to the user and will be used to mmap the relevant block.
  1831. * only addresses from configuration space are allowed.
  1832. */
  1833. struct {
  1834. __u64 block_addr;
  1835. } map_block;
  1836. /**
  1837. * structure for unmapping host memory (used with the HL_MEM_OP_UNMAP op)
  1838. * @device_virt_addr: virtual address returned from HL_MEM_OP_MAP
  1839. */
  1840. struct {
  1841. __u64 device_virt_addr;
  1842. } unmap;
  1843. /**
  1844. * structure for exporting DMABUF object (used with
  1845. * the HL_MEM_OP_EXPORT_DMABUF_FD op)
  1846. * @addr: for Gaudi1, the driver expects a physical address
  1847. * inside the device's DRAM. this is because in Gaudi1
  1848. * we don't have MMU that covers the device's DRAM.
  1849. * for all other ASICs, the driver expects a device
  1850. * virtual address that represents the start address of
  1851. * a mapped DRAM memory area inside the device.
  1852. * the address must be the same as was received from the
  1853. * driver during a previous HL_MEM_OP_MAP operation.
  1854. * @mem_size: size of memory to export.
  1855. * @offset: for Gaudi1, this value must be 0. For all other ASICs,
  1856. * the driver expects an offset inside of the memory area
  1857. * describe by addr. the offset represents the start
  1858. * address of that the exported dma-buf object describes.
  1859. */
  1860. struct {
  1861. __u64 addr;
  1862. __u64 mem_size;
  1863. __u64 offset;
  1864. } export_dmabuf_fd;
  1865. };
  1866. __u32 op;
  1867. __u32 flags;
  1868. __u32 ctx_id;
  1869. __u32 num_of_elements;
  1870. };
  1871. struct hl_mem_out {
  1872. union {
  1873. /*
  1874. * Used for HL_MEM_OP_MAP as the virtual address that was
  1875. * assigned in the device VA space.
  1876. * A value of 0 means the requested operation failed.
  1877. */
  1878. __u64 device_virt_addr;
  1879. /*
  1880. * Used in HL_MEM_OP_ALLOC
  1881. * This is the assigned handle for the allocated memory
  1882. */
  1883. __u64 handle;
  1884. struct {
  1885. /*
  1886. * Used in HL_MEM_OP_MAP_BLOCK.
  1887. * This is the assigned handle for the mapped block
  1888. */
  1889. __u64 block_handle;
  1890. /*
  1891. * Used in HL_MEM_OP_MAP_BLOCK
  1892. * This is the size of the mapped block
  1893. */
  1894. __u32 block_size;
  1895. __u32 pad;
  1896. };
  1897. /* Returned in HL_MEM_OP_EXPORT_DMABUF_FD. Represents the
  1898. * DMA-BUF object that was created to describe a memory
  1899. * allocation on the device's memory space. The FD should be
  1900. * passed to the importer driver
  1901. */
  1902. __s32 fd;
  1903. };
  1904. };
  1905. union hl_mem_args {
  1906. struct hl_mem_in in;
  1907. struct hl_mem_out out;
  1908. };
  1909. #define HL_DEBUG_MAX_AUX_VALUES 10
  1910. struct hl_debug_params_etr {
  1911. /* Address in memory to allocate buffer */
  1912. __u64 buffer_address;
  1913. /* Size of buffer to allocate */
  1914. __u64 buffer_size;
  1915. /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
  1916. __u32 sink_mode;
  1917. __u32 pad;
  1918. };
  1919. struct hl_debug_params_etf {
  1920. /* Address in memory to allocate buffer */
  1921. __u64 buffer_address;
  1922. /* Size of buffer to allocate */
  1923. __u64 buffer_size;
  1924. /* Sink operation mode: SW fifo, HW fifo, Circular buffer */
  1925. __u32 sink_mode;
  1926. __u32 pad;
  1927. };
  1928. struct hl_debug_params_stm {
  1929. /* Two bit masks for HW event and Stimulus Port */
  1930. __u64 he_mask;
  1931. __u64 sp_mask;
  1932. /* Trace source ID */
  1933. __u32 id;
  1934. /* Frequency for the timestamp register */
  1935. __u32 frequency;
  1936. };
  1937. struct hl_debug_params_bmon {
  1938. /* Two address ranges that the user can request to filter */
  1939. __u64 start_addr0;
  1940. __u64 addr_mask0;
  1941. __u64 start_addr1;
  1942. __u64 addr_mask1;
  1943. /* Capture window configuration */
  1944. __u32 bw_win;
  1945. __u32 win_capture;
  1946. /* Trace source ID */
  1947. __u32 id;
  1948. /* Control register */
  1949. __u32 control;
  1950. /* Two more address ranges that the user can request to filter */
  1951. __u64 start_addr2;
  1952. __u64 end_addr2;
  1953. __u64 start_addr3;
  1954. __u64 end_addr3;
  1955. };
  1956. struct hl_debug_params_spmu {
  1957. /* Event types selection */
  1958. __u64 event_types[HL_DEBUG_MAX_AUX_VALUES];
  1959. /* Number of event types selection */
  1960. __u32 event_types_num;
  1961. /* TRC configuration register values */
  1962. __u32 pmtrc_val;
  1963. __u32 trc_ctrl_host_val;
  1964. __u32 trc_en_host_val;
  1965. };
  1966. /* Opcode for ETR component */
  1967. #define HL_DEBUG_OP_ETR 0
  1968. /* Opcode for ETF component */
  1969. #define HL_DEBUG_OP_ETF 1
  1970. /* Opcode for STM component */
  1971. #define HL_DEBUG_OP_STM 2
  1972. /* Opcode for FUNNEL component */
  1973. #define HL_DEBUG_OP_FUNNEL 3
  1974. /* Opcode for BMON component */
  1975. #define HL_DEBUG_OP_BMON 4
  1976. /* Opcode for SPMU component */
  1977. #define HL_DEBUG_OP_SPMU 5
  1978. /* Opcode for timestamp (deprecated) */
  1979. #define HL_DEBUG_OP_TIMESTAMP 6
  1980. /* Opcode for setting the device into or out of debug mode. The enable
  1981. * variable should be 1 for enabling debug mode and 0 for disabling it
  1982. */
  1983. #define HL_DEBUG_OP_SET_MODE 7
  1984. struct hl_debug_args {
  1985. /*
  1986. * Pointer to user input structure.
  1987. * This field is relevant to specific opcodes.
  1988. */
  1989. __u64 input_ptr;
  1990. /* Pointer to user output structure */
  1991. __u64 output_ptr;
  1992. /* Size of user input structure */
  1993. __u32 input_size;
  1994. /* Size of user output structure */
  1995. __u32 output_size;
  1996. /* HL_DEBUG_OP_* */
  1997. __u32 op;
  1998. /*
  1999. * Register index in the component, taken from the debug_regs_index enum
  2000. * in the various ASIC header files
  2001. */
  2002. __u32 reg_idx;
  2003. /* Enable/disable */
  2004. __u32 enable;
  2005. /* Context ID - Currently not in use */
  2006. __u32 ctx_id;
  2007. };
  2008. #define HL_IOCTL_INFO 0x00
  2009. #define HL_IOCTL_CB 0x01
  2010. #define HL_IOCTL_CS 0x02
  2011. #define HL_IOCTL_WAIT_CS 0x03
  2012. #define HL_IOCTL_MEMORY 0x04
  2013. #define HL_IOCTL_DEBUG 0x05
  2014. /*
  2015. * Various information operations such as:
  2016. * - H/W IP information
  2017. * - Current dram usage
  2018. *
  2019. * The user calls this IOCTL with an opcode that describes the required
  2020. * information. The user should supply a pointer to a user-allocated memory
  2021. * chunk, which will be filled by the driver with the requested information.
  2022. *
  2023. * The user supplies the maximum amount of size to copy into the user's memory,
  2024. * in order to prevent data corruption in case of differences between the
  2025. * definitions of structures in kernel and userspace, e.g. in case of old
  2026. * userspace and new kernel driver
  2027. */
  2028. #define DRM_IOCTL_HL_INFO DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_INFO, struct hl_info_args)
  2029. /*
  2030. * Command Buffer
  2031. * - Request a Command Buffer
  2032. * - Destroy a Command Buffer
  2033. *
  2034. * The command buffers are memory blocks that reside in DMA-able address
  2035. * space and are physically contiguous so they can be accessed by the device
  2036. * directly. They are allocated using the coherent DMA API.
  2037. *
  2038. * When creating a new CB, the IOCTL returns a handle of it, and the user-space
  2039. * process needs to use that handle to mmap the buffer so it can access them.
  2040. *
  2041. * In some instances, the device must access the command buffer through the
  2042. * device's MMU, and thus its memory should be mapped. In these cases, user can
  2043. * indicate the driver that such a mapping is required.
  2044. * The resulting device virtual address will be used internally by the driver,
  2045. * and won't be returned to user.
  2046. *
  2047. */
  2048. #define DRM_IOCTL_HL_CB DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CB, union hl_cb_args)
  2049. /*
  2050. * Command Submission
  2051. *
  2052. * To submit work to the device, the user need to call this IOCTL with a set
  2053. * of JOBS. That set of JOBS constitutes a CS object.
  2054. * Each JOB will be enqueued on a specific queue, according to the user's input.
  2055. * There can be more then one JOB per queue.
  2056. *
  2057. * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase
  2058. * and a second set is for "execution" phase.
  2059. * The JOBS on the "restore" phase are enqueued only after context-switch
  2060. * (or if its the first CS for this context). The user can also order the
  2061. * driver to run the "restore" phase explicitly
  2062. *
  2063. * Goya/Gaudi:
  2064. * There are two types of queues - external and internal. External queues
  2065. * are DMA queues which transfer data from/to the Host. All other queues are
  2066. * internal. The driver will get completion notifications from the device only
  2067. * on JOBS which are enqueued in the external queues.
  2068. *
  2069. * Gaudi2 onwards:
  2070. * There is a single type of queue for all types of engines, either DMA engines
  2071. * for transfers from/to the host or inside the device, or compute engines.
  2072. * The driver will get completion notifications from the device for all queues.
  2073. *
  2074. * For jobs on external queues, the user needs to create command buffers
  2075. * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on
  2076. * internal queues, the user needs to prepare a "command buffer" with packets
  2077. * on either the device SRAM/DRAM or the host, and give the device address of
  2078. * that buffer to the CS ioctl.
  2079. * For jobs on H/W queues both options of command buffers are valid.
  2080. *
  2081. * This IOCTL is asynchronous in regard to the actual execution of the CS. This
  2082. * means it returns immediately after ALL the JOBS were enqueued on their
  2083. * relevant queues. Therefore, the user mustn't assume the CS has been completed
  2084. * or has even started to execute.
  2085. *
  2086. * Upon successful enqueue, the IOCTL returns a sequence number which the user
  2087. * can use with the "Wait for CS" IOCTL to check whether the handle's CS
  2088. * non-internal JOBS have been completed. Note that if the CS has internal JOBS
  2089. * which can execute AFTER the external JOBS have finished, the driver might
  2090. * report that the CS has finished executing BEFORE the internal JOBS have
  2091. * actually finished executing.
  2092. *
  2093. * Even though the sequence number increments per CS, the user can NOT
  2094. * automatically assume that if CS with sequence number N finished, then CS
  2095. * with sequence number N-1 also finished. The user can make this assumption if
  2096. * and only if CS N and CS N-1 are exactly the same (same CBs for the same
  2097. * queues).
  2098. */
  2099. #define DRM_IOCTL_HL_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_CS, union hl_cs_args)
  2100. /*
  2101. * Wait for Command Submission
  2102. *
  2103. * The user can call this IOCTL with a handle it received from the CS IOCTL
  2104. * to wait until the handle's CS has finished executing. The user will wait
  2105. * inside the kernel until the CS has finished or until the user-requested
  2106. * timeout has expired.
  2107. *
  2108. * If the timeout value is 0, the driver won't sleep at all. It will check
  2109. * the status of the CS and return immediately
  2110. *
  2111. * The return value of the IOCTL is a standard Linux error code. The possible
  2112. * values are:
  2113. *
  2114. * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal
  2115. * that the user process received
  2116. * ETIMEDOUT - The CS has caused a timeout on the device
  2117. * EIO - The CS was aborted (usually because the device was reset)
  2118. * ENODEV - The device wants to do hard-reset (so user need to close FD)
  2119. *
  2120. * The driver also returns a custom define in case the IOCTL call returned 0.
  2121. * The define can be one of the following:
  2122. *
  2123. * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0)
  2124. * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0)
  2125. * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device
  2126. * (ETIMEDOUT)
  2127. * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the
  2128. * device was reset (EIO)
  2129. */
  2130. #define DRM_IOCTL_HL_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_WAIT_CS, union hl_wait_cs_args)
  2131. /*
  2132. * Memory
  2133. * - Map host memory to device MMU
  2134. * - Unmap host memory from device MMU
  2135. *
  2136. * This IOCTL allows the user to map host memory to the device MMU
  2137. *
  2138. * For host memory, the IOCTL doesn't allocate memory. The user is supposed
  2139. * to allocate the memory in user-space (malloc/new). The driver pins the
  2140. * physical pages (up to the allowed limit by the OS), assigns a virtual
  2141. * address in the device VA space and initializes the device MMU.
  2142. *
  2143. * There is an option for the user to specify the requested virtual address.
  2144. *
  2145. */
  2146. #define DRM_IOCTL_HL_MEMORY DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_MEMORY, union hl_mem_args)
  2147. /*
  2148. * Debug
  2149. * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces
  2150. *
  2151. * This IOCTL allows the user to get debug traces from the chip.
  2152. *
  2153. * Before the user can send configuration requests of the various
  2154. * debug/profile engines, it needs to set the device into debug mode.
  2155. * This is because the debug/profile infrastructure is shared component in the
  2156. * device and we can't allow multiple users to access it at the same time.
  2157. *
  2158. * Once a user set the device into debug mode, the driver won't allow other
  2159. * users to "work" with the device, i.e. open a FD. If there are multiple users
  2160. * opened on the device, the driver won't allow any user to debug the device.
  2161. *
  2162. * For each configuration request, the user needs to provide the register index
  2163. * and essential data such as buffer address and size.
  2164. *
  2165. * Once the user has finished using the debug/profile engines, he should
  2166. * set the device into non-debug mode, i.e. disable debug mode.
  2167. *
  2168. * The driver can decide to "kick out" the user if he abuses this interface.
  2169. *
  2170. */
  2171. #define DRM_IOCTL_HL_DEBUG DRM_IOWR(DRM_COMMAND_BASE + HL_IOCTL_DEBUG, struct hl_debug_args)
  2172. #define HL_COMMAND_START (DRM_COMMAND_BASE + HL_IOCTL_INFO)
  2173. #define HL_COMMAND_END (DRM_COMMAND_BASE + HL_IOCTL_DEBUG + 1)
  2174. #endif /* HABANALABS_H_ */