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Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

drm_fourcc.h (70595B)


  1. /*
  2. * Copyright 2011 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21. * OTHER DEALINGS IN THE SOFTWARE.
  22. */
  23. #ifndef DRM_FOURCC_H
  24. #define DRM_FOURCC_H
  25. #include "drm.h"
  26. #if defined(__cplusplus)
  27. extern "C" {
  28. #endif
  29. /**
  30. * DOC: overview
  31. *
  32. * In the DRM subsystem, framebuffer pixel formats are described using the
  33. * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
  34. * fourcc code, a Format Modifier may optionally be provided, in order to
  35. * further describe the buffer's format - for example tiling or compression.
  36. *
  37. * Format Modifiers
  38. * ----------------
  39. *
  40. * Format modifiers are used in conjunction with a fourcc code, forming a
  41. * unique fourcc:modifier pair. This format:modifier pair must fully define the
  42. * format and data layout of the buffer, and should be the only way to describe
  43. * that particular buffer.
  44. *
  45. * Having multiple fourcc:modifier pairs which describe the same layout should
  46. * be avoided, as such aliases run the risk of different drivers exposing
  47. * different names for the same data format, forcing userspace to understand
  48. * that they are aliases.
  49. *
  50. * Format modifiers may change any property of the buffer, including the number
  51. * of planes and/or the required allocation size. Format modifiers are
  52. * vendor-namespaced, and as such the relationship between a fourcc code and a
  53. * modifier is specific to the modifier being used. For example, some modifiers
  54. * may preserve meaning - such as number of planes - from the fourcc code,
  55. * whereas others may not.
  56. *
  57. * Modifiers must uniquely encode buffer layout. In other words, a buffer must
  58. * match only a single modifier. A modifier must not be a subset of layouts of
  59. * another modifier. For instance, it's incorrect to encode pitch alignment in
  60. * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
  61. * aligned modifier. That said, modifiers can have implicit minimal
  62. * requirements.
  63. *
  64. * For modifiers where the combination of fourcc code and modifier can alias,
  65. * a canonical pair needs to be defined and used by all drivers. Preferred
  66. * combinations are also encouraged where all combinations might lead to
  67. * confusion and unnecessarily reduced interoperability. An example for the
  68. * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
  69. *
  70. * There are two kinds of modifier users:
  71. *
  72. * - Kernel and user-space drivers: for drivers it's important that modifiers
  73. * don't alias, otherwise two drivers might support the same format but use
  74. * different aliases, preventing them from sharing buffers in an efficient
  75. * format.
  76. * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
  77. * see modifiers as opaque tokens they can check for equality and intersect.
  78. * These users mustn't need to know to reason about the modifier value
  79. * (i.e. they are not expected to extract information out of the modifier).
  80. *
  81. * Vendors should document their modifier usage in as much detail as
  82. * possible, to ensure maximum compatibility across devices, drivers and
  83. * applications.
  84. *
  85. * The authoritative list of format modifier codes is found in
  86. * `include/uapi/drm/drm_fourcc.h`
  87. *
  88. * Open Source User Waiver
  89. * -----------------------
  90. *
  91. * Because this is the authoritative source for pixel formats and modifiers
  92. * referenced by GL, Vulkan extensions and other standards and hence used both
  93. * by open source and closed source driver stacks, the usual requirement for an
  94. * upstream in-kernel or open source userspace user does not apply.
  95. *
  96. * To ensure, as much as feasible, compatibility across stacks and avoid
  97. * confusion with incompatible enumerations stakeholders for all relevant driver
  98. * stacks should approve additions.
  99. */
  100. #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
  101. ((__u32)(c) << 16) | ((__u32)(d) << 24))
  102. #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
  103. /* Reserve 0 for the invalid format specifier */
  104. #define DRM_FORMAT_INVALID 0
  105. /* color index */
  106. #define DRM_FORMAT_C1 fourcc_code('C', '1', ' ', ' ') /* [7:0] C0:C1:C2:C3:C4:C5:C6:C7 1:1:1:1:1:1:1:1 eight pixels/byte */
  107. #define DRM_FORMAT_C2 fourcc_code('C', '2', ' ', ' ') /* [7:0] C0:C1:C2:C3 2:2:2:2 four pixels/byte */
  108. #define DRM_FORMAT_C4 fourcc_code('C', '4', ' ', ' ') /* [7:0] C0:C1 4:4 two pixels/byte */
  109. #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
  110. /* 1 bpp Darkness (inverse relationship between channel value and brightness) */
  111. #define DRM_FORMAT_D1 fourcc_code('D', '1', ' ', ' ') /* [7:0] D0:D1:D2:D3:D4:D5:D6:D7 1:1:1:1:1:1:1:1 eight pixels/byte */
  112. /* 2 bpp Darkness (inverse relationship between channel value and brightness) */
  113. #define DRM_FORMAT_D2 fourcc_code('D', '2', ' ', ' ') /* [7:0] D0:D1:D2:D3 2:2:2:2 four pixels/byte */
  114. /* 4 bpp Darkness (inverse relationship between channel value and brightness) */
  115. #define DRM_FORMAT_D4 fourcc_code('D', '4', ' ', ' ') /* [7:0] D0:D1 4:4 two pixels/byte */
  116. /* 8 bpp Darkness (inverse relationship between channel value and brightness) */
  117. #define DRM_FORMAT_D8 fourcc_code('D', '8', ' ', ' ') /* [7:0] D */
  118. /* 1 bpp Red (direct relationship between channel value and brightness) */
  119. #define DRM_FORMAT_R1 fourcc_code('R', '1', ' ', ' ') /* [7:0] R0:R1:R2:R3:R4:R5:R6:R7 1:1:1:1:1:1:1:1 eight pixels/byte */
  120. /* 2 bpp Red (direct relationship between channel value and brightness) */
  121. #define DRM_FORMAT_R2 fourcc_code('R', '2', ' ', ' ') /* [7:0] R0:R1:R2:R3 2:2:2:2 four pixels/byte */
  122. /* 4 bpp Red (direct relationship between channel value and brightness) */
  123. #define DRM_FORMAT_R4 fourcc_code('R', '4', ' ', ' ') /* [7:0] R0:R1 4:4 two pixels/byte */
  124. /* 8 bpp Red (direct relationship between channel value and brightness) */
  125. #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
  126. /* 10 bpp Red (direct relationship between channel value and brightness) */
  127. #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
  128. /* 12 bpp Red (direct relationship between channel value and brightness) */
  129. #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
  130. /* 16 bpp Red (direct relationship between channel value and brightness) */
  131. #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
  132. /* 16 bpp RG */
  133. #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
  134. #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
  135. /* 32 bpp RG */
  136. #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
  137. #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
  138. /* 8 bpp RGB */
  139. #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
  140. #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
  141. /* 16 bpp RGB */
  142. #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
  143. #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
  144. #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
  145. #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
  146. #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
  147. #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
  148. #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
  149. #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
  150. #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
  151. #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
  152. #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
  153. #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
  154. #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
  155. #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
  156. #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
  157. #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
  158. #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
  159. #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
  160. /* 24 bpp RGB */
  161. #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
  162. #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
  163. /* 32 bpp RGB */
  164. #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
  165. #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
  166. #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
  167. #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
  168. #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
  169. #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
  170. #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
  171. #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
  172. #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
  173. #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
  174. #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
  175. #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
  176. #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
  177. #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
  178. #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
  179. #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
  180. /* 64 bpp RGB */
  181. #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
  182. #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
  183. #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
  184. #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
  185. /*
  186. * Floating point 64bpp RGB
  187. * IEEE 754-2008 binary16 half-precision float
  188. * [15:0] sign:exponent:mantissa 1:5:10
  189. */
  190. #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
  191. #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
  192. #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
  193. #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
  194. /*
  195. * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
  196. * of unused padding per component:
  197. */
  198. #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
  199. /* packed YCbCr */
  200. #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
  201. #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
  202. #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
  203. #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
  204. #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
  205. #define DRM_FORMAT_AVUY8888 fourcc_code('A', 'V', 'U', 'Y') /* [31:0] A:Cr:Cb:Y 8:8:8:8 little endian */
  206. #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
  207. #define DRM_FORMAT_XVUY8888 fourcc_code('X', 'V', 'U', 'Y') /* [31:0] X:Cr:Cb:Y 8:8:8:8 little endian */
  208. #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
  209. #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
  210. /*
  211. * packed Y2xx indicate for each component, xx valid data occupy msb
  212. * 16-xx padding occupy lsb
  213. */
  214. #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
  215. #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
  216. #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
  217. /*
  218. * packed Y4xx indicate for each component, xx valid data occupy msb
  219. * 16-xx padding occupy lsb except Y410
  220. */
  221. #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
  222. #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
  223. #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
  224. #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
  225. #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
  226. #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
  227. /*
  228. * packed YCbCr420 2x2 tiled formats
  229. * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
  230. */
  231. /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
  232. #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
  233. /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
  234. #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
  235. /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
  236. #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
  237. /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
  238. #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
  239. /*
  240. * 1-plane YUV 4:2:0
  241. * In these formats, the component ordering is specified (Y, followed by U
  242. * then V), but the exact Linear layout is undefined.
  243. * These formats can only be used with a non-Linear modifier.
  244. */
  245. #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
  246. #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
  247. /*
  248. * 2 plane RGB + A
  249. * index 0 = RGB plane, same format as the corresponding non _A8 format has
  250. * index 1 = A plane, [7:0] A
  251. */
  252. #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
  253. #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
  254. #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
  255. #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
  256. #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
  257. #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
  258. #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
  259. #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
  260. /*
  261. * 2 plane YCbCr
  262. * index 0 = Y plane, [7:0] Y
  263. * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
  264. * or
  265. * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
  266. */
  267. #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
  268. #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
  269. #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
  270. #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
  271. #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
  272. #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
  273. /*
  274. * 2 plane YCbCr
  275. * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
  276. * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
  277. */
  278. #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
  279. #define DRM_FORMAT_NV20 fourcc_code('N', 'V', '2', '0') /* 2x1 subsampled Cr:Cb plane */
  280. #define DRM_FORMAT_NV30 fourcc_code('N', 'V', '3', '0') /* non-subsampled Cr:Cb plane */
  281. /*
  282. * 2 plane YCbCr MSB aligned
  283. * index 0 = Y plane, [15:0] Y:x [10:6] little endian
  284. * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
  285. */
  286. #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
  287. /*
  288. * 2 plane YCbCr MSB aligned
  289. * index 0 = Y plane, [15:0] Y:x [10:6] little endian
  290. * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
  291. */
  292. #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
  293. /*
  294. * 2 plane YCbCr MSB aligned
  295. * index 0 = Y plane, [15:0] Y:x [12:4] little endian
  296. * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
  297. */
  298. #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
  299. /*
  300. * 2 plane YCbCr MSB aligned
  301. * index 0 = Y plane, [15:0] Y little endian
  302. * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
  303. */
  304. #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
  305. /* 2 plane YCbCr420.
  306. * 3 10 bit components and 2 padding bits packed into 4 bytes.
  307. * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
  308. * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
  309. */
  310. #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
  311. /* 3 plane non-subsampled (444) YCbCr
  312. * 16 bits per component, but only 10 bits are used and 6 bits are padded
  313. * index 0: Y plane, [15:0] Y:x [10:6] little endian
  314. * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
  315. * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
  316. */
  317. #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
  318. /* 3 plane non-subsampled (444) YCrCb
  319. * 16 bits per component, but only 10 bits are used and 6 bits are padded
  320. * index 0: Y plane, [15:0] Y:x [10:6] little endian
  321. * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
  322. * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
  323. */
  324. #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
  325. /*
  326. * 3 plane YCbCr
  327. * index 0: Y plane, [7:0] Y
  328. * index 1: Cb plane, [7:0] Cb
  329. * index 2: Cr plane, [7:0] Cr
  330. * or
  331. * index 1: Cr plane, [7:0] Cr
  332. * index 2: Cb plane, [7:0] Cb
  333. */
  334. #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
  335. #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
  336. #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
  337. #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
  338. #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
  339. #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
  340. #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
  341. #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
  342. #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
  343. #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
  344. /*
  345. * Format Modifiers:
  346. *
  347. * Format modifiers describe, typically, a re-ordering or modification
  348. * of the data in a plane of an FB. This can be used to express tiled/
  349. * swizzled formats, or compression, or a combination of the two.
  350. *
  351. * The upper 8 bits of the format modifier are a vendor-id as assigned
  352. * below. The lower 56 bits are assigned as vendor sees fit.
  353. */
  354. /* Vendor Ids: */
  355. #define DRM_FORMAT_MOD_VENDOR_NONE 0
  356. #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
  357. #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
  358. #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
  359. #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
  360. #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
  361. #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
  362. #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
  363. #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
  364. #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
  365. #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
  366. /* add more to the end as needed */
  367. #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
  368. #define fourcc_mod_get_vendor(modifier) \
  369. (((modifier) >> 56) & 0xff)
  370. #define fourcc_mod_is_vendor(modifier, vendor) \
  371. (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
  372. #define fourcc_mod_code(vendor, val) \
  373. ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
  374. /*
  375. * Format Modifier tokens:
  376. *
  377. * When adding a new token please document the layout with a code comment,
  378. * similar to the fourcc codes above. drm_fourcc.h is considered the
  379. * authoritative source for all of these.
  380. *
  381. * Generic modifier names:
  382. *
  383. * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
  384. * for layouts which are common across multiple vendors. To preserve
  385. * compatibility, in cases where a vendor-specific definition already exists and
  386. * a generic name for it is desired, the common name is a purely symbolic alias
  387. * and must use the same numerical value as the original definition.
  388. *
  389. * Note that generic names should only be used for modifiers which describe
  390. * generic layouts (such as pixel re-ordering), which may have
  391. * independently-developed support across multiple vendors.
  392. *
  393. * In future cases where a generic layout is identified before merging with a
  394. * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
  395. * 'NONE' could be considered. This should only be for obvious, exceptional
  396. * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
  397. * apply to a single vendor.
  398. *
  399. * Generic names should not be used for cases where multiple hardware vendors
  400. * have implementations of the same standardised compression scheme (such as
  401. * AFBC). In those cases, all implementations should use the same format
  402. * modifier(s), reflecting the vendor of the standard.
  403. */
  404. #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
  405. /*
  406. * Invalid Modifier
  407. *
  408. * This modifier can be used as a sentinel to terminate the format modifiers
  409. * list, or to initialize a variable with an invalid modifier. It might also be
  410. * used to report an error back to userspace for certain APIs.
  411. */
  412. #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
  413. /*
  414. * Linear Layout
  415. *
  416. * Just plain linear layout. Note that this is different from no specifying any
  417. * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
  418. * which tells the driver to also take driver-internal information into account
  419. * and so might actually result in a tiled framebuffer.
  420. */
  421. #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
  422. /*
  423. * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
  424. *
  425. * The "none" format modifier doesn't actually mean that the modifier is
  426. * implicit, instead it means that the layout is linear. Whether modifiers are
  427. * used is out-of-band information carried in an API-specific way (e.g. in a
  428. * flag for drm_mode_fb_cmd2).
  429. */
  430. #define DRM_FORMAT_MOD_NONE 0
  431. /* Intel framebuffer modifiers */
  432. /*
  433. * Intel X-tiling layout
  434. *
  435. * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
  436. * in row-major layout. Within the tile bytes are laid out row-major, with
  437. * a platform-dependent stride. On top of that the memory can apply
  438. * platform-depending swizzling of some higher address bits into bit6.
  439. *
  440. * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
  441. * On earlier platforms the is highly platforms specific and not useful for
  442. * cross-driver sharing. It exists since on a given platform it does uniquely
  443. * identify the layout in a simple way for i915-specific userspace, which
  444. * facilitated conversion of userspace to modifiers. Additionally the exact
  445. * format on some really old platforms is not known.
  446. */
  447. #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
  448. /*
  449. * Intel Y-tiling layout
  450. *
  451. * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
  452. * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
  453. * chunks column-major, with a platform-dependent height. On top of that the
  454. * memory can apply platform-depending swizzling of some higher address bits
  455. * into bit6.
  456. *
  457. * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
  458. * On earlier platforms the is highly platforms specific and not useful for
  459. * cross-driver sharing. It exists since on a given platform it does uniquely
  460. * identify the layout in a simple way for i915-specific userspace, which
  461. * facilitated conversion of userspace to modifiers. Additionally the exact
  462. * format on some really old platforms is not known.
  463. */
  464. #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
  465. /*
  466. * Intel Yf-tiling layout
  467. *
  468. * This is a tiled layout using 4Kb tiles in row-major layout.
  469. * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
  470. * are arranged in four groups (two wide, two high) with column-major layout.
  471. * Each group therefore consists out of four 256 byte units, which are also laid
  472. * out as 2x2 column-major.
  473. * 256 byte units are made out of four 64 byte blocks of pixels, producing
  474. * either a square block or a 2:1 unit.
  475. * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
  476. * in pixel depends on the pixel depth.
  477. */
  478. #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
  479. /*
  480. * Intel color control surface (CCS) for render compression
  481. *
  482. * The framebuffer format must be one of the 8:8:8:8 RGB formats.
  483. * The main surface will be plane index 0 and must be Y/Yf-tiled,
  484. * the CCS will be plane index 1.
  485. *
  486. * Each CCS tile matches a 1024x512 pixel area of the main surface.
  487. * To match certain aspects of the 3D hardware the CCS is
  488. * considered to be made up of normal 128Bx32 Y tiles, Thus
  489. * the CCS pitch must be specified in multiples of 128 bytes.
  490. *
  491. * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
  492. * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
  493. * But that fact is not relevant unless the memory is accessed
  494. * directly.
  495. */
  496. #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
  497. #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
  498. /*
  499. * Intel color control surfaces (CCS) for Gen-12 render compression.
  500. *
  501. * The main surface is Y-tiled and at plane index 0, the CCS is linear and
  502. * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
  503. * main surface. In other words, 4 bits in CCS map to a main surface cache
  504. * line pair. The main surface pitch is required to be a multiple of four
  505. * Y-tile widths.
  506. */
  507. #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
  508. /*
  509. * Intel color control surfaces (CCS) for Gen-12 media compression
  510. *
  511. * The main surface is Y-tiled and at plane index 0, the CCS is linear and
  512. * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
  513. * main surface. In other words, 4 bits in CCS map to a main surface cache
  514. * line pair. The main surface pitch is required to be a multiple of four
  515. * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
  516. * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
  517. * planes 2 and 3 for the respective CCS.
  518. */
  519. #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
  520. /*
  521. * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
  522. * compression.
  523. *
  524. * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
  525. * and at index 1. The clear color is stored at index 2, and the pitch should
  526. * be 64 bytes aligned. The clear color structure is 256 bits. The first 128 bits
  527. * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
  528. * by 32 bits. The raw clear color is consumed by the 3d engine and generates
  529. * the converted clear color of size 64 bits. The first 32 bits store the Lower
  530. * Converted Clear Color value and the next 32 bits store the Higher Converted
  531. * Clear Color value when applicable. The Converted Clear Color values are
  532. * consumed by the DE. The last 64 bits are used to store Color Discard Enable
  533. * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
  534. * corresponds to an area of 4x1 tiles in the main surface. The main surface
  535. * pitch is required to be a multiple of 4 tile widths.
  536. */
  537. #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
  538. /*
  539. * Intel Tile 4 layout
  540. *
  541. * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
  542. * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
  543. * only differs from Tile Y at the 256B granularity in between. At this
  544. * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
  545. * of 64B x 8 rows.
  546. */
  547. #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
  548. /*
  549. * Intel color control surfaces (CCS) for DG2 render compression.
  550. *
  551. * The main surface is Tile 4 and at plane index 0. The CCS data is stored
  552. * outside of the GEM object in a reserved memory area dedicated for the
  553. * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
  554. * main surface pitch is required to be a multiple of four Tile 4 widths.
  555. */
  556. #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
  557. /*
  558. * Intel color control surfaces (CCS) for DG2 media compression.
  559. *
  560. * The main surface is Tile 4 and at plane index 0. For semi-planar formats
  561. * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
  562. * 0 and 1, respectively. The CCS for all planes are stored outside of the
  563. * GEM object in a reserved memory area dedicated for the storage of the
  564. * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
  565. * pitch is required to be a multiple of four Tile 4 widths.
  566. */
  567. #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
  568. /*
  569. * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
  570. *
  571. * The main surface is Tile 4 and at plane index 0. The CCS data is stored
  572. * outside of the GEM object in a reserved memory area dedicated for the
  573. * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
  574. * main surface pitch is required to be a multiple of four Tile 4 widths. The
  575. * clear color is stored at plane index 1 and the pitch should be 64 bytes
  576. * aligned. The format of the 256 bits of clear color data matches the one used
  577. * for the I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
  578. * for details.
  579. */
  580. #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
  581. /*
  582. * Intel Color Control Surfaces (CCS) for display ver. 14 render compression.
  583. *
  584. * The main surface is tile4 and at plane index 0, the CCS is linear and
  585. * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
  586. * main surface. In other words, 4 bits in CCS map to a main surface cache
  587. * line pair. The main surface pitch is required to be a multiple of four
  588. * tile4 widths.
  589. */
  590. #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS fourcc_mod_code(INTEL, 13)
  591. /*
  592. * Intel Color Control Surfaces (CCS) for display ver. 14 media compression
  593. *
  594. * The main surface is tile4 and at plane index 0, the CCS is linear and
  595. * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
  596. * main surface. In other words, 4 bits in CCS map to a main surface cache
  597. * line pair. The main surface pitch is required to be a multiple of four
  598. * tile4 widths. For semi-planar formats like NV12, CCS planes follow the
  599. * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
  600. * planes 2 and 3 for the respective CCS.
  601. */
  602. #define I915_FORMAT_MOD_4_TILED_MTL_MC_CCS fourcc_mod_code(INTEL, 14)
  603. /*
  604. * Intel Color Control Surface with Clear Color (CCS) for display ver. 14 render
  605. * compression.
  606. *
  607. * The main surface is tile4 and is at plane index 0 whereas CCS is linear
  608. * and at index 1. The clear color is stored at index 2, and the pitch should
  609. * be ignored. The clear color structure is 256 bits. The first 128 bits
  610. * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
  611. * by 32 bits. The raw clear color is consumed by the 3d engine and generates
  612. * the converted clear color of size 64 bits. The first 32 bits store the Lower
  613. * Converted Clear Color value and the next 32 bits store the Higher Converted
  614. * Clear Color value when applicable. The Converted Clear Color values are
  615. * consumed by the DE. The last 64 bits are used to store Color Discard Enable
  616. * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
  617. * corresponds to an area of 4x1 tiles in the main surface. The main surface
  618. * pitch is required to be a multiple of 4 tile widths.
  619. */
  620. #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
  621. /*
  622. * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
  623. * on integrated graphics
  624. *
  625. * The main surface is Tile 4 and at plane index 0. For semi-planar formats
  626. * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
  627. * 0 and 1, respectively. The CCS for all planes are stored outside of the
  628. * GEM object in a reserved memory area dedicated for the storage of the
  629. * CCS data for all compressible GEM objects.
  630. */
  631. #define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
  632. /*
  633. * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
  634. * on discrete graphics
  635. *
  636. * The main surface is Tile 4 and at plane index 0. For semi-planar formats
  637. * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
  638. * 0 and 1, respectively. The CCS for all planes are stored outside of the
  639. * GEM object in a reserved memory area dedicated for the storage of the
  640. * CCS data for all compressible GEM objects. The GEM object must be stored in
  641. * contiguous memory with a size aligned to 64KB
  642. */
  643. #define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
  644. /*
  645. * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  646. *
  647. * Macroblocks are laid in a Z-shape, and each pixel data is following the
  648. * standard NV12 style.
  649. * As for NV12, an image is the result of two frame buffers: one for Y,
  650. * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
  651. * Alignment requirements are (for each buffer):
  652. * - multiple of 128 pixels for the width
  653. * - multiple of 32 pixels for the height
  654. *
  655. * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
  656. */
  657. #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
  658. /*
  659. * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
  660. *
  661. * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
  662. * layout. For YCbCr formats Cb/Cr components are taken in such a way that
  663. * they correspond to their 16x16 luma block.
  664. */
  665. #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
  666. /*
  667. * Qualcomm Compressed Format
  668. *
  669. * Refers to a compressed variant of the base format that is compressed.
  670. * Implementation may be platform and base-format specific.
  671. *
  672. * Each macrotile consists of m x n (mostly 4 x 4) tiles.
  673. * Pixel data pitch/stride is aligned with macrotile width.
  674. * Pixel data height is aligned with macrotile height.
  675. * Entire pixel data buffer is aligned with 4k(bytes).
  676. */
  677. #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
  678. /*
  679. * Qualcomm Tiled Format
  680. *
  681. * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
  682. * Implementation may be platform and base-format specific.
  683. *
  684. * Each macrotile consists of m x n (mostly 4 x 4) tiles.
  685. * Pixel data pitch/stride is aligned with macrotile width.
  686. * Pixel data height is aligned with macrotile height.
  687. * Entire pixel data buffer is aligned with 4k(bytes).
  688. */
  689. #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3)
  690. /*
  691. * Qualcomm Alternate Tiled Format
  692. *
  693. * Alternate tiled format typically only used within GMEM.
  694. * Implementation may be platform and base-format specific.
  695. */
  696. #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
  697. /* Vivante framebuffer modifiers */
  698. /*
  699. * Vivante 4x4 tiling layout
  700. *
  701. * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
  702. * layout.
  703. */
  704. #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
  705. /*
  706. * Vivante 64x64 super-tiling layout
  707. *
  708. * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
  709. * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
  710. * major layout.
  711. *
  712. * For more information: see
  713. * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
  714. */
  715. #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
  716. /*
  717. * Vivante 4x4 tiling layout for dual-pipe
  718. *
  719. * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
  720. * different base address. Offsets from the base addresses are therefore halved
  721. * compared to the non-split tiled layout.
  722. */
  723. #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
  724. /*
  725. * Vivante 64x64 super-tiling layout for dual-pipe
  726. *
  727. * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
  728. * starts at a different base address. Offsets from the base addresses are
  729. * therefore halved compared to the non-split super-tiled layout.
  730. */
  731. #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
  732. /*
  733. * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
  734. * the color buffer tiling modifiers defined above. When TS is present it's a
  735. * separate buffer containing the clear/compression status of each tile. The
  736. * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
  737. * tile size in bytes covered by one entry in the status buffer and s is the
  738. * number of status bits per entry.
  739. * We reserve the top 8 bits of the Vivante modifier space for tile status
  740. * clear/compression modifiers, as future cores might add some more TS layout
  741. * variations.
  742. */
  743. #define VIVANTE_MOD_TS_64_4 (1ULL << 48)
  744. #define VIVANTE_MOD_TS_64_2 (2ULL << 48)
  745. #define VIVANTE_MOD_TS_128_4 (3ULL << 48)
  746. #define VIVANTE_MOD_TS_256_4 (4ULL << 48)
  747. #define VIVANTE_MOD_TS_MASK (0xfULL << 48)
  748. /*
  749. * Vivante compression modifiers. Those depend on a TS modifier being present
  750. * as the TS bits get reinterpreted as compression tags instead of simple
  751. * clear markers when compression is enabled.
  752. */
  753. #define VIVANTE_MOD_COMP_DEC400 (1ULL << 52)
  754. #define VIVANTE_MOD_COMP_MASK (0xfULL << 52)
  755. /* Masking out the extension bits will yield the base modifier. */
  756. #define VIVANTE_MOD_EXT_MASK (VIVANTE_MOD_TS_MASK | \
  757. VIVANTE_MOD_COMP_MASK)
  758. /* NVIDIA frame buffer modifiers */
  759. /*
  760. * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
  761. *
  762. * Pixels are arranged in simple tiles of 16 x 16 bytes.
  763. */
  764. #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
  765. /*
  766. * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
  767. * and Tegra GPUs starting with Tegra K1.
  768. *
  769. * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
  770. * based on the architecture generation. GOBs themselves are then arranged in
  771. * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
  772. * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
  773. * a block depth or height of "4").
  774. *
  775. * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
  776. * in full detail.
  777. *
  778. * Macro
  779. * Bits Param Description
  780. * ---- ----- -----------------------------------------------------------------
  781. *
  782. * 3:0 h log2(height) of each block, in GOBs. Placed here for
  783. * compatibility with the existing
  784. * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
  785. *
  786. * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
  787. * compatibility with the existing
  788. * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
  789. *
  790. * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
  791. * size). Must be zero.
  792. *
  793. * Note there is no log2(width) parameter. Some portions of the
  794. * hardware support a block width of two gobs, but it is impractical
  795. * to use due to lack of support elsewhere, and has no known
  796. * benefits.
  797. *
  798. * 11:9 - Reserved (To support 2D-array textures with variable array stride
  799. * in blocks, specified via log2(tile width in blocks)). Must be
  800. * zero.
  801. *
  802. * 19:12 k Page Kind. This value directly maps to a field in the page
  803. * tables of all GPUs >= NV50. It affects the exact layout of bits
  804. * in memory and can be derived from the tuple
  805. *
  806. * (format, GPU model, compression type, samples per pixel)
  807. *
  808. * Where compression type is defined below. If GPU model were
  809. * implied by the format modifier, format, or memory buffer, page
  810. * kind would not need to be included in the modifier itself, but
  811. * since the modifier should define the layout of the associated
  812. * memory buffer independent from any device or other context, it
  813. * must be included here.
  814. *
  815. * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
  816. * starting with Fermi GPUs. Additionally, the mapping between page
  817. * kind and bit layout has changed at various points.
  818. *
  819. * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
  820. * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
  821. * 2 = Gob Height 8, Turing+ Page Kind mapping
  822. * 3 = Reserved for future use.
  823. *
  824. * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
  825. * bit remapping step that occurs at an even lower level than the
  826. * page kind and block linear swizzles. This causes the layout of
  827. * surfaces mapped in those SOC's GPUs to be incompatible with the
  828. * equivalent mapping on other GPUs in the same system.
  829. *
  830. * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
  831. * 1 = Desktop GPU and Tegra Xavier+ Layout
  832. *
  833. * 25:23 c Lossless Framebuffer Compression type.
  834. *
  835. * 0 = none
  836. * 1 = ROP/3D, layout 1, exact compression format implied by Page
  837. * Kind field
  838. * 2 = ROP/3D, layout 2, exact compression format implied by Page
  839. * Kind field
  840. * 3 = CDE horizontal
  841. * 4 = CDE vertical
  842. * 5 = Reserved for future use
  843. * 6 = Reserved for future use
  844. * 7 = Reserved for future use
  845. *
  846. * 55:25 - Reserved for future use. Must be zero.
  847. */
  848. #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
  849. fourcc_mod_code(NVIDIA, (0x10 | \
  850. ((h) & 0xf) | \
  851. (((k) & 0xff) << 12) | \
  852. (((g) & 0x3) << 20) | \
  853. (((s) & 0x1) << 22) | \
  854. (((c) & 0x7) << 23)))
  855. /* To grandfather in prior block linear format modifiers to the above layout,
  856. * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
  857. * with block-linear layouts, is remapped within drivers to the value 0xfe,
  858. * which corresponds to the "generic" kind used for simple single-sample
  859. * uncompressed color formats on Fermi - Volta GPUs.
  860. */
  861. static __inline__ __u64
  862. drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  863. {
  864. if (!(modifier & 0x10) || (modifier & (0xff << 12)))
  865. return modifier;
  866. else
  867. return modifier | (0xfe << 12);
  868. }
  869. /*
  870. * 16Bx2 Block Linear layout, used by Tegra K1 and later
  871. *
  872. * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
  873. * vertically by a power of 2 (1 to 32 GOBs) to form a block.
  874. *
  875. * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
  876. *
  877. * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
  878. * Valid values are:
  879. *
  880. * 0 == ONE_GOB
  881. * 1 == TWO_GOBS
  882. * 2 == FOUR_GOBS
  883. * 3 == EIGHT_GOBS
  884. * 4 == SIXTEEN_GOBS
  885. * 5 == THIRTYTWO_GOBS
  886. *
  887. * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
  888. * in full detail.
  889. */
  890. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
  891. DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
  892. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
  893. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
  894. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
  895. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
  896. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
  897. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
  898. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
  899. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
  900. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
  901. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
  902. #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
  903. DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
  904. /*
  905. * Some Broadcom modifiers take parameters, for example the number of
  906. * vertical lines in the image. Reserve the lower 32 bits for modifier
  907. * type, and the next 24 bits for parameters. Top 8 bits are the
  908. * vendor code.
  909. */
  910. #define __fourcc_mod_broadcom_param_shift 8
  911. #define __fourcc_mod_broadcom_param_bits 48
  912. #define fourcc_mod_broadcom_code(val, params) \
  913. fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
  914. #define fourcc_mod_broadcom_param(m) \
  915. ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
  916. ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
  917. #define fourcc_mod_broadcom_mod(m) \
  918. ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
  919. __fourcc_mod_broadcom_param_shift))
  920. /*
  921. * Broadcom VC4 "T" format
  922. *
  923. * This is the primary layout that the V3D GPU can texture from (it
  924. * can't do linear). The T format has:
  925. *
  926. * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
  927. * pixels at 32 bit depth.
  928. *
  929. * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
  930. * 16x16 pixels).
  931. *
  932. * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
  933. * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
  934. * they're (TR, BR, BL, TL), where bottom left is start of memory.
  935. *
  936. * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
  937. * tiles) or right-to-left (odd rows of 4k tiles).
  938. */
  939. #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
  940. /*
  941. * Broadcom SAND format
  942. *
  943. * This is the native format that the H.264 codec block uses. For VC4
  944. * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
  945. *
  946. * The image can be considered to be split into columns, and the
  947. * columns are placed consecutively into memory. The width of those
  948. * columns can be either 32, 64, 128, or 256 pixels, but in practice
  949. * only 128 pixel columns are used.
  950. *
  951. * The pitch between the start of each column is set to optimally
  952. * switch between SDRAM banks. This is passed as the number of lines
  953. * of column width in the modifier (we can't use the stride value due
  954. * to various core checks that look at it , so you should set the
  955. * stride to width*cpp).
  956. *
  957. * Note that the column height for this format modifier is the same
  958. * for all of the planes, assuming that each column contains both Y
  959. * and UV. Some SAND-using hardware stores UV in a separate tiled
  960. * image from Y to reduce the column height, which is not supported
  961. * with these modifiers.
  962. *
  963. * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
  964. * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
  965. * wide, but as this is a 10 bpp format that translates to 96 pixels.
  966. */
  967. #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
  968. fourcc_mod_broadcom_code(2, v)
  969. #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
  970. fourcc_mod_broadcom_code(3, v)
  971. #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
  972. fourcc_mod_broadcom_code(4, v)
  973. #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
  974. fourcc_mod_broadcom_code(5, v)
  975. #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
  976. DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
  977. #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
  978. DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
  979. #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
  980. DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
  981. #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
  982. DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
  983. /* Broadcom UIF format
  984. *
  985. * This is the common format for the current Broadcom multimedia
  986. * blocks, including V3D 3.x and newer, newer video codecs, and
  987. * displays.
  988. *
  989. * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
  990. * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
  991. * stored in columns, with padding between the columns to ensure that
  992. * moving from one column to the next doesn't hit the same SDRAM page
  993. * bank.
  994. *
  995. * To calculate the padding, it is assumed that each hardware block
  996. * and the software driving it knows the platform's SDRAM page size,
  997. * number of banks, and XOR address, and that it's identical between
  998. * all blocks using the format. This tiling modifier will use XOR as
  999. * necessary to reduce the padding. If a hardware block can't do XOR,
  1000. * the assumption is that a no-XOR tiling modifier will be created.
  1001. */
  1002. #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
  1003. /*
  1004. * Arm Framebuffer Compression (AFBC) modifiers
  1005. *
  1006. * AFBC is a proprietary lossless image compression protocol and format.
  1007. * It provides fine-grained random access and minimizes the amount of data
  1008. * transferred between IP blocks.
  1009. *
  1010. * AFBC has several features which may be supported and/or used, which are
  1011. * represented using bits in the modifier. Not all combinations are valid,
  1012. * and different devices or use-cases may support different combinations.
  1013. *
  1014. * Further information on the use of AFBC modifiers can be found in
  1015. * Documentation/gpu/afbc.rst
  1016. */
  1017. /*
  1018. * The top 4 bits (out of the 56 bits allotted for specifying vendor specific
  1019. * modifiers) denote the category for modifiers. Currently we have three
  1020. * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
  1021. * sixteen different categories.
  1022. */
  1023. #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
  1024. fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
  1025. #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
  1026. #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
  1027. #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
  1028. DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
  1029. /*
  1030. * AFBC superblock size
  1031. *
  1032. * Indicates the superblock size(s) used for the AFBC buffer. The buffer
  1033. * size (in pixels) must be aligned to a multiple of the superblock size.
  1034. * Four lowest significant bits(LSBs) are reserved for block size.
  1035. *
  1036. * Where one superblock size is specified, it applies to all planes of the
  1037. * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
  1038. * the first applies to the Luma plane and the second applies to the Chroma
  1039. * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
  1040. * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
  1041. */
  1042. #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
  1043. #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
  1044. #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
  1045. #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
  1046. #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
  1047. /*
  1048. * AFBC lossless colorspace transform
  1049. *
  1050. * Indicates that the buffer makes use of the AFBC lossless colorspace
  1051. * transform.
  1052. */
  1053. #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
  1054. /*
  1055. * AFBC block-split
  1056. *
  1057. * Indicates that the payload of each superblock is split. The second
  1058. * half of the payload is positioned at a predefined offset from the start
  1059. * of the superblock payload.
  1060. */
  1061. #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
  1062. /*
  1063. * AFBC sparse layout
  1064. *
  1065. * This flag indicates that the payload of each superblock must be stored at a
  1066. * predefined position relative to the other superblocks in the same AFBC
  1067. * buffer. This order is the same order used by the header buffer. In this mode
  1068. * each superblock is given the same amount of space as an uncompressed
  1069. * superblock of the particular format would require, rounding up to the next
  1070. * multiple of 128 bytes in size.
  1071. */
  1072. #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
  1073. /*
  1074. * AFBC copy-block restrict
  1075. *
  1076. * Buffers with this flag must obey the copy-block restriction. The restriction
  1077. * is such that there are no copy-blocks referring across the border of 8x8
  1078. * blocks. For the subsampled data the 8x8 limitation is also subsampled.
  1079. */
  1080. #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
  1081. /*
  1082. * AFBC tiled layout
  1083. *
  1084. * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
  1085. * superblocks inside a tile are stored together in memory. 8x8 tiles are used
  1086. * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
  1087. * larger bpp formats. The order between the tiles is scan line.
  1088. * When the tiled layout is used, the buffer size (in pixels) must be aligned
  1089. * to the tile size.
  1090. */
  1091. #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
  1092. /*
  1093. * AFBC solid color blocks
  1094. *
  1095. * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
  1096. * can be reduced if a whole superblock is a single color.
  1097. */
  1098. #define AFBC_FORMAT_MOD_SC (1ULL << 9)
  1099. /*
  1100. * AFBC double-buffer
  1101. *
  1102. * Indicates that the buffer is allocated in a layout safe for front-buffer
  1103. * rendering.
  1104. */
  1105. #define AFBC_FORMAT_MOD_DB (1ULL << 10)
  1106. /*
  1107. * AFBC buffer content hints
  1108. *
  1109. * Indicates that the buffer includes per-superblock content hints.
  1110. */
  1111. #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
  1112. /* AFBC uncompressed storage mode
  1113. *
  1114. * Indicates that the buffer is using AFBC uncompressed storage mode.
  1115. * In this mode all superblock payloads in the buffer use the uncompressed
  1116. * storage mode, which is usually only used for data which cannot be compressed.
  1117. * The buffer layout is the same as for AFBC buffers without USM set, this only
  1118. * affects the storage mode of the individual superblocks. Note that even a
  1119. * buffer without USM set may use uncompressed storage mode for some or all
  1120. * superblocks, USM just guarantees it for all.
  1121. */
  1122. #define AFBC_FORMAT_MOD_USM (1ULL << 12)
  1123. /*
  1124. * Arm Fixed-Rate Compression (AFRC) modifiers
  1125. *
  1126. * AFRC is a proprietary fixed rate image compression protocol and format,
  1127. * designed to provide guaranteed bandwidth and memory footprint
  1128. * reductions in graphics and media use-cases.
  1129. *
  1130. * AFRC buffers consist of one or more planes, with the same components
  1131. * and meaning as an uncompressed buffer using the same pixel format.
  1132. *
  1133. * Within each plane, the pixel/luma/chroma values are grouped into
  1134. * "coding unit" blocks which are individually compressed to a
  1135. * fixed size (in bytes). All coding units within a given plane of a buffer
  1136. * store the same number of values, and have the same compressed size.
  1137. *
  1138. * The coding unit size is configurable, allowing different rates of compression.
  1139. *
  1140. * The start of each AFRC buffer plane must be aligned to an alignment granule which
  1141. * depends on the coding unit size.
  1142. *
  1143. * Coding Unit Size Plane Alignment
  1144. * ---------------- ---------------
  1145. * 16 bytes 1024 bytes
  1146. * 24 bytes 512 bytes
  1147. * 32 bytes 2048 bytes
  1148. *
  1149. * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
  1150. * to a multiple of the paging tile dimensions.
  1151. * The dimensions of each paging tile depend on whether the buffer is optimised for
  1152. * scanline (SCAN layout) or rotated (ROT layout) access.
  1153. *
  1154. * Layout Paging Tile Width Paging Tile Height
  1155. * ------ ----------------- ------------------
  1156. * SCAN 16 coding units 4 coding units
  1157. * ROT 8 coding units 8 coding units
  1158. *
  1159. * The dimensions of each coding unit depend on the number of components
  1160. * in the compressed plane and whether the buffer is optimised for
  1161. * scanline (SCAN layout) or rotated (ROT layout) access.
  1162. *
  1163. * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
  1164. * ----------------------------- --------- ----------------- ------------------
  1165. * 1 SCAN 16 samples 4 samples
  1166. * Example: 16x4 luma samples in a 'Y' plane
  1167. * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
  1168. * ----------------------------- --------- ----------------- ------------------
  1169. * 1 ROT 8 samples 8 samples
  1170. * Example: 8x8 luma samples in a 'Y' plane
  1171. * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
  1172. * ----------------------------- --------- ----------------- ------------------
  1173. * 2 DONT CARE 8 samples 4 samples
  1174. * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
  1175. * ----------------------------- --------- ----------------- ------------------
  1176. * 3 DONT CARE 4 samples 4 samples
  1177. * Example: 4x4 pixels in an RGB buffer without alpha
  1178. * ----------------------------- --------- ----------------- ------------------
  1179. * 4 DONT CARE 4 samples 4 samples
  1180. * Example: 4x4 pixels in an RGB buffer with alpha
  1181. */
  1182. #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
  1183. #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
  1184. DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
  1185. /*
  1186. * AFRC coding unit size modifier.
  1187. *
  1188. * Indicates the number of bytes used to store each compressed coding unit for
  1189. * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
  1190. * is the same for both Cb and Cr, which may be stored in separate planes.
  1191. *
  1192. * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
  1193. * each compressed coding unit in the first plane of the buffer. For RGBA buffers
  1194. * this is the only plane, while for semi-planar and fully-planar YUV buffers,
  1195. * this corresponds to the luma plane.
  1196. *
  1197. * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
  1198. * each compressed coding unit in the second and third planes in the buffer.
  1199. * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
  1200. *
  1201. * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
  1202. * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
  1203. * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
  1204. * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
  1205. */
  1206. #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
  1207. #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
  1208. #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
  1209. #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
  1210. #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
  1211. #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
  1212. /*
  1213. * AFRC scanline memory layout.
  1214. *
  1215. * Indicates if the buffer uses the scanline-optimised layout
  1216. * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
  1217. * The memory layout is the same for all planes.
  1218. */
  1219. #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
  1220. /*
  1221. * Arm 16x16 Block U-Interleaved modifier
  1222. *
  1223. * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
  1224. * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
  1225. * in the block are reordered.
  1226. */
  1227. #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
  1228. DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
  1229. /*
  1230. * Allwinner tiled modifier
  1231. *
  1232. * This tiling mode is implemented by the VPU found on all Allwinner platforms,
  1233. * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
  1234. * planes.
  1235. *
  1236. * With this tiling, the luminance samples are disposed in tiles representing
  1237. * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
  1238. * The pixel order in each tile is linear and the tiles are disposed linearly,
  1239. * both in row-major order.
  1240. */
  1241. #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
  1242. /*
  1243. * Amlogic Video Framebuffer Compression modifiers
  1244. *
  1245. * Amlogic uses a proprietary lossless image compression protocol and format
  1246. * for their hardware video codec accelerators, either video decoders or
  1247. * video input encoders.
  1248. *
  1249. * It considerably reduces memory bandwidth while writing and reading
  1250. * frames in memory.
  1251. *
  1252. * The underlying storage is considered to be 3 components, 8bit or 10-bit
  1253. * per component YCbCr 420, single plane :
  1254. * - DRM_FORMAT_YUV420_8BIT
  1255. * - DRM_FORMAT_YUV420_10BIT
  1256. *
  1257. * The first 8 bits of the mode defines the layout, then the following 8 bits
  1258. * defines the options changing the layout.
  1259. *
  1260. * Not all combinations are valid, and different SoCs may support different
  1261. * combinations of layout and options.
  1262. */
  1263. #define __fourcc_mod_amlogic_layout_mask 0xff
  1264. #define __fourcc_mod_amlogic_options_shift 8
  1265. #define __fourcc_mod_amlogic_options_mask 0xff
  1266. #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
  1267. fourcc_mod_code(AMLOGIC, \
  1268. ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
  1269. (((__options) & __fourcc_mod_amlogic_options_mask) \
  1270. << __fourcc_mod_amlogic_options_shift))
  1271. /* Amlogic FBC Layouts */
  1272. /*
  1273. * Amlogic FBC Basic Layout
  1274. *
  1275. * The basic layout is composed of:
  1276. * - a body content organized in 64x32 superblocks with 4096 bytes per
  1277. * superblock in default mode.
  1278. * - a 32 bytes per 128x64 header block
  1279. *
  1280. * This layout is transferrable between Amlogic SoCs supporting this modifier.
  1281. */
  1282. #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
  1283. /*
  1284. * Amlogic FBC Scatter Memory layout
  1285. *
  1286. * Indicates the header contains IOMMU references to the compressed
  1287. * frames content to optimize memory access and layout.
  1288. *
  1289. * In this mode, only the header memory address is needed, thus the
  1290. * content memory organization is tied to the current producer
  1291. * execution and cannot be saved/dumped neither transferrable between
  1292. * Amlogic SoCs supporting this modifier.
  1293. *
  1294. * Due to the nature of the layout, these buffers are not expected to
  1295. * be accessible by the user-space clients, but only accessible by the
  1296. * hardware producers and consumers.
  1297. *
  1298. * The user-space clients should expect a failure while trying to mmap
  1299. * the DMA-BUF handle returned by the producer.
  1300. */
  1301. #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
  1302. /* Amlogic FBC Layout Options Bit Mask */
  1303. /*
  1304. * Amlogic FBC Memory Saving mode
  1305. *
  1306. * Indicates the storage is packed when pixel size is multiple of word
  1307. * boundaries, i.e. 8bit should be stored in this mode to save allocation
  1308. * memory.
  1309. *
  1310. * This mode reduces body layout to 3072 bytes per 64x32 superblock with
  1311. * the basic layout and 3200 bytes per 64x32 superblock combined with
  1312. * the scatter layout.
  1313. */
  1314. #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
  1315. /*
  1316. * AMD modifiers
  1317. *
  1318. * Memory layout:
  1319. *
  1320. * without DCC:
  1321. * - main surface
  1322. *
  1323. * with DCC & without DCC_RETILE:
  1324. * - main surface in plane 0
  1325. * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
  1326. *
  1327. * with DCC & DCC_RETILE:
  1328. * - main surface in plane 0
  1329. * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
  1330. * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
  1331. *
  1332. * For multi-plane formats the above surfaces get merged into one plane for
  1333. * each format plane, based on the required alignment only.
  1334. *
  1335. * Bits Parameter Notes
  1336. * ----- ------------------------ ---------------------------------------------
  1337. *
  1338. * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
  1339. * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
  1340. * 13 DCC
  1341. * 14 DCC_RETILE
  1342. * 15 DCC_PIPE_ALIGN
  1343. * 16 DCC_INDEPENDENT_64B
  1344. * 17 DCC_INDEPENDENT_128B
  1345. * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
  1346. * 20 DCC_CONSTANT_ENCODE
  1347. * 23:21 PIPE_XOR_BITS Only for some chips
  1348. * 26:24 BANK_XOR_BITS Only for some chips
  1349. * 29:27 PACKERS Only for some chips
  1350. * 32:30 RB Only for some chips
  1351. * 35:33 PIPE Only for some chips
  1352. * 55:36 - Reserved for future use, must be zero
  1353. */
  1354. #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
  1355. #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
  1356. /* Reserve 0 for GFX8 and older */
  1357. #define AMD_FMT_MOD_TILE_VER_GFX9 1
  1358. #define AMD_FMT_MOD_TILE_VER_GFX10 2
  1359. #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
  1360. #define AMD_FMT_MOD_TILE_VER_GFX11 4
  1361. #define AMD_FMT_MOD_TILE_VER_GFX12 5
  1362. /*
  1363. * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
  1364. * version.
  1365. */
  1366. #define AMD_FMT_MOD_TILE_GFX9_64K_S 9
  1367. /*
  1368. * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
  1369. * GFX9 as canonical version.
  1370. *
  1371. * 64K_D_2D on GFX12 is identical to 64K_D on GFX11.
  1372. */
  1373. #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
  1374. #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
  1375. #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
  1376. #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
  1377. #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31
  1378. /* Gfx12 swizzle modes:
  1379. * 0 - LINEAR
  1380. * 1 - 256B_2D - 2D block dimensions
  1381. * 2 - 4KB_2D
  1382. * 3 - 64KB_2D
  1383. * 4 - 256KB_2D
  1384. * 5 - 4KB_3D - 3D block dimensions
  1385. * 6 - 64KB_3D
  1386. * 7 - 256KB_3D
  1387. */
  1388. #define AMD_FMT_MOD_TILE_GFX12_256B_2D 1
  1389. #define AMD_FMT_MOD_TILE_GFX12_4K_2D 2
  1390. #define AMD_FMT_MOD_TILE_GFX12_64K_2D 3
  1391. #define AMD_FMT_MOD_TILE_GFX12_256K_2D 4
  1392. #define AMD_FMT_MOD_DCC_BLOCK_64B 0
  1393. #define AMD_FMT_MOD_DCC_BLOCK_128B 1
  1394. #define AMD_FMT_MOD_DCC_BLOCK_256B 2
  1395. #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
  1396. #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
  1397. #define AMD_FMT_MOD_TILE_SHIFT 8
  1398. #define AMD_FMT_MOD_TILE_MASK 0x1F
  1399. /* Whether DCC compression is enabled. */
  1400. #define AMD_FMT_MOD_DCC_SHIFT 13
  1401. #define AMD_FMT_MOD_DCC_MASK 0x1
  1402. /*
  1403. * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
  1404. * one which is not-aligned.
  1405. */
  1406. #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
  1407. #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
  1408. /* Only set if DCC_RETILE = false */
  1409. #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
  1410. #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
  1411. #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
  1412. #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
  1413. #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
  1414. #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
  1415. #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
  1416. #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
  1417. /*
  1418. * DCC supports embedding some clear colors directly in the DCC surface.
  1419. * However, on older GPUs the rendering HW ignores the embedded clear color
  1420. * and prefers the driver provided color. This necessitates doing a fastclear
  1421. * eliminate operation before a process transfers control.
  1422. *
  1423. * If this bit is set that means the fastclear eliminate is not needed for these
  1424. * embeddable colors.
  1425. */
  1426. #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
  1427. #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
  1428. /*
  1429. * The below fields are for accounting for per GPU differences. These are only
  1430. * relevant for GFX9 and later and if the tile field is *_X/_T.
  1431. *
  1432. * PIPE_XOR_BITS = always needed
  1433. * BANK_XOR_BITS = only for TILE_VER_GFX9
  1434. * PACKERS = only for TILE_VER_GFX10_RBPLUS
  1435. * RB = only for TILE_VER_GFX9 & DCC
  1436. * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
  1437. */
  1438. #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
  1439. #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
  1440. #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
  1441. #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
  1442. #define AMD_FMT_MOD_PACKERS_SHIFT 27
  1443. #define AMD_FMT_MOD_PACKERS_MASK 0x7
  1444. #define AMD_FMT_MOD_RB_SHIFT 30
  1445. #define AMD_FMT_MOD_RB_MASK 0x7
  1446. #define AMD_FMT_MOD_PIPE_SHIFT 33
  1447. #define AMD_FMT_MOD_PIPE_MASK 0x7
  1448. #define AMD_FMT_MOD_SET(field, value) \
  1449. ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
  1450. #define AMD_FMT_MOD_GET(field, value) \
  1451. (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
  1452. #define AMD_FMT_MOD_CLEAR(field) \
  1453. (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
  1454. #if defined(__cplusplus)
  1455. }
  1456. #endif
  1457. #endif /* DRM_FOURCC_H */