logo

oasis-root

Compiled tree of Oasis Linux based on own branch at <https://hacktivis.me/git/oasis/> git clone https://anongit.hacktivis.me/git/oasis-root.git

amd_hsmp.h (11550B)


  1. /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
  2. #ifndef _ASM_X86_AMD_HSMP_H_
  3. #define _ASM_X86_AMD_HSMP_H_
  4. #include <linux/types.h>
  5. #pragma pack(4)
  6. #define HSMP_MAX_MSG_LEN 8
  7. /*
  8. * HSMP Messages supported
  9. */
  10. enum hsmp_message_ids {
  11. HSMP_TEST = 1, /* 01h Increments input value by 1 */
  12. HSMP_GET_SMU_VER, /* 02h SMU FW version */
  13. HSMP_GET_PROTO_VER, /* 03h HSMP interface version */
  14. HSMP_GET_SOCKET_POWER, /* 04h average package power consumption */
  15. HSMP_SET_SOCKET_POWER_LIMIT, /* 05h Set the socket power limit */
  16. HSMP_GET_SOCKET_POWER_LIMIT, /* 06h Get current socket power limit */
  17. HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */
  18. HSMP_SET_BOOST_LIMIT, /* 08h Set a core maximum frequency limit */
  19. HSMP_SET_BOOST_LIMIT_SOCKET, /* 09h Set socket maximum frequency level */
  20. HSMP_GET_BOOST_LIMIT, /* 0Ah Get current frequency limit */
  21. HSMP_GET_PROC_HOT, /* 0Bh Get PROCHOT status */
  22. HSMP_SET_XGMI_LINK_WIDTH, /* 0Ch Set max and min width of xGMI Link */
  23. HSMP_SET_DF_PSTATE, /* 0Dh Alter APEnable/Disable messages behavior */
  24. HSMP_SET_AUTO_DF_PSTATE, /* 0Eh Enable DF P-State Performance Boost algorithm */
  25. HSMP_GET_FCLK_MCLK, /* 0Fh Get FCLK and MEMCLK for current socket */
  26. HSMP_GET_CCLK_THROTTLE_LIMIT, /* 10h Get CCLK frequency limit in socket */
  27. HSMP_GET_C0_PERCENT, /* 11h Get average C0 residency in socket */
  28. HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */
  29. HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */
  30. HSMP_GET_DDR_BANDWIDTH, /* 14h Get theoretical maximum and current DDR Bandwidth */
  31. HSMP_GET_TEMP_MONITOR, /* 15h Get socket temperature */
  32. HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */
  33. HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */
  34. HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */
  35. HSMP_GET_SOCKET_FREQ_LIMIT, /* 19h Get current active frequency per socket */
  36. HSMP_GET_CCLK_CORE_LIMIT, /* 1Ah Get CCLK frequency limit per core */
  37. HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */
  38. HSMP_GET_SOCKET_FMAX_FMIN, /* 1Ch Get Fmax and Fmin per socket */
  39. HSMP_GET_IOLINK_BANDWITH, /* 1Dh Get current bandwidth on IO Link */
  40. HSMP_GET_XGMI_BANDWITH, /* 1Eh Get current bandwidth on xGMI Link */
  41. HSMP_SET_GMI3_WIDTH, /* 1Fh Set max and min GMI3 Link width */
  42. HSMP_SET_PCI_RATE, /* 20h Control link rate on PCIe devices */
  43. HSMP_SET_POWER_MODE, /* 21h Select power efficiency profile policy */
  44. HSMP_SET_PSTATE_MAX_MIN, /* 22h Set the max and min DF P-State */
  45. HSMP_GET_METRIC_TABLE_VER, /* 23h Get metrics table version */
  46. HSMP_GET_METRIC_TABLE, /* 24h Get metrics table */
  47. HSMP_GET_METRIC_TABLE_DRAM_ADDR,/* 25h Get metrics table dram address */
  48. HSMP_MSG_ID_MAX,
  49. };
  50. struct hsmp_message {
  51. __u32 msg_id; /* Message ID */
  52. __u16 num_args; /* Number of input argument words in message */
  53. __u16 response_sz; /* Number of expected output/response words */
  54. __u32 args[HSMP_MAX_MSG_LEN]; /* argument/response buffer */
  55. __u16 sock_ind; /* socket number */
  56. };
  57. enum hsmp_msg_type {
  58. HSMP_RSVD = -1,
  59. HSMP_SET = 0,
  60. HSMP_GET = 1,
  61. };
  62. enum hsmp_proto_versions {
  63. HSMP_PROTO_VER2 = 2,
  64. HSMP_PROTO_VER3,
  65. HSMP_PROTO_VER4,
  66. HSMP_PROTO_VER5,
  67. HSMP_PROTO_VER6
  68. };
  69. struct hsmp_msg_desc {
  70. int num_args;
  71. int response_sz;
  72. enum hsmp_msg_type type;
  73. };
  74. /*
  75. * User may use these comments as reference, please find the
  76. * supported list of messages and message definition in the
  77. * HSMP chapter of respective family/model PPR.
  78. *
  79. * Not supported messages would return -ENOMSG.
  80. */
  81. static const struct hsmp_msg_desc hsmp_msg_desc_table[] = {
  82. /* RESERVED */
  83. {0, 0, HSMP_RSVD},
  84. /*
  85. * HSMP_TEST, num_args = 1, response_sz = 1
  86. * input: args[0] = xx
  87. * output: args[0] = xx + 1
  88. */
  89. {1, 1, HSMP_GET},
  90. /*
  91. * HSMP_GET_SMU_VER, num_args = 0, response_sz = 1
  92. * output: args[0] = smu fw ver
  93. */
  94. {0, 1, HSMP_GET},
  95. /*
  96. * HSMP_GET_PROTO_VER, num_args = 0, response_sz = 1
  97. * output: args[0] = proto version
  98. */
  99. {0, 1, HSMP_GET},
  100. /*
  101. * HSMP_GET_SOCKET_POWER, num_args = 0, response_sz = 1
  102. * output: args[0] = socket power in mWatts
  103. */
  104. {0, 1, HSMP_GET},
  105. /*
  106. * HSMP_SET_SOCKET_POWER_LIMIT, num_args = 1, response_sz = 0
  107. * input: args[0] = power limit value in mWatts
  108. */
  109. {1, 0, HSMP_SET},
  110. /*
  111. * HSMP_GET_SOCKET_POWER_LIMIT, num_args = 0, response_sz = 1
  112. * output: args[0] = socket power limit value in mWatts
  113. */
  114. {0, 1, HSMP_GET},
  115. /*
  116. * HSMP_GET_SOCKET_POWER_LIMIT_MAX, num_args = 0, response_sz = 1
  117. * output: args[0] = maximuam socket power limit in mWatts
  118. */
  119. {0, 1, HSMP_GET},
  120. /*
  121. * HSMP_SET_BOOST_LIMIT, num_args = 1, response_sz = 0
  122. * input: args[0] = apic id[31:16] + boost limit value in MHz[15:0]
  123. */
  124. {1, 0, HSMP_SET},
  125. /*
  126. * HSMP_SET_BOOST_LIMIT_SOCKET, num_args = 1, response_sz = 0
  127. * input: args[0] = boost limit value in MHz
  128. */
  129. {1, 0, HSMP_SET},
  130. /*
  131. * HSMP_GET_BOOST_LIMIT, num_args = 1, response_sz = 1
  132. * input: args[0] = apic id
  133. * output: args[0] = boost limit value in MHz
  134. */
  135. {1, 1, HSMP_GET},
  136. /*
  137. * HSMP_GET_PROC_HOT, num_args = 0, response_sz = 1
  138. * output: args[0] = proc hot status
  139. */
  140. {0, 1, HSMP_GET},
  141. /*
  142. * HSMP_SET_XGMI_LINK_WIDTH, num_args = 1, response_sz = 0
  143. * input: args[0] = min link width[15:8] + max link width[7:0]
  144. */
  145. {1, 0, HSMP_SET},
  146. /*
  147. * HSMP_SET_DF_PSTATE, num_args = 1, response_sz = 0
  148. * input: args[0] = df pstate[7:0]
  149. */
  150. {1, 0, HSMP_SET},
  151. /* HSMP_SET_AUTO_DF_PSTATE, num_args = 0, response_sz = 0 */
  152. {0, 0, HSMP_SET},
  153. /*
  154. * HSMP_GET_FCLK_MCLK, num_args = 0, response_sz = 2
  155. * output: args[0] = fclk in MHz, args[1] = mclk in MHz
  156. */
  157. {0, 2, HSMP_GET},
  158. /*
  159. * HSMP_GET_CCLK_THROTTLE_LIMIT, num_args = 0, response_sz = 1
  160. * output: args[0] = core clock in MHz
  161. */
  162. {0, 1, HSMP_GET},
  163. /*
  164. * HSMP_GET_C0_PERCENT, num_args = 0, response_sz = 1
  165. * output: args[0] = average c0 residency
  166. */
  167. {0, 1, HSMP_GET},
  168. /*
  169. * HSMP_SET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 0
  170. * input: args[0] = nbioid[23:16] + max dpm level[15:8] + min dpm level[7:0]
  171. */
  172. {1, 0, HSMP_SET},
  173. /*
  174. * HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1
  175. * input: args[0] = nbioid[23:16]
  176. * output: args[0] = max dpm level[15:8] + min dpm level[7:0]
  177. */
  178. {1, 1, HSMP_GET},
  179. /*
  180. * HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1
  181. * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] +
  182. * bw in percentage[7:0]
  183. */
  184. {0, 1, HSMP_GET},
  185. /*
  186. * HSMP_GET_TEMP_MONITOR, num_args = 0, response_sz = 1
  187. * output: args[0] = temperature in degree celsius. [15:8] integer part +
  188. * [7:5] fractional part
  189. */
  190. {0, 1, HSMP_GET},
  191. /*
  192. * HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1
  193. * input: args[0] = DIMM address[7:0]
  194. * output: args[0] = refresh rate[3] + temperature range[2:0]
  195. */
  196. {1, 1, HSMP_GET},
  197. /*
  198. * HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1
  199. * input: args[0] = DIMM address[7:0]
  200. * output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] +
  201. * DIMM address[7:0]
  202. */
  203. {1, 1, HSMP_GET},
  204. /*
  205. * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1
  206. * input: args[0] = DIMM address[7:0]
  207. * output: args[0] = temperature in degree celsius[31:21] + update rate in ms[16:8] +
  208. * DIMM address[7:0]
  209. */
  210. {1, 1, HSMP_GET},
  211. /*
  212. * HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1
  213. * output: args[0] = frequency in MHz[31:16] + frequency source[15:0]
  214. */
  215. {0, 1, HSMP_GET},
  216. /*
  217. * HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1
  218. * input: args[0] = apic id [31:0]
  219. * output: args[0] = frequency in MHz[31:0]
  220. */
  221. {1, 1, HSMP_GET},
  222. /*
  223. * HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1
  224. * output: args[0] = power in mW[31:0]
  225. */
  226. {0, 1, HSMP_GET},
  227. /*
  228. * HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1
  229. * output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0]
  230. */
  231. {0, 1, HSMP_GET},
  232. /*
  233. * HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1
  234. * input: args[0] = link id[15:8] + bw type[2:0]
  235. * output: args[0] = io bandwidth in Mbps[31:0]
  236. */
  237. {1, 1, HSMP_GET},
  238. /*
  239. * HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1
  240. * input: args[0] = link id[15:8] + bw type[2:0]
  241. * output: args[0] = xgmi bandwidth in Mbps[31:0]
  242. */
  243. {1, 1, HSMP_GET},
  244. /*
  245. * HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0
  246. * input: args[0] = min link width[15:8] + max link width[7:0]
  247. */
  248. {1, 0, HSMP_SET},
  249. /*
  250. * HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1
  251. * input: args[0] = link rate control value
  252. * output: args[0] = previous link rate control value
  253. */
  254. {1, 1, HSMP_SET},
  255. /*
  256. * HSMP_SET_POWER_MODE, num_args = 1, response_sz = 0
  257. * input: args[0] = power efficiency mode[2:0]
  258. */
  259. {1, 0, HSMP_SET},
  260. /*
  261. * HSMP_SET_PSTATE_MAX_MIN, num_args = 1, response_sz = 0
  262. * input: args[0] = min df pstate[15:8] + max df pstate[7:0]
  263. */
  264. {1, 0, HSMP_SET},
  265. /*
  266. * HSMP_GET_METRIC_TABLE_VER, num_args = 0, response_sz = 1
  267. * output: args[0] = metrics table version
  268. */
  269. {0, 1, HSMP_GET},
  270. /*
  271. * HSMP_GET_METRIC_TABLE, num_args = 0, response_sz = 0
  272. */
  273. {0, 0, HSMP_GET},
  274. /*
  275. * HSMP_GET_METRIC_TABLE_DRAM_ADDR, num_args = 0, response_sz = 2
  276. * output: args[0] = lower 32 bits of the address
  277. * output: args[1] = upper 32 bits of the address
  278. */
  279. {0, 2, HSMP_GET},
  280. };
  281. /* Metrics table (supported only with proto version 6) */
  282. struct hsmp_metric_table {
  283. __u32 accumulation_counter;
  284. /* TEMPERATURE */
  285. __u32 max_socket_temperature;
  286. __u32 max_vr_temperature;
  287. __u32 max_hbm_temperature;
  288. __u64 max_socket_temperature_acc;
  289. __u64 max_vr_temperature_acc;
  290. __u64 max_hbm_temperature_acc;
  291. /* POWER */
  292. __u32 socket_power_limit;
  293. __u32 max_socket_power_limit;
  294. __u32 socket_power;
  295. /* ENERGY */
  296. __u64 timestamp;
  297. __u64 socket_energy_acc;
  298. __u64 ccd_energy_acc;
  299. __u64 xcd_energy_acc;
  300. __u64 aid_energy_acc;
  301. __u64 hbm_energy_acc;
  302. /* FREQUENCY */
  303. __u32 cclk_frequency_limit;
  304. __u32 gfxclk_frequency_limit;
  305. __u32 fclk_frequency;
  306. __u32 uclk_frequency;
  307. __u32 socclk_frequency[4];
  308. __u32 vclk_frequency[4];
  309. __u32 dclk_frequency[4];
  310. __u32 lclk_frequency[4];
  311. __u64 gfxclk_frequency_acc[8];
  312. __u64 cclk_frequency_acc[96];
  313. /* FREQUENCY RANGE */
  314. __u32 max_cclk_frequency;
  315. __u32 min_cclk_frequency;
  316. __u32 max_gfxclk_frequency;
  317. __u32 min_gfxclk_frequency;
  318. __u32 fclk_frequency_table[4];
  319. __u32 uclk_frequency_table[4];
  320. __u32 socclk_frequency_table[4];
  321. __u32 vclk_frequency_table[4];
  322. __u32 dclk_frequency_table[4];
  323. __u32 lclk_frequency_table[4];
  324. __u32 max_lclk_dpm_range;
  325. __u32 min_lclk_dpm_range;
  326. /* XGMI */
  327. __u32 xgmi_width;
  328. __u32 xgmi_bitrate;
  329. __u64 xgmi_read_bandwidth_acc[8];
  330. __u64 xgmi_write_bandwidth_acc[8];
  331. /* ACTIVITY */
  332. __u32 socket_c0_residency;
  333. __u32 socket_gfx_busy;
  334. __u32 dram_bandwidth_utilization;
  335. __u64 socket_c0_residency_acc;
  336. __u64 socket_gfx_busy_acc;
  337. __u64 dram_bandwidth_acc;
  338. __u32 max_dram_bandwidth;
  339. __u64 dram_bandwidth_utilization_acc;
  340. __u64 pcie_bandwidth_acc[4];
  341. /* THROTTLERS */
  342. __u32 prochot_residency_acc;
  343. __u32 ppt_residency_acc;
  344. __u32 socket_thm_residency_acc;
  345. __u32 vr_thm_residency_acc;
  346. __u32 hbm_thm_residency_acc;
  347. __u32 spare;
  348. /* New items at the end to maintain driver compatibility */
  349. __u32 gfxclk_frequency[8];
  350. };
  351. /* Reset to default packing */
  352. #pragma pack()
  353. /* Define unique ioctl command for hsmp msgs using generic _IOWR */
  354. #define HSMP_BASE_IOCTL_NR 0xF8
  355. #define HSMP_IOCTL_CMD _IOWR(HSMP_BASE_IOCTL_NR, 0, struct hsmp_message)
  356. #endif /*_ASM_X86_AMD_HSMP_H_*/