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deblob.patch (290298B)

    

  1. SPDX-FileCopyrightText: 2024 Gábor Stefanik <netrolller.3d@gmail.com>
  3. SPDX-License-Identifier: GPL-2.0-only
  5. Remove drivers containing embedded blobs
  7. diff -ruN ../linux-4.14.336/Documentation/networking/cops.txt ./Documentation/networking/cops.txt
  8. --- linux-4.14.336/../linux-4.14.336/Documentation/networking/cops.txt	2024-01-10 14:45:41.000000000 +0100
  9. +++ linux-4.14.336/./Documentation/networking/cops.txt	1970-01-01 01:00:00.000000000 +0100
  10. @@ -1,63 +0,0 @@
  11. -Text File for the COPS LocalTalk Linux driver (cops.c).
  12. -	By Jay Schulist <jschlst@samba.org>
  13. -
  14. -This driver has two modes and they are: Dayna mode and Tangent mode.
  15. -Each mode corresponds with the type of card. It has been found
  16. -that there are 2 main types of cards and all other cards are
  17. -the same and just have different names or only have minor differences
  18. -such as more IO ports. As this driver is tested it will
  19. -become more clear exactly what cards are supported. 
  20. -
  21. -Right now these cards are known to work with the COPS driver. The
  22. -LT-200 cards work in a somewhat more limited capacity than the
  23. -DL200 cards, which work very well and are in use by many people.
  24. -
  25. -TANGENT driver mode:
  26. -	Tangent ATB-II, Novell NL-1000, Daystar Digital LT-200
  27. -DAYNA driver mode:
  28. -	Dayna DL2000/DaynaTalk PC (Half Length), COPS LT-95,
  29. -	Farallon PhoneNET PC III, Farallon PhoneNET PC II
  30. -Other cards possibly supported mode unknown though:
  31. -	Dayna DL2000 (Full length)
  32. -
  33. -The COPS driver defaults to using Dayna mode. To change the driver's 
  34. -mode if you built a driver with dual support use board_type=1 or
  35. -board_type=2 for Dayna or Tangent with insmod.
  36. -
  37. -** Operation/loading of the driver.
  38. -Use modprobe like this:	/sbin/modprobe cops.o (IO #) (IRQ #)
  39. -If you do not specify any options the driver will try and use the IO = 0x240,
  40. -IRQ = 5. As of right now I would only use IRQ 5 for the card, if autoprobing.
  41. -
  42. -To load multiple COPS driver Localtalk cards you can do one of the following.
  43. -
  44. -insmod cops io=0x240 irq=5
  45. -insmod -o cops2 cops io=0x260 irq=3
  46. -
  47. -Or in lilo.conf put something like this:
  48. -	append="ether=5,0x240,lt0 ether=3,0x260,lt1"
  49. -
  50. -Then bring up the interface with ifconfig. It will look something like this:
  51. -lt0       Link encap:UNSPEC  HWaddr 00-00-00-00-00-00-00-F7-00-00-00-00-00-00-00-00
  52. -          inet addr:192.168.1.2  Bcast:192.168.1.255  Mask:255.255.255.0
  53. -          UP BROADCAST RUNNING NOARP MULTICAST  MTU:600  Metric:1
  54. -          RX packets:0 errors:0 dropped:0 overruns:0 frame:0
  55. -          TX packets:0 errors:0 dropped:0 overruns:0 carrier:0 coll:0
  56. -
  57. -** Netatalk Configuration
  58. -You will need to configure atalkd with something like the following to make
  59. -it work with the cops.c driver.
  60. -
  61. -* For single LTalk card use.
  62. -dummy -seed -phase 2 -net 2000 -addr 2000.10 -zone "1033"
  63. -lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
  64. -
  65. -* For multiple cards, Ethernet and LocalTalk.
  66. -eth0 -seed -phase 2 -net 3000 -addr 3000.20 -zone "1033"
  67. -lt0 -seed -phase 1 -net 1000 -addr 1000.50 -zone "1033"
  68. -
  69. -* For multiple LocalTalk cards, and an Ethernet card.
  70. -* Order seems to matter here, Ethernet last.
  71. -lt0 -seed -phase 1 -net 1000 -addr 1000.10 -zone "LocalTalk1"
  72. -lt1 -seed -phase 1 -net 2000 -addr 2000.20 -zone "LocalTalk2"
  73. -eth0 -seed -phase 2 -net 3000 -addr 3000.30 -zone "EtherTalk"
  74. diff -ruN ../linux-4.14.336/arch/powerpc/include/asm/cpm1.h ./arch/powerpc/include/asm/cpm1.h
  75. --- linux-4.14.336/../linux-4.14.336/arch/powerpc/include/asm/cpm1.h	2024-01-10 14:45:41.000000000 +0100
  76. +++ linux-4.14.336/./arch/powerpc/include/asm/cpm1.h	2024-02-14 20:39:09.131692114 +0100
  77. @@ -56,8 +56,6 @@
  78.  
  79.  extern void cpm_setbrg(uint brg, uint rate);
  80.  
  81. -extern void __init cpm_load_patch(cpm8xx_t *cp);
  82. -
  83.  extern void cpm_reset(void);
  84.  
  85.  /* Parameter RAM offsets.
  86. diff -ruN ../linux-4.14.336/arch/powerpc/platforms/8xx/Kconfig ./arch/powerpc/platforms/8xx/Kconfig
  87. --- linux-4.14.336/../linux-4.14.336/arch/powerpc/platforms/8xx/Kconfig	2024-01-10 14:45:41.000000000 +0100
  88. +++ linux-4.14.336/./arch/powerpc/platforms/8xx/Kconfig	2024-02-14 21:00:16.561611905 +0100
  89. @@ -145,35 +145,4 @@
  90.  
  91.  	  If in doubt, say Y here.
  92.  
  93. -choice
  94. -	prompt "Microcode patch selection"
  95. -	default NO_UCODE_PATCH
  96. -	help
  97. -	  Help not implemented yet, coming soon.
  98. -
  99. -config NO_UCODE_PATCH
  100. -	bool "None"
  101. -
  102. -config USB_SOF_UCODE_PATCH
  103. -	bool "USB SOF patch"
  104. -	help
  105. -	  Help not implemented yet, coming soon.
  106. -
  107. -config I2C_SPI_UCODE_PATCH
  108. -	bool "I2C/SPI relocation patch"
  109. -	help
  110. -	  Help not implemented yet, coming soon.
  111. -
  112. -config I2C_SPI_SMC1_UCODE_PATCH
  113. -	bool "I2C/SPI/SMC1 relocation patch"
  114. -	help
  115. -	  Help not implemented yet, coming soon.
  116. -
  117. -endchoice
  118. -
  119. -config UCODE_PATCH
  120. -	bool
  121. -	default y
  122. -	depends on !NO_UCODE_PATCH
  123. -
  124.  endmenu
  125. diff -ruN ../linux-4.14.336/arch/powerpc/sysdev/Makefile ./arch/powerpc/sysdev/Makefile
  126. --- linux-4.14.336/../linux-4.14.336/arch/powerpc/sysdev/Makefile	2024-01-10 14:45:41.000000000 +0100
  127. +++ linux-4.14.336/./arch/powerpc/sysdev/Makefile	2024-02-14 20:37:04.311700569 +0100
  128. @@ -46,7 +46,6 @@
  129.  obj-$(CONFIG_CPM2)		+= cpm2.o cpm2_pic.o
  130.  obj-$(CONFIG_QUICC_ENGINE)	+= cpm_common.o
  131.  obj-$(CONFIG_PPC_DCR)		+= dcr.o
  132. -obj-$(CONFIG_UCODE_PATCH)	+= micropatch.o
  133.  
  134.  obj-$(CONFIG_PPC_MPC512x)	+= mpc5xxx_clocks.o
  135.  obj-$(CONFIG_PPC_MPC52xx)	+= mpc5xxx_clocks.o
  136. diff -ruN ../linux-4.14.336/arch/powerpc/sysdev/cpm1.c ./arch/powerpc/sysdev/cpm1.c
  137. --- linux-4.14.336/../linux-4.14.336/arch/powerpc/sysdev/cpm1.c	2024-01-10 14:45:41.000000000 +0100
  138. +++ linux-4.14.336/./arch/powerpc/sysdev/cpm1.c	2024-02-14 20:38:38.041694200 +0100
  139. @@ -218,10 +218,6 @@
  140.  	while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
  141.  #endif
  142.  
  143. -#ifdef CONFIG_UCODE_PATCH
  144. -	cpm_load_patch(cpmp);
  145. -#endif
  146. -
  147.  	/* Set SDMA Bus Request priority 5.
  148.  	 * On 860T, this also enables FEC priority 6.  I am not sure
  149.  	 * this is what we really want for some applications, but the
  150. diff -ruN ../linux-4.14.336/arch/powerpc/sysdev/micropatch.c ./arch/powerpc/sysdev/micropatch.c
  151. --- linux-4.14.336/../linux-4.14.336/arch/powerpc/sysdev/micropatch.c	2024-01-10 14:45:41.000000000 +0100
  152. +++ linux-4.14.336/./arch/powerpc/sysdev/micropatch.c	1970-01-01 01:00:00.000000000 +0100
  153. @@ -1,749 +0,0 @@
  154. -// SPDX-License-Identifier: GPL-2.0
  155. -
  156. -/* Microcode patches for the CPM as supplied by Motorola.
  157. - * This is the one for IIC/SPI.  There is a newer one that
  158. - * also relocates SMC2, but this would require additional changes
  159. - * to uart.c, so I am holding off on that for a moment.
  160. - */
  161. -#include <linux/init.h>
  162. -#include <linux/errno.h>
  163. -#include <linux/sched.h>
  164. -#include <linux/kernel.h>
  165. -#include <linux/param.h>
  166. -#include <linux/string.h>
  167. -#include <linux/mm.h>
  168. -#include <linux/interrupt.h>
  169. -#include <asm/irq.h>
  170. -#include <asm/page.h>
  171. -#include <asm/pgtable.h>
  172. -#include <asm/8xx_immap.h>
  173. -#include <asm/cpm.h>
  174. -#include <asm/cpm1.h>
  175. -
  176. -/*
  177. - * I2C/SPI relocation patch arrays.
  178. - */
  179. -
  180. -#ifdef CONFIG_I2C_SPI_UCODE_PATCH
  181. -
  182. -static uint patch_2000[] __initdata = {
  183. -	0x7FFFEFD9,
  184. -	0x3FFD0000,
  185. -	0x7FFB49F7,
  186. -	0x7FF90000,
  187. -	0x5FEFADF7,
  188. -	0x5F89ADF7,
  189. -	0x5FEFAFF7,
  190. -	0x5F89AFF7,
  191. -	0x3A9CFBC8,
  192. -	0xE7C0EDF0,
  193. -	0x77C1E1BB,
  194. -	0xF4DC7F1D,
  195. -	0xABAD932F,
  196. -	0x4E08FDCF,
  197. -	0x6E0FAFF8,
  198. -	0x7CCF76CF,
  199. -	0xFD1FF9CF,
  200. -	0xABF88DC6,
  201. -	0xAB5679F7,
  202. -	0xB0937383,
  203. -	0xDFCE79F7,
  204. -	0xB091E6BB,
  205. -	0xE5BBE74F,
  206. -	0xB3FA6F0F,
  207. -	0x6FFB76CE,
  208. -	0xEE0DF9CF,
  209. -	0x2BFBEFEF,
  210. -	0xCFEEF9CF,
  211. -	0x76CEAD24,
  212. -	0x90B2DF9A,
  213. -	0x7FDDD0BF,
  214. -	0x4BF847FD,
  215. -	0x7CCF76CE,
  216. -	0xCFEF7E1F,
  217. -	0x7F1D7DFD,
  218. -	0xF0B6EF71,
  219. -	0x7FC177C1,
  220. -	0xFBC86079,
  221. -	0xE722FBC8,
  222. -	0x5FFFDFFF,
  223. -	0x5FB2FFFB,
  224. -	0xFBC8F3C8,
  225. -	0x94A67F01,
  226. -	0x7F1D5F39,
  227. -	0xAFE85F5E,
  228. -	0xFFDFDF96,
  229. -	0xCB9FAF7D,
  230. -	0x5FC1AFED,
  231. -	0x8C1C5FC1,
  232. -	0xAFDD5FC3,
  233. -	0xDF9A7EFD,
  234. -	0xB0B25FB2,
  235. -	0xFFFEABAD,
  236. -	0x5FB2FFFE,
  237. -	0x5FCE600B,
  238. -	0xE6BB600B,
  239. -	0x5FCEDFC6,
  240. -	0x27FBEFDF,
  241. -	0x5FC8CFDE,
  242. -	0x3A9CE7C0,
  243. -	0xEDF0F3C8,
  244. -	0x7F0154CD,
  245. -	0x7F1D2D3D,
  246. -	0x363A7570,
  247. -	0x7E0AF1CE,
  248. -	0x37EF2E68,
  249. -	0x7FEE10EC,
  250. -	0xADF8EFDE,
  251. -	0xCFEAE52F,
  252. -	0x7D0FE12B,
  253. -	0xF1CE5F65,
  254. -	0x7E0A4DF8,
  255. -	0xCFEA5F72,
  256. -	0x7D0BEFEE,
  257. -	0xCFEA5F74,
  258. -	0xE522EFDE,
  259. -	0x5F74CFDA,
  260. -	0x0B627385,
  261. -	0xDF627E0A,
  262. -	0x30D8145B,
  263. -	0xBFFFF3C8,
  264. -	0x5FFFDFFF,
  265. -	0xA7F85F5E,
  266. -	0xBFFE7F7D,
  267. -	0x10D31450,
  268. -	0x5F36BFFF,
  269. -	0xAF785F5E,
  270. -	0xBFFDA7F8,
  271. -	0x5F36BFFE,
  272. -	0x77FD30C0,
  273. -	0x4E08FDCF,
  274. -	0xE5FF6E0F,
  275. -	0xAFF87E1F,
  276. -	0x7E0FFD1F,
  277. -	0xF1CF5F1B,
  278. -	0xABF80D5E,
  279. -	0x5F5EFFEF,
  280. -	0x79F730A2,
  281. -	0xAFDD5F34,
  282. -	0x47F85F34,
  283. -	0xAFED7FDD,
  284. -	0x50B24978,
  285. -	0x47FD7F1D,
  286. -	0x7DFD70AD,
  287. -	0xEF717EC1,
  288. -	0x6BA47F01,
  289. -	0x2D267EFD,
  290. -	0x30DE5F5E,
  291. -	0xFFFD5F5E,
  292. -	0xFFEF5F5E,
  293. -	0xFFDF0CA0,
  294. -	0xAFED0A9E,
  295. -	0xAFDD0C3A,
  296. -	0x5F3AAFBD,
  297. -	0x7FBDB082,
  298. -	0x5F8247F8
  299. -};
  300. -
  301. -static uint patch_2f00[] __initdata = {
  302. -	0x3E303430,
  303. -	0x34343737,
  304. -	0xABF7BF9B,
  305. -	0x994B4FBD,
  306. -	0xBD599493,
  307. -	0x349FFF37,
  308. -	0xFB9B177D,
  309. -	0xD9936956,
  310. -	0xBBFDD697,
  311. -	0xBDD2FD11,
  312. -	0x31DB9BB3,
  313. -	0x63139637,
  314. -	0x93733693,
  315. -	0x193137F7,
  316. -	0x331737AF,
  317. -	0x7BB9B999,
  318. -	0xBB197957,
  319. -	0x7FDFD3D5,
  320. -	0x73B773F7,
  321. -	0x37933B99,
  322. -	0x1D115316,
  323. -	0x99315315,
  324. -	0x31694BF4,
  325. -	0xFBDBD359,
  326. -	0x31497353,
  327. -	0x76956D69,
  328. -	0x7B9D9693,
  329. -	0x13131979,
  330. -	0x79376935
  331. -};
  332. -#endif
  333. -
  334. -/*
  335. - * I2C/SPI/SMC1 relocation patch arrays.
  336. - */
  337. -
  338. -#ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
  339. -
  340. -static uint patch_2000[] __initdata = {
  341. -	0x3fff0000,
  342. -	0x3ffd0000,
  343. -	0x3ffb0000,
  344. -	0x3ff90000,
  345. -	0x5f13eff8,
  346. -	0x5eb5eff8,
  347. -	0x5f88adf7,
  348. -	0x5fefadf7,
  349. -	0x3a9cfbc8,
  350. -	0x77cae1bb,
  351. -	0xf4de7fad,
  352. -	0xabae9330,
  353. -	0x4e08fdcf,
  354. -	0x6e0faff8,
  355. -	0x7ccf76cf,
  356. -	0xfdaff9cf,
  357. -	0xabf88dc8,
  358. -	0xab5879f7,
  359. -	0xb0925d8d,
  360. -	0xdfd079f7,
  361. -	0xb090e6bb,
  362. -	0xe5bbe74f,
  363. -	0x9e046f0f,
  364. -	0x6ffb76ce,
  365. -	0xee0cf9cf,
  366. -	0x2bfbefef,
  367. -	0xcfeef9cf,
  368. -	0x76cead23,
  369. -	0x90b3df99,
  370. -	0x7fddd0c1,
  371. -	0x4bf847fd,
  372. -	0x7ccf76ce,
  373. -	0xcfef77ca,
  374. -	0x7eaf7fad,
  375. -	0x7dfdf0b7,
  376. -	0xef7a7fca,
  377. -	0x77cafbc8,
  378. -	0x6079e722,
  379. -	0xfbc85fff,
  380. -	0xdfff5fb3,
  381. -	0xfffbfbc8,
  382. -	0xf3c894a5,
  383. -	0xe7c9edf9,
  384. -	0x7f9a7fad,
  385. -	0x5f36afe8,
  386. -	0x5f5bffdf,
  387. -	0xdf95cb9e,
  388. -	0xaf7d5fc3,
  389. -	0xafed8c1b,
  390. -	0x5fc3afdd,
  391. -	0x5fc5df99,
  392. -	0x7efdb0b3,
  393. -	0x5fb3fffe,
  394. -	0xabae5fb3,
  395. -	0xfffe5fd0,
  396. -	0x600be6bb,
  397. -	0x600b5fd0,
  398. -	0xdfc827fb,
  399. -	0xefdf5fca,
  400. -	0xcfde3a9c,
  401. -	0xe7c9edf9,
  402. -	0xf3c87f9e,
  403. -	0x54ca7fed,
  404. -	0x2d3a3637,
  405. -	0x756f7e9a,
  406. -	0xf1ce37ef,
  407. -	0x2e677fee,
  408. -	0x10ebadf8,
  409. -	0xefdecfea,
  410. -	0xe52f7d9f,
  411. -	0xe12bf1ce,
  412. -	0x5f647e9a,
  413. -	0x4df8cfea,
  414. -	0x5f717d9b,
  415. -	0xefeecfea,
  416. -	0x5f73e522,
  417. -	0xefde5f73,
  418. -	0xcfda0b61,
  419. -	0x5d8fdf61,
  420. -	0xe7c9edf9,
  421. -	0x7e9a30d5,
  422. -	0x1458bfff,
  423. -	0xf3c85fff,
  424. -	0xdfffa7f8,
  425. -	0x5f5bbffe,
  426. -	0x7f7d10d0,
  427. -	0x144d5f33,
  428. -	0xbfffaf78,
  429. -	0x5f5bbffd,
  430. -	0xa7f85f33,
  431. -	0xbffe77fd,
  432. -	0x30bd4e08,
  433. -	0xfdcfe5ff,
  434. -	0x6e0faff8,
  435. -	0x7eef7e9f,
  436. -	0xfdeff1cf,
  437. -	0x5f17abf8,
  438. -	0x0d5b5f5b,
  439. -	0xffef79f7,
  440. -	0x309eafdd,
  441. -	0x5f3147f8,
  442. -	0x5f31afed,
  443. -	0x7fdd50af,
  444. -	0x497847fd,
  445. -	0x7f9e7fed,
  446. -	0x7dfd70a9,
  447. -	0xef7e7ece,
  448. -	0x6ba07f9e,
  449. -	0x2d227efd,
  450. -	0x30db5f5b,
  451. -	0xfffd5f5b,
  452. -	0xffef5f5b,
  453. -	0xffdf0c9c,
  454. -	0xafed0a9a,
  455. -	0xafdd0c37,
  456. -	0x5f37afbd,
  457. -	0x7fbdb081,
  458. -	0x5f8147f8,
  459. -	0x3a11e710,
  460. -	0xedf0ccdd,
  461. -	0xf3186d0a,
  462. -	0x7f0e5f06,
  463. -	0x7fedbb38,
  464. -	0x3afe7468,
  465. -	0x7fedf4fc,
  466. -	0x8ffbb951,
  467. -	0xb85f77fd,
  468. -	0xb0df5ddd,
  469. -	0xdefe7fed,
  470. -	0x90e1e74d,
  471. -	0x6f0dcbf7,
  472. -	0xe7decfed,
  473. -	0xcb74cfed,
  474. -	0xcfeddf6d,
  475. -	0x91714f74,
  476. -	0x5dd2deef,
  477. -	0x9e04e7df,
  478. -	0xefbb6ffb,
  479. -	0xe7ef7f0e,
  480. -	0x9e097fed,
  481. -	0xebdbeffa,
  482. -	0xeb54affb,
  483. -	0x7fea90d7,
  484. -	0x7e0cf0c3,
  485. -	0xbffff318,
  486. -	0x5fffdfff,
  487. -	0xac59efea,
  488. -	0x7fce1ee5,
  489. -	0xe2ff5ee1,
  490. -	0xaffbe2ff,
  491. -	0x5ee3affb,
  492. -	0xf9cc7d0f,
  493. -	0xaef8770f,
  494. -	0x7d0fb0c6,
  495. -	0xeffbbfff,
  496. -	0xcfef5ede,
  497. -	0x7d0fbfff,
  498. -	0x5ede4cf8,
  499. -	0x7fddd0bf,
  500. -	0x49f847fd,
  501. -	0x7efdf0bb,
  502. -	0x7fedfffd,
  503. -	0x7dfdf0b7,
  504. -	0xef7e7e1e,
  505. -	0x5ede7f0e,
  506. -	0x3a11e710,
  507. -	0xedf0ccab,
  508. -	0xfb18ad2e,
  509. -	0x1ea9bbb8,
  510. -	0x74283b7e,
  511. -	0x73c2e4bb,
  512. -	0x2ada4fb8,
  513. -	0xdc21e4bb,
  514. -	0xb2a1ffbf,
  515. -	0x5e2c43f8,
  516. -	0xfc87e1bb,
  517. -	0xe74ffd91,
  518. -	0x6f0f4fe8,
  519. -	0xc7ba32e2,
  520. -	0xf396efeb,
  521. -	0x600b4f78,
  522. -	0xe5bb760b,
  523. -	0x53acaef8,
  524. -	0x4ef88b0e,
  525. -	0xcfef9e09,
  526. -	0xabf8751f,
  527. -	0xefef5bac,
  528. -	0x741f4fe8,
  529. -	0x751e760d,
  530. -	0x7fdbf081,
  531. -	0x741cafce,
  532. -	0xefcc7fce,
  533. -	0x751e70ac,
  534. -	0x741ce7bb,
  535. -	0x3372cfed,
  536. -	0xafdbefeb,
  537. -	0xe5bb760b,
  538. -	0x53f2aef8,
  539. -	0xafe8e7eb,
  540. -	0x4bf8771e,
  541. -	0x7e247fed,
  542. -	0x4fcbe2cc,
  543. -	0x7fbc30a9,
  544. -	0x7b0f7a0f,
  545. -	0x34d577fd,
  546. -	0x308b5db7,
  547. -	0xde553e5f,
  548. -	0xaf78741f,
  549. -	0x741f30f0,
  550. -	0xcfef5e2c,
  551. -	0x741f3eac,
  552. -	0xafb8771e,
  553. -	0x5e677fed,
  554. -	0x0bd3e2cc,
  555. -	0x741ccfec,
  556. -	0xe5ca53cd,
  557. -	0x6fcb4f74,
  558. -	0x5dadde4b,
  559. -	0x2ab63d38,
  560. -	0x4bb3de30,
  561. -	0x751f741c,
  562. -	0x6c42effa,
  563. -	0xefea7fce,
  564. -	0x6ffc30be,
  565. -	0xefec3fca,
  566. -	0x30b3de2e,
  567. -	0xadf85d9e,
  568. -	0xaf7daefd,
  569. -	0x5d9ede2e,
  570. -	0x5d9eafdd,
  571. -	0x761f10ac,
  572. -	0x1da07efd,
  573. -	0x30adfffe,
  574. -	0x4908fb18,
  575. -	0x5fffdfff,
  576. -	0xafbb709b,
  577. -	0x4ef85e67,
  578. -	0xadf814ad,
  579. -	0x7a0f70ad,
  580. -	0xcfef50ad,
  581. -	0x7a0fde30,
  582. -	0x5da0afed,
  583. -	0x3c12780f,
  584. -	0xefef780f,
  585. -	0xefef790f,
  586. -	0xa7f85e0f,
  587. -	0xffef790f,
  588. -	0xefef790f,
  589. -	0x14adde2e,
  590. -	0x5d9eadfd,
  591. -	0x5e2dfffb,
  592. -	0xe79addfd,
  593. -	0xeff96079,
  594. -	0x607ae79a,
  595. -	0xddfceff9,
  596. -	0x60795dff,
  597. -	0x607acfef,
  598. -	0xefefefdf,
  599. -	0xefbfef7f,
  600. -	0xeeffedff,
  601. -	0xebffe7ff,
  602. -	0xafefafdf,
  603. -	0xafbfaf7f,
  604. -	0xaeffadff,
  605. -	0xabffa7ff,
  606. -	0x6fef6fdf,
  607. -	0x6fbf6f7f,
  608. -	0x6eff6dff,
  609. -	0x6bff67ff,
  610. -	0x2fef2fdf,
  611. -	0x2fbf2f7f,
  612. -	0x2eff2dff,
  613. -	0x2bff27ff,
  614. -	0x4e08fd1f,
  615. -	0xe5ff6e0f,
  616. -	0xaff87eef,
  617. -	0x7e0ffdef,
  618. -	0xf11f6079,
  619. -	0xabf8f542,
  620. -	0x7e0af11c,
  621. -	0x37cfae3a,
  622. -	0x7fec90be,
  623. -	0xadf8efdc,
  624. -	0xcfeae52f,
  625. -	0x7d0fe12b,
  626. -	0xf11c6079,
  627. -	0x7e0a4df8,
  628. -	0xcfea5dc4,
  629. -	0x7d0befec,
  630. -	0xcfea5dc6,
  631. -	0xe522efdc,
  632. -	0x5dc6cfda,
  633. -	0x4e08fd1f,
  634. -	0x6e0faff8,
  635. -	0x7c1f761f,
  636. -	0xfdeff91f,
  637. -	0x6079abf8,
  638. -	0x761cee24,
  639. -	0xf91f2bfb,
  640. -	0xefefcfec,
  641. -	0xf91f6079,
  642. -	0x761c27fb,
  643. -	0xefdf5da7,
  644. -	0xcfdc7fdd,
  645. -	0xd09c4bf8,
  646. -	0x47fd7c1f,
  647. -	0x761ccfcf,
  648. -	0x7eef7fed,
  649. -	0x7dfdf093,
  650. -	0xef7e7f1e,
  651. -	0x771efb18,
  652. -	0x6079e722,
  653. -	0xe6bbe5bb,
  654. -	0xae0ae5bb,
  655. -	0x600bae85,
  656. -	0xe2bbe2bb,
  657. -	0xe2bbe2bb,
  658. -	0xaf02e2bb,
  659. -	0xe2bb2ff9,
  660. -	0x6079e2bb
  661. -};
  662. -
  663. -static uint patch_2f00[] __initdata = {
  664. -	0x30303030,
  665. -	0x3e3e3434,
  666. -	0xabbf9b99,
  667. -	0x4b4fbdbd,
  668. -	0x59949334,
  669. -	0x9fff37fb,
  670. -	0x9b177dd9,
  671. -	0x936956bb,
  672. -	0xfbdd697b,
  673. -	0xdd2fd113,
  674. -	0x1db9f7bb,
  675. -	0x36313963,
  676. -	0x79373369,
  677. -	0x3193137f,
  678. -	0x7331737a,
  679. -	0xf7bb9b99,
  680. -	0x9bb19795,
  681. -	0x77fdfd3d,
  682. -	0x573b773f,
  683. -	0x737933f7,
  684. -	0xb991d115,
  685. -	0x31699315,
  686. -	0x31531694,
  687. -	0xbf4fbdbd,
  688. -	0x35931497,
  689. -	0x35376956,
  690. -	0xbd697b9d,
  691. -	0x96931313,
  692. -	0x19797937,
  693. -	0x6935af78,
  694. -	0xb9b3baa3,
  695. -	0xb8788683,
  696. -	0x368f78f7,
  697. -	0x87778733,
  698. -	0x3ffffb3b,
  699. -	0x8e8f78b8,
  700. -	0x1d118e13,
  701. -	0xf3ff3f8b,
  702. -	0x6bd8e173,
  703. -	0xd1366856,
  704. -	0x68d1687b,
  705. -	0x3daf78b8,
  706. -	0x3a3a3f87,
  707. -	0x8f81378f,
  708. -	0xf876f887,
  709. -	0x77fd8778,
  710. -	0x737de8d6,
  711. -	0xbbf8bfff,
  712. -	0xd8df87f7,
  713. -	0xfd876f7b,
  714. -	0x8bfff8bd,
  715. -	0x8683387d,
  716. -	0xb873d87b,
  717. -	0x3b8fd7f8,
  718. -	0xf7338883,
  719. -	0xbb8ee1f8,
  720. -	0xef837377,
  721. -	0x3337b836,
  722. -	0x817d11f8,
  723. -	0x7378b878,
  724. -	0xd3368b7d,
  725. -	0xed731b7d,
  726. -	0x833731f3,
  727. -	0xf22f3f23
  728. -};
  729. -
  730. -static uint patch_2e00[] __initdata = {
  731. -	0x27eeeeee,
  732. -	0xeeeeeeee,
  733. -	0xeeeeeeee,
  734. -	0xeeeeeeee,
  735. -	0xee4bf4fb,
  736. -	0xdbd259bb,
  737. -	0x1979577f,
  738. -	0xdfd2d573,
  739. -	0xb773f737,
  740. -	0x4b4fbdbd,
  741. -	0x25b9b177,
  742. -	0xd2d17376,
  743. -	0x956bbfdd,
  744. -	0x697bdd2f,
  745. -	0xff9f79ff,
  746. -	0xff9ff22f
  747. -};
  748. -#endif
  749. -
  750. -/*
  751. - *  USB SOF patch arrays.
  752. - */
  753. -
  754. -#ifdef CONFIG_USB_SOF_UCODE_PATCH
  755. -
  756. -static uint patch_2000[] __initdata = {
  757. -	0x7fff0000,
  758. -	0x7ffd0000,
  759. -	0x7ffb0000,
  760. -	0x49f7ba5b,
  761. -	0xba383ffb,
  762. -	0xf9b8b46d,
  763. -	0xe5ab4e07,
  764. -	0xaf77bffe,
  765. -	0x3f7bbf79,
  766. -	0xba5bba38,
  767. -	0xe7676076,
  768. -	0x60750000
  769. -};
  770. -
  771. -static uint patch_2f00[] __initdata = {
  772. -	0x3030304c,
  773. -	0xcab9e441,
  774. -	0xa1aaf220
  775. -};
  776. -#endif
  777. -
  778. -void __init cpm_load_patch(cpm8xx_t *cp)
  779. -{
  780. -	volatile uint		*dp;		/* Dual-ported RAM. */
  781. -	volatile cpm8xx_t	*commproc;
  782. -#if defined(CONFIG_I2C_SPI_UCODE_PATCH) || \
  783. -    defined(CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
  784. -	volatile iic_t		*iip;
  785. -	volatile struct spi_pram *spp;
  786. -#ifdef CONFIG_I2C_SPI_SMC1_UCODE_PATCH
  787. -	volatile smc_uart_t	*smp;
  788. -#endif
  789. -#endif
  790. -	int	i;
  791. -
  792. -	commproc = cp;
  793. -
  794. -#ifdef CONFIG_USB_SOF_UCODE_PATCH
  795. -	commproc->cp_rccr = 0;
  796. -
  797. -	dp = (uint *)(commproc->cp_dpmem);
  798. -	for (i=0; i<(sizeof(patch_2000)/4); i++)
  799. -		*dp++ = patch_2000[i];
  800. -
  801. -	dp = (uint *)&(commproc->cp_dpmem[0x0f00]);
  802. -	for (i=0; i<(sizeof(patch_2f00)/4); i++)
  803. -		*dp++ = patch_2f00[i];
  804. -
  805. -	commproc->cp_rccr = 0x0009;
  806. -
  807. -	printk("USB SOF microcode patch installed\n");
  808. -#endif /* CONFIG_USB_SOF_UCODE_PATCH */
  809. -
  810. -#if defined(CONFIG_I2C_SPI_UCODE_PATCH) || \
  811. -    defined(CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
  812. -
  813. -	commproc->cp_rccr = 0;
  814. -
  815. -	dp = (uint *)(commproc->cp_dpmem);
  816. -	for (i=0; i<(sizeof(patch_2000)/4); i++)
  817. -		*dp++ = patch_2000[i];
  818. -
  819. -	dp = (uint *)&(commproc->cp_dpmem[0x0f00]);
  820. -	for (i=0; i<(sizeof(patch_2f00)/4); i++)
  821. -		*dp++ = patch_2f00[i];
  822. -
  823. -	iip = (iic_t *)&commproc->cp_dparam[PROFF_IIC];
  824. -# define RPBASE 0x0500
  825. -	iip->iic_rpbase = RPBASE;
  826. -
  827. -	/* Put SPI above the IIC, also 32-byte aligned.
  828. -	*/
  829. -	i = (RPBASE + sizeof(iic_t) + 31) & ~31;
  830. -	spp = (struct spi_pram *)&commproc->cp_dparam[PROFF_SPI];
  831. -	spp->rpbase = i;
  832. -
  833. -# if defined(CONFIG_I2C_SPI_UCODE_PATCH)
  834. -	commproc->cp_cpmcr1 = 0x802a;
  835. -	commproc->cp_cpmcr2 = 0x8028;
  836. -	commproc->cp_cpmcr3 = 0x802e;
  837. -	commproc->cp_cpmcr4 = 0x802c;
  838. -	commproc->cp_rccr = 1;
  839. -
  840. -	printk("I2C/SPI microcode patch installed.\n");
  841. -# endif /* CONFIG_I2C_SPI_UCODE_PATCH */
  842. -
  843. -# if defined(CONFIG_I2C_SPI_SMC1_UCODE_PATCH)
  844. -
  845. -	dp = (uint *)&(commproc->cp_dpmem[0x0e00]);
  846. -	for (i=0; i<(sizeof(patch_2e00)/4); i++)
  847. -		*dp++ = patch_2e00[i];
  848. -
  849. -	commproc->cp_cpmcr1 = 0x8080;
  850. -	commproc->cp_cpmcr2 = 0x808a;
  851. -	commproc->cp_cpmcr3 = 0x8028;
  852. -	commproc->cp_cpmcr4 = 0x802a;
  853. -	commproc->cp_rccr = 3;
  854. -
  855. -	smp = (smc_uart_t *)&commproc->cp_dparam[PROFF_SMC1];
  856. -	smp->smc_rpbase = 0x1FC0;
  857. -
  858. -	printk("I2C/SPI/SMC1 microcode patch installed.\n");
  859. -# endif /* CONFIG_I2C_SPI_SMC1_UCODE_PATCH) */
  860. -
  861. -#endif /* some variation of the I2C/SPI patch was selected */
  862. -}
  863. -
  864. -/*
  865. - *  Take this entire routine out, since no one calls it and its
  866. - * logic is suspect.
  867. - */
  868. -
  869. -#if 0
  870. -void
  871. -verify_patch(volatile immap_t *immr)
  872. -{
  873. -	volatile uint		*dp;
  874. -	volatile cpm8xx_t	*commproc;
  875. -	int i;
  876. -
  877. -	commproc = (cpm8xx_t *)&immr->im_cpm;
  878. -
  879. -	printk("cp_rccr %x\n", commproc->cp_rccr);
  880. -	commproc->cp_rccr = 0;
  881. -
  882. -	dp = (uint *)(commproc->cp_dpmem);
  883. -	for (i=0; i<(sizeof(patch_2000)/4); i++)
  884. -		if (*dp++ != patch_2000[i]) {
  885. -			printk("patch_2000 bad at %d\n", i);
  886. -			dp--;
  887. -			printk("found 0x%X, wanted 0x%X\n", *dp, patch_2000[i]);
  888. -			break;
  889. -		}
  890. -
  891. -	dp = (uint *)&(commproc->cp_dpmem[0x0f00]);
  892. -	for (i=0; i<(sizeof(patch_2f00)/4); i++)
  893. -		if (*dp++ != patch_2f00[i]) {
  894. -			printk("patch_2f00 bad at %d\n", i);
  895. -			dp--;
  896. -			printk("found 0x%X, wanted 0x%X\n", *dp, patch_2f00[i]);
  897. -			break;
  898. -		}
  899. -
  900. -	commproc->cp_rccr = 0x0009;
  901. -}
  902. -#endif
  903. diff -ruN ../linux-4.14.336/drivers/i2c/busses/i2c-cpm.c ./drivers/i2c/busses/i2c-cpm.c
  904. --- linux-4.14.336/../linux-4.14.336/drivers/i2c/busses/i2c-cpm.c	2024-01-10 14:45:41.000000000 +0100
  905. +++ linux-4.14.336/./drivers/i2c/busses/i2c-cpm.c	2024-02-14 20:42:10.901680998 +0100
  906. @@ -461,20 +461,9 @@
  907.  	}
  908.  
  909.  	if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm1-i2c")) {
  910. -
  911. -		/* Check for and use a microcode relocation patch. */
  912.  		cpm->i2c_ram = i2c_base;
  913.  		cpm->i2c_addr = in_be16(&cpm->i2c_ram->rpbase);
  914.  
  915. -		/*
  916. -		 * Maybe should use cpm_muram_alloc instead of hardcoding
  917. -		 * this in micropatch.c
  918. -		 */
  919. -		if (cpm->i2c_addr) {
  920. -			cpm->i2c_ram = cpm_muram_addr(cpm->i2c_addr);
  921. -			iounmap(i2c_base);
  922. -		}
  923. -
  924.  		cpm->version = 1;
  925.  
  926.  	} else if (of_device_is_compatible(ofdev->dev.of_node, "fsl,cpm2-i2c")) {
  927. diff -ruN ../linux-4.14.336/drivers/media/usb/dvb-usb/Kconfig ./drivers/media/usb/dvb-usb/Kconfig
  928. --- linux-4.14.336/../linux-4.14.336/drivers/media/usb/dvb-usb/Kconfig	2024-01-10 14:45:41.000000000 +0100
  929. +++ linux-4.14.336/./drivers/media/usb/dvb-usb/Kconfig	2024-02-14 21:41:13.341455995 +0100
  930. @@ -242,22 +242,6 @@
  931.  	help
  932.  	  Say Y here to support the Opera DVB-S USB2.0 receiver.
  933.  
  934. -config DVB_USB_AF9005
  935. -	tristate "Afatech AF9005 DVB-T USB1.1 support"
  936. -	depends on DVB_USB
  937. -	select MEDIA_TUNER_MT2060 if MEDIA_SUBDRV_AUTOSELECT
  938. -	select MEDIA_TUNER_QT1010 if MEDIA_SUBDRV_AUTOSELECT
  939. -	help
  940. -	  Say Y here to support the Afatech AF9005 based DVB-T USB1.1 receiver
  941. -	  and the TerraTec Cinergy T USB XE (Rev.1)
  942. -
  943. -config DVB_USB_AF9005_REMOTE
  944. -	tristate "Afatech AF9005 default remote control support"
  945. -	depends on DVB_USB_AF9005
  946. -	help
  947. -	  Say Y here to support the default remote control decoding for the
  948. -	  Afatech AF9005 based receiver.
  949. -
  950.  config DVB_USB_PCTV452E
  951.  	tristate "Pinnacle PCTV HDTV Pro USB device/TT Connect S2-3600"
  952.  	depends on DVB_USB
  953. diff -ruN ../linux-4.14.336/drivers/media/usb/dvb-usb/Makefile ./drivers/media/usb/dvb-usb/Makefile
  954. --- linux-4.14.336/../linux-4.14.336/drivers/media/usb/dvb-usb/Makefile	2024-01-10 14:45:41.000000000 +0100
  955. +++ linux-4.14.336/./drivers/media/usb/dvb-usb/Makefile	2024-02-14 21:40:58.271457116 +0100
  956. @@ -53,12 +53,6 @@
  957.  dvb-usb-opera-objs := opera1.o
  958.  obj-$(CONFIG_DVB_USB_OPERA1) += dvb-usb-opera.o
  959.  
  960. -dvb-usb-af9005-objs := af9005.o af9005-fe.o
  961. -obj-$(CONFIG_DVB_USB_AF9005) += dvb-usb-af9005.o
  962. -
  963. -dvb-usb-af9005-remote-objs := af9005-remote.o
  964. -obj-$(CONFIG_DVB_USB_AF9005_REMOTE) += dvb-usb-af9005-remote.o
  965. -
  966.  dvb-usb-pctv452e-objs := pctv452e.o
  967.  obj-$(CONFIG_DVB_USB_PCTV452E) += dvb-usb-pctv452e.o
  968.  
  969. diff -ruN ../linux-4.14.336/drivers/media/usb/dvb-usb/af9005-fe.c ./drivers/media/usb/dvb-usb/af9005-fe.c
  970. --- linux-4.14.336/../linux-4.14.336/drivers/media/usb/dvb-usb/af9005-fe.c	2024-01-10 14:45:41.000000000 +0100
  971. +++ linux-4.14.336/./drivers/media/usb/dvb-usb/af9005-fe.c	1970-01-01 01:00:00.000000000 +0100
  972. @@ -1,1484 +0,0 @@
  973. -/* Frontend part of the Linux driver for the Afatech 9005
  974. - * USB1.1 DVB-T receiver.
  975. - *
  976. - * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
  977. - *
  978. - * Thanks to Afatech who kindly provided information.
  979. - *
  980. - * This program is free software; you can redistribute it and/or modify
  981. - * it under the terms of the GNU General Public License as published by
  982. - * the Free Software Foundation; either version 2 of the License, or
  983. - * (at your option) any later version.
  984. - *
  985. - * This program is distributed in the hope that it will be useful,
  986. - * but WITHOUT ANY WARRANTY; without even the implied warranty of
  987. - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  988. - * GNU General Public License for more details.
  989. - *
  990. - * see Documentation/dvb/README.dvb-usb for more information
  991. - */
  992. -#include "af9005.h"
  993. -#include "af9005-script.h"
  994. -#include "mt2060.h"
  995. -#include "qt1010.h"
  996. -#include <asm/div64.h>
  997. -
  998. -struct af9005_fe_state {
  999. -	struct dvb_usb_device *d;
  1000. -	enum fe_status stat;
  1001. -
  1002. -	/* retraining parameters */
  1003. -	u32 original_fcw;
  1004. -	u16 original_rf_top;
  1005. -	u16 original_if_top;
  1006. -	u16 original_if_min;
  1007. -	u16 original_aci0_if_top;
  1008. -	u16 original_aci1_if_top;
  1009. -	u16 original_aci0_if_min;
  1010. -	u8 original_if_unplug_th;
  1011. -	u8 original_rf_unplug_th;
  1012. -	u8 original_dtop_if_unplug_th;
  1013. -	u8 original_dtop_rf_unplug_th;
  1014. -
  1015. -	/* statistics */
  1016. -	u32 pre_vit_error_count;
  1017. -	u32 pre_vit_bit_count;
  1018. -	u32 ber;
  1019. -	u32 post_vit_error_count;
  1020. -	u32 post_vit_bit_count;
  1021. -	u32 unc;
  1022. -	u16 abort_count;
  1023. -
  1024. -	int opened;
  1025. -	int strong;
  1026. -	unsigned long next_status_check;
  1027. -	struct dvb_frontend frontend;
  1028. -};
  1029. -
  1030. -static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
  1031. -				 u16 reglo, u8 pos, u8 len, u16 value)
  1032. -{
  1033. -	int ret;
  1034. -
  1035. -	if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
  1036. -		return ret;
  1037. -	return af9005_write_register_bits(d, reghi, pos, len,
  1038. -					  (u8) ((value & 0x300) >> 8));
  1039. -}
  1040. -
  1041. -static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
  1042. -				u16 reglo, u8 pos, u8 len, u16 * value)
  1043. -{
  1044. -	int ret;
  1045. -	u8 temp0, temp1;
  1046. -
  1047. -	if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
  1048. -		return ret;
  1049. -	if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
  1050. -		return ret;
  1051. -	switch (pos) {
  1052. -	case 0:
  1053. -		*value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
  1054. -		break;
  1055. -	case 2:
  1056. -		*value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
  1057. -		break;
  1058. -	case 4:
  1059. -		*value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
  1060. -		break;
  1061. -	case 6:
  1062. -		*value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
  1063. -		break;
  1064. -	default:
  1065. -		err("invalid pos in read word agc");
  1066. -		return -EINVAL;
  1067. -	}
  1068. -	return 0;
  1069. -
  1070. -}
  1071. -
  1072. -static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
  1073. -{
  1074. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1075. -	int ret;
  1076. -	u8 temp;
  1077. -
  1078. -	*available = false;
  1079. -
  1080. -	ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
  1081. -					fec_vtb_rsd_mon_en_pos,
  1082. -					fec_vtb_rsd_mon_en_len, &temp);
  1083. -	if (ret)
  1084. -		return ret;
  1085. -	if (temp & 1) {
  1086. -		ret =
  1087. -		    af9005_read_register_bits(state->d,
  1088. -					      xd_p_reg_ofsm_read_rbc_en,
  1089. -					      reg_ofsm_read_rbc_en_pos,
  1090. -					      reg_ofsm_read_rbc_en_len, &temp);
  1091. -		if (ret)
  1092. -			return ret;
  1093. -		if ((temp & 1) == 0)
  1094. -			*available = true;
  1095. -
  1096. -	}
  1097. -	return 0;
  1098. -}
  1099. -
  1100. -static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
  1101. -					    u32 * post_err_count,
  1102. -					    u32 * post_cw_count,
  1103. -					    u16 * abort_count)
  1104. -{
  1105. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1106. -	int ret;
  1107. -	u32 err_count;
  1108. -	u32 cw_count;
  1109. -	u8 temp, temp0, temp1, temp2;
  1110. -	u16 loc_abort_count;
  1111. -
  1112. -	*post_err_count = 0;
  1113. -	*post_cw_count = 0;
  1114. -
  1115. -	/* check if error bit count is ready */
  1116. -	ret =
  1117. -	    af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
  1118. -				      fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
  1119. -				      &temp);
  1120. -	if (ret)
  1121. -		return ret;
  1122. -	if (!temp) {
  1123. -		deb_info("rsd counter not ready\n");
  1124. -		return 100;
  1125. -	}
  1126. -	/* get abort count */
  1127. -	ret =
  1128. -	    af9005_read_ofdm_register(state->d,
  1129. -				      xd_r_fec_rsd_abort_packet_cnt_7_0,
  1130. -				      &temp0);
  1131. -	if (ret)
  1132. -		return ret;
  1133. -	ret =
  1134. -	    af9005_read_ofdm_register(state->d,
  1135. -				      xd_r_fec_rsd_abort_packet_cnt_15_8,
  1136. -				      &temp1);
  1137. -	if (ret)
  1138. -		return ret;
  1139. -	loc_abort_count = ((u16) temp1 << 8) + temp0;
  1140. -
  1141. -	/* get error count */
  1142. -	ret =
  1143. -	    af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
  1144. -				      &temp0);
  1145. -	if (ret)
  1146. -		return ret;
  1147. -	ret =
  1148. -	    af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
  1149. -				      &temp1);
  1150. -	if (ret)
  1151. -		return ret;
  1152. -	ret =
  1153. -	    af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
  1154. -				      &temp2);
  1155. -	if (ret)
  1156. -		return ret;
  1157. -	err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
  1158. -	*post_err_count = err_count - (u32) loc_abort_count *8 * 8;
  1159. -
  1160. -	/* get RSD packet number */
  1161. -	ret =
  1162. -	    af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
  1163. -				      &temp0);
  1164. -	if (ret)
  1165. -		return ret;
  1166. -	ret =
  1167. -	    af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
  1168. -				      &temp1);
  1169. -	if (ret)
  1170. -		return ret;
  1171. -	cw_count = ((u32) temp1 << 8) + temp0;
  1172. -	if (cw_count == 0) {
  1173. -		err("wrong RSD packet count");
  1174. -		return -EIO;
  1175. -	}
  1176. -	deb_info("POST abort count %d err count %d rsd packets %d\n",
  1177. -		 loc_abort_count, err_count, cw_count);
  1178. -	*post_cw_count = cw_count - (u32) loc_abort_count;
  1179. -	*abort_count = loc_abort_count;
  1180. -	return 0;
  1181. -
  1182. -}
  1183. -
  1184. -static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
  1185. -				   u32 * post_err_count, u32 * post_cw_count,
  1186. -				   u16 * abort_count)
  1187. -{
  1188. -	u32 loc_cw_count = 0, loc_err_count;
  1189. -	u16 loc_abort_count = 0;
  1190. -	int ret;
  1191. -
  1192. -	ret =
  1193. -	    af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
  1194. -					     &loc_abort_count);
  1195. -	if (ret)
  1196. -		return ret;
  1197. -	*post_err_count = loc_err_count;
  1198. -	*post_cw_count = loc_cw_count * 204 * 8;
  1199. -	*abort_count = loc_abort_count;
  1200. -
  1201. -	return 0;
  1202. -}
  1203. -
  1204. -static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
  1205. -					    u32 * pre_err_count,
  1206. -					    u32 * pre_bit_count)
  1207. -{
  1208. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1209. -	u8 temp, temp0, temp1, temp2;
  1210. -	u32 super_frame_count, x, bits;
  1211. -	int ret;
  1212. -
  1213. -	ret =
  1214. -	    af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
  1215. -				      fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
  1216. -				      &temp);
  1217. -	if (ret)
  1218. -		return ret;
  1219. -	if (!temp) {
  1220. -		deb_info("viterbi counter not ready\n");
  1221. -		return 101;	/* ERR_APO_VTB_COUNTER_NOT_READY; */
  1222. -	}
  1223. -	ret =
  1224. -	    af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
  1225. -				      &temp0);
  1226. -	if (ret)
  1227. -		return ret;
  1228. -	ret =
  1229. -	    af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
  1230. -				      &temp1);
  1231. -	if (ret)
  1232. -		return ret;
  1233. -	ret =
  1234. -	    af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
  1235. -				      &temp2);
  1236. -	if (ret)
  1237. -		return ret;
  1238. -	*pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
  1239. -
  1240. -	ret =
  1241. -	    af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
  1242. -				      &temp0);
  1243. -	if (ret)
  1244. -		return ret;
  1245. -	ret =
  1246. -	    af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
  1247. -				      &temp1);
  1248. -	if (ret)
  1249. -		return ret;
  1250. -	super_frame_count = ((u32) temp1 << 8) + temp0;
  1251. -	if (super_frame_count == 0) {
  1252. -		deb_info("super frame count 0\n");
  1253. -		return 102;
  1254. -	}
  1255. -
  1256. -	/* read fft mode */
  1257. -	ret =
  1258. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
  1259. -				      reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
  1260. -				      &temp);
  1261. -	if (ret)
  1262. -		return ret;
  1263. -	if (temp == 0) {
  1264. -		/* 2K */
  1265. -		x = 1512;
  1266. -	} else if (temp == 1) {
  1267. -		/* 8k */
  1268. -		x = 6048;
  1269. -	} else {
  1270. -		err("Invalid fft mode");
  1271. -		return -EINVAL;
  1272. -	}
  1273. -
  1274. -	/* read modulation mode */
  1275. -	ret =
  1276. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
  1277. -				      reg_tpsd_const_pos, reg_tpsd_const_len,
  1278. -				      &temp);
  1279. -	if (ret)
  1280. -		return ret;
  1281. -	switch (temp) {
  1282. -	case 0:		/* QPSK */
  1283. -		bits = 2;
  1284. -		break;
  1285. -	case 1:		/* QAM_16 */
  1286. -		bits = 4;
  1287. -		break;
  1288. -	case 2:		/* QAM_64 */
  1289. -		bits = 6;
  1290. -		break;
  1291. -	default:
  1292. -		err("invalid modulation mode");
  1293. -		return -EINVAL;
  1294. -	}
  1295. -	*pre_bit_count = super_frame_count * 68 * 4 * x * bits;
  1296. -	deb_info("PRE err count %d frame count %d bit count %d\n",
  1297. -		 *pre_err_count, super_frame_count, *pre_bit_count);
  1298. -	return 0;
  1299. -}
  1300. -
  1301. -static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
  1302. -{
  1303. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1304. -	int ret;
  1305. -
  1306. -	/* set super frame count to 1 */
  1307. -	ret =
  1308. -	    af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
  1309. -				       1 & 0xff);
  1310. -	if (ret)
  1311. -		return ret;
  1312. -	ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
  1313. -					 1 >> 8);
  1314. -	if (ret)
  1315. -		return ret;
  1316. -	/* reset pre viterbi error count */
  1317. -	ret =
  1318. -	    af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
  1319. -				       fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
  1320. -				       1);
  1321. -
  1322. -	return ret;
  1323. -}
  1324. -
  1325. -static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
  1326. -{
  1327. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1328. -	int ret;
  1329. -
  1330. -	/* set packet unit */
  1331. -	ret =
  1332. -	    af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
  1333. -				       10000 & 0xff);
  1334. -	if (ret)
  1335. -		return ret;
  1336. -	ret =
  1337. -	    af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
  1338. -				       10000 >> 8);
  1339. -	if (ret)
  1340. -		return ret;
  1341. -	/* reset post viterbi error count */
  1342. -	ret =
  1343. -	    af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
  1344. -				       fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
  1345. -				       1);
  1346. -
  1347. -	return ret;
  1348. -}
  1349. -
  1350. -static int af9005_get_statistic(struct dvb_frontend *fe)
  1351. -{
  1352. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1353. -	int ret, fecavailable;
  1354. -	u64 numerator, denominator;
  1355. -
  1356. -	deb_info("GET STATISTIC\n");
  1357. -	ret = af9005_is_fecmon_available(fe, &fecavailable);
  1358. -	if (ret)
  1359. -		return ret;
  1360. -	if (!fecavailable) {
  1361. -		deb_info("fecmon not available\n");
  1362. -		return 0;
  1363. -	}
  1364. -
  1365. -	ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
  1366. -					       &state->pre_vit_bit_count);
  1367. -	if (ret == 0) {
  1368. -		af9005_reset_pre_viterbi(fe);
  1369. -		if (state->pre_vit_bit_count > 0) {
  1370. -			/* according to v 0.0.4 of the dvb api ber should be a multiple
  1371. -			   of 10E-9 so we have to multiply the error count by
  1372. -			   10E9=1000000000 */
  1373. -			numerator =
  1374. -			    (u64) state->pre_vit_error_count * (u64) 1000000000;
  1375. -			denominator = (u64) state->pre_vit_bit_count;
  1376. -			state->ber = do_div(numerator, denominator);
  1377. -		} else {
  1378. -			state->ber = 0xffffffff;
  1379. -		}
  1380. -	}
  1381. -
  1382. -	ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
  1383. -				      &state->post_vit_bit_count,
  1384. -				      &state->abort_count);
  1385. -	if (ret == 0) {
  1386. -		ret = af9005_reset_post_viterbi(fe);
  1387. -		state->unc += state->abort_count;
  1388. -		if (ret)
  1389. -			return ret;
  1390. -	}
  1391. -	return 0;
  1392. -}
  1393. -
  1394. -static int af9005_fe_refresh_state(struct dvb_frontend *fe)
  1395. -{
  1396. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1397. -	if (time_after(jiffies, state->next_status_check)) {
  1398. -		deb_info("REFRESH STATE\n");
  1399. -
  1400. -		/* statistics */
  1401. -		if (af9005_get_statistic(fe))
  1402. -			err("get_statistic_failed");
  1403. -		state->next_status_check = jiffies + 250 * HZ / 1000;
  1404. -	}
  1405. -	return 0;
  1406. -}
  1407. -
  1408. -static int af9005_fe_read_status(struct dvb_frontend *fe,
  1409. -				 enum fe_status *stat)
  1410. -{
  1411. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1412. -	u8 temp;
  1413. -	int ret;
  1414. -
  1415. -	if (fe->ops.tuner_ops.release == NULL)
  1416. -		return -ENODEV;
  1417. -
  1418. -	*stat = 0;
  1419. -	ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
  1420. -					agc_lock_pos, agc_lock_len, &temp);
  1421. -	if (ret)
  1422. -		return ret;
  1423. -	if (temp)
  1424. -		*stat |= FE_HAS_SIGNAL;
  1425. -
  1426. -	ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
  1427. -					fd_tpsd_lock_pos, fd_tpsd_lock_len,
  1428. -					&temp);
  1429. -	if (ret)
  1430. -		return ret;
  1431. -	if (temp)
  1432. -		*stat |= FE_HAS_CARRIER;
  1433. -
  1434. -	ret = af9005_read_register_bits(state->d,
  1435. -					xd_r_mp2if_sync_byte_locked,
  1436. -					mp2if_sync_byte_locked_pos,
  1437. -					mp2if_sync_byte_locked_pos, &temp);
  1438. -	if (ret)
  1439. -		return ret;
  1440. -	if (temp)
  1441. -		*stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
  1442. -	if (state->opened)
  1443. -		af9005_led_control(state->d, *stat & FE_HAS_LOCK);
  1444. -
  1445. -	ret =
  1446. -	    af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
  1447. -				      reg_strong_sginal_detected_pos,
  1448. -				      reg_strong_sginal_detected_len, &temp);
  1449. -	if (ret)
  1450. -		return ret;
  1451. -	if (temp != state->strong) {
  1452. -		deb_info("adjust for strong signal %d\n", temp);
  1453. -		state->strong = temp;
  1454. -	}
  1455. -	return 0;
  1456. -}
  1457. -
  1458. -static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
  1459. -{
  1460. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1461. -	if (fe->ops.tuner_ops.release  == NULL)
  1462. -		return -ENODEV;
  1463. -	af9005_fe_refresh_state(fe);
  1464. -	*ber = state->ber;
  1465. -	return 0;
  1466. -}
  1467. -
  1468. -static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
  1469. -{
  1470. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1471. -	if (fe->ops.tuner_ops.release == NULL)
  1472. -		return -ENODEV;
  1473. -	af9005_fe_refresh_state(fe);
  1474. -	*unc = state->unc;
  1475. -	return 0;
  1476. -}
  1477. -
  1478. -static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
  1479. -					  u16 * strength)
  1480. -{
  1481. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1482. -	int ret;
  1483. -	u8 if_gain, rf_gain;
  1484. -
  1485. -	if (fe->ops.tuner_ops.release == NULL)
  1486. -		return -ENODEV;
  1487. -	ret =
  1488. -	    af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
  1489. -				      &rf_gain);
  1490. -	if (ret)
  1491. -		return ret;
  1492. -	ret =
  1493. -	    af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
  1494. -				      &if_gain);
  1495. -	if (ret)
  1496. -		return ret;
  1497. -	/* this value has no real meaning, but i don't have the tables that relate
  1498. -	   the rf and if gain with the dbm, so I just scale the value */
  1499. -	*strength = (512 - rf_gain - if_gain) << 7;
  1500. -	return 0;
  1501. -}
  1502. -
  1503. -static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
  1504. -{
  1505. -	/* the snr can be derived from the ber and the modulation
  1506. -	   but I don't think this kind of complex calculations belong
  1507. -	   in the driver. I may be wrong.... */
  1508. -	return -ENOSYS;
  1509. -}
  1510. -
  1511. -static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw)
  1512. -{
  1513. -	u8 temp0, temp1, temp2, temp3, buf[4];
  1514. -	int ret;
  1515. -	u32 NS_coeff1_2048Nu;
  1516. -	u32 NS_coeff1_8191Nu;
  1517. -	u32 NS_coeff1_8192Nu;
  1518. -	u32 NS_coeff1_8193Nu;
  1519. -	u32 NS_coeff2_2k;
  1520. -	u32 NS_coeff2_8k;
  1521. -
  1522. -	switch (bw) {
  1523. -	case 6000000:
  1524. -		NS_coeff1_2048Nu = 0x2ADB6DC;
  1525. -		NS_coeff1_8191Nu = 0xAB7313;
  1526. -		NS_coeff1_8192Nu = 0xAB6DB7;
  1527. -		NS_coeff1_8193Nu = 0xAB685C;
  1528. -		NS_coeff2_2k = 0x156DB6E;
  1529. -		NS_coeff2_8k = 0x55B6DC;
  1530. -		break;
  1531. -
  1532. -	case 7000000:
  1533. -		NS_coeff1_2048Nu = 0x3200001;
  1534. -		NS_coeff1_8191Nu = 0xC80640;
  1535. -		NS_coeff1_8192Nu = 0xC80000;
  1536. -		NS_coeff1_8193Nu = 0xC7F9C0;
  1537. -		NS_coeff2_2k = 0x1900000;
  1538. -		NS_coeff2_8k = 0x640000;
  1539. -		break;
  1540. -
  1541. -	case 8000000:
  1542. -		NS_coeff1_2048Nu = 0x3924926;
  1543. -		NS_coeff1_8191Nu = 0xE4996E;
  1544. -		NS_coeff1_8192Nu = 0xE49249;
  1545. -		NS_coeff1_8193Nu = 0xE48B25;
  1546. -		NS_coeff2_2k = 0x1C92493;
  1547. -		NS_coeff2_8k = 0x724925;
  1548. -		break;
  1549. -	default:
  1550. -		err("Invalid bandwidth %d.", bw);
  1551. -		return -EINVAL;
  1552. -	}
  1553. -
  1554. -	/*
  1555. -	 *  write NS_coeff1_2048Nu
  1556. -	 */
  1557. -
  1558. -	temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
  1559. -	temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
  1560. -	temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
  1561. -	temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
  1562. -
  1563. -	/*  big endian to make 8051 happy */
  1564. -	buf[0] = temp3;
  1565. -	buf[1] = temp2;
  1566. -	buf[2] = temp1;
  1567. -	buf[3] = temp0;
  1568. -
  1569. -	/*  cfoe_NS_2k_coeff1_25_24 */
  1570. -	ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
  1571. -	if (ret)
  1572. -		return ret;
  1573. -
  1574. -	/*  cfoe_NS_2k_coeff1_23_16 */
  1575. -	ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
  1576. -	if (ret)
  1577. -		return ret;
  1578. -
  1579. -	/*  cfoe_NS_2k_coeff1_15_8 */
  1580. -	ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
  1581. -	if (ret)
  1582. -		return ret;
  1583. -
  1584. -	/*  cfoe_NS_2k_coeff1_7_0 */
  1585. -	ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
  1586. -	if (ret)
  1587. -		return ret;
  1588. -
  1589. -	/*
  1590. -	 *  write NS_coeff2_2k
  1591. -	 */
  1592. -
  1593. -	temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
  1594. -	temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
  1595. -	temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
  1596. -	temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
  1597. -
  1598. -	/*  big endian to make 8051 happy */
  1599. -	buf[0] = temp3;
  1600. -	buf[1] = temp2;
  1601. -	buf[2] = temp1;
  1602. -	buf[3] = temp0;
  1603. -
  1604. -	ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
  1605. -	if (ret)
  1606. -		return ret;
  1607. -
  1608. -	ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
  1609. -	if (ret)
  1610. -		return ret;
  1611. -
  1612. -	ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
  1613. -	if (ret)
  1614. -		return ret;
  1615. -
  1616. -	ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
  1617. -	if (ret)
  1618. -		return ret;
  1619. -
  1620. -	/*
  1621. -	 *  write NS_coeff1_8191Nu
  1622. -	 */
  1623. -
  1624. -	temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
  1625. -	temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
  1626. -	temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
  1627. -	temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
  1628. -
  1629. -	/*  big endian to make 8051 happy */
  1630. -	buf[0] = temp3;
  1631. -	buf[1] = temp2;
  1632. -	buf[2] = temp1;
  1633. -	buf[3] = temp0;
  1634. -
  1635. -	ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
  1636. -	if (ret)
  1637. -		return ret;
  1638. -
  1639. -	ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
  1640. -	if (ret)
  1641. -		return ret;
  1642. -
  1643. -	ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
  1644. -	if (ret)
  1645. -		return ret;
  1646. -
  1647. -	ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
  1648. -	if (ret)
  1649. -		return ret;
  1650. -
  1651. -	/*
  1652. -	 *  write NS_coeff1_8192Nu
  1653. -	 */
  1654. -
  1655. -	temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
  1656. -	temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
  1657. -	temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
  1658. -	temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
  1659. -
  1660. -	/*  big endian to make 8051 happy */
  1661. -	buf[0] = temp3;
  1662. -	buf[1] = temp2;
  1663. -	buf[2] = temp1;
  1664. -	buf[3] = temp0;
  1665. -
  1666. -	ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
  1667. -	if (ret)
  1668. -		return ret;
  1669. -
  1670. -	ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
  1671. -	if (ret)
  1672. -		return ret;
  1673. -
  1674. -	ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
  1675. -	if (ret)
  1676. -		return ret;
  1677. -
  1678. -	ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
  1679. -	if (ret)
  1680. -		return ret;
  1681. -
  1682. -	/*
  1683. -	 *  write NS_coeff1_8193Nu
  1684. -	 */
  1685. -
  1686. -	temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
  1687. -	temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
  1688. -	temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
  1689. -	temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
  1690. -
  1691. -	/*  big endian to make 8051 happy */
  1692. -	buf[0] = temp3;
  1693. -	buf[1] = temp2;
  1694. -	buf[2] = temp1;
  1695. -	buf[3] = temp0;
  1696. -
  1697. -	ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
  1698. -	if (ret)
  1699. -		return ret;
  1700. -
  1701. -	ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
  1702. -	if (ret)
  1703. -		return ret;
  1704. -
  1705. -	ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
  1706. -	if (ret)
  1707. -		return ret;
  1708. -
  1709. -	ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
  1710. -	if (ret)
  1711. -		return ret;
  1712. -
  1713. -	/*
  1714. -	 *  write NS_coeff2_8k
  1715. -	 */
  1716. -
  1717. -	temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
  1718. -	temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
  1719. -	temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
  1720. -	temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
  1721. -
  1722. -	/*  big endian to make 8051 happy */
  1723. -	buf[0] = temp3;
  1724. -	buf[1] = temp2;
  1725. -	buf[2] = temp1;
  1726. -	buf[3] = temp0;
  1727. -
  1728. -	ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
  1729. -	if (ret)
  1730. -		return ret;
  1731. -
  1732. -	ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
  1733. -	if (ret)
  1734. -		return ret;
  1735. -
  1736. -	ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
  1737. -	if (ret)
  1738. -		return ret;
  1739. -
  1740. -	ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
  1741. -	return ret;
  1742. -
  1743. -}
  1744. -
  1745. -static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw)
  1746. -{
  1747. -	u8 temp;
  1748. -	switch (bw) {
  1749. -	case 6000000:
  1750. -		temp = 0;
  1751. -		break;
  1752. -	case 7000000:
  1753. -		temp = 1;
  1754. -		break;
  1755. -	case 8000000:
  1756. -		temp = 2;
  1757. -		break;
  1758. -	default:
  1759. -		err("Invalid bandwidth %d.", bw);
  1760. -		return -EINVAL;
  1761. -	}
  1762. -	return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
  1763. -					  reg_bw_len, temp);
  1764. -}
  1765. -
  1766. -static int af9005_fe_power(struct dvb_frontend *fe, int on)
  1767. -{
  1768. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1769. -	u8 temp = on;
  1770. -	int ret;
  1771. -	deb_info("power %s tuner\n", on ? "on" : "off");
  1772. -	ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
  1773. -	return ret;
  1774. -}
  1775. -
  1776. -static struct mt2060_config af9005_mt2060_config = {
  1777. -	0xC0
  1778. -};
  1779. -
  1780. -static struct qt1010_config af9005_qt1010_config = {
  1781. -	0xC4
  1782. -};
  1783. -
  1784. -static int af9005_fe_init(struct dvb_frontend *fe)
  1785. -{
  1786. -	struct af9005_fe_state *state = fe->demodulator_priv;
  1787. -	struct dvb_usb_adapter *adap = fe->dvb->priv;
  1788. -	int ret, i, scriptlen;
  1789. -	u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
  1790. -	u8 buf[2];
  1791. -	u16 if1;
  1792. -
  1793. -	deb_info("in af9005_fe_init\n");
  1794. -
  1795. -	/* reset */
  1796. -	deb_info("reset\n");
  1797. -	if ((ret =
  1798. -	     af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
  1799. -					4, 1, 0x01)))
  1800. -		return ret;
  1801. -	if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
  1802. -		return ret;
  1803. -	/* clear ofdm reset */
  1804. -	deb_info("clear ofdm reset\n");
  1805. -	for (i = 0; i < 150; i++) {
  1806. -		if ((ret =
  1807. -		     af9005_read_ofdm_register(state->d,
  1808. -					       xd_I2C_reg_ofdm_rst, &temp)))
  1809. -			return ret;
  1810. -		if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
  1811. -			break;
  1812. -		msleep(10);
  1813. -	}
  1814. -	if (i == 150)
  1815. -		return -ETIMEDOUT;
  1816. -
  1817. -	/*FIXME in the dump
  1818. -	   write B200 A9
  1819. -	   write xd_g_reg_ofsm_clk 7
  1820. -	   read eepr c6 (2)
  1821. -	   read eepr c7 (2)
  1822. -	   misc ctrl 3 -> 1
  1823. -	   read eepr ca (6)
  1824. -	   write xd_g_reg_ofsm_clk 0
  1825. -	   write B200 a1
  1826. -	 */
  1827. -	ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
  1828. -	if (ret)
  1829. -		return ret;
  1830. -	ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
  1831. -	if (ret)
  1832. -		return ret;
  1833. -	temp = 0x01;
  1834. -	ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
  1835. -	if (ret)
  1836. -		return ret;
  1837. -	ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
  1838. -	if (ret)
  1839. -		return ret;
  1840. -	ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
  1841. -	if (ret)
  1842. -		return ret;
  1843. -
  1844. -	temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
  1845. -	if ((ret =
  1846. -	     af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
  1847. -					reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
  1848. -		return ret;
  1849. -	ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
  1850. -					 reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
  1851. -
  1852. -	if (ret)
  1853. -		return ret;
  1854. -	/* don't know what register aefc is, but this is what the windows driver does */
  1855. -	ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
  1856. -	if (ret)
  1857. -		return ret;
  1858. -
  1859. -	/* set stand alone chip */
  1860. -	deb_info("set stand alone chip\n");
  1861. -	if ((ret =
  1862. -	     af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
  1863. -					reg_dca_stand_alone_pos,
  1864. -					reg_dca_stand_alone_len, 1)))
  1865. -		return ret;
  1866. -
  1867. -	/* set dca upper & lower chip */
  1868. -	deb_info("set dca upper & lower chip\n");
  1869. -	if ((ret =
  1870. -	     af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
  1871. -					reg_dca_upper_chip_pos,
  1872. -					reg_dca_upper_chip_len, 0)))
  1873. -		return ret;
  1874. -	if ((ret =
  1875. -	     af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
  1876. -					reg_dca_lower_chip_pos,
  1877. -					reg_dca_lower_chip_len, 0)))
  1878. -		return ret;
  1879. -
  1880. -	/* set 2wire master clock to 0x14 (for 60KHz) */
  1881. -	deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
  1882. -	if ((ret =
  1883. -	     af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
  1884. -		return ret;
  1885. -
  1886. -	/* clear dca enable chip */
  1887. -	deb_info("clear dca enable chip\n");
  1888. -	if ((ret =
  1889. -	     af9005_write_register_bits(state->d, xd_p_reg_dca_en,
  1890. -					reg_dca_en_pos, reg_dca_en_len, 0)))
  1891. -		return ret;
  1892. -	/* FIXME these are register bits, but I don't know which ones */
  1893. -	ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
  1894. -	if (ret)
  1895. -		return ret;
  1896. -	ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
  1897. -	if (ret)
  1898. -		return ret;
  1899. -
  1900. -	/* init other parameters: program cfoe and select bandwidth */
  1901. -	deb_info("program cfoe\n");
  1902. -	ret = af9005_fe_program_cfoe(state->d, 6000000);
  1903. -	if (ret)
  1904. -		return ret;
  1905. -	/* set read-update bit for modulation */
  1906. -	deb_info("set read-update bit for modulation\n");
  1907. -	if ((ret =
  1908. -	     af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
  1909. -					reg_feq_read_update_pos,
  1910. -					reg_feq_read_update_len, 1)))
  1911. -		return ret;
  1912. -
  1913. -	/* sample code has a set MPEG TS code here
  1914. -	   but sniffing reveals that it doesn't do it */
  1915. -
  1916. -	/* set read-update bit to 1 for DCA modulation */
  1917. -	deb_info("set read-update bit 1 for DCA modulation\n");
  1918. -	if ((ret =
  1919. -	     af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
  1920. -					reg_dca_read_update_pos,
  1921. -					reg_dca_read_update_len, 1)))
  1922. -		return ret;
  1923. -
  1924. -	/* enable fec monitor */
  1925. -	deb_info("enable fec monitor\n");
  1926. -	if ((ret =
  1927. -	     af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
  1928. -					fec_vtb_rsd_mon_en_pos,
  1929. -					fec_vtb_rsd_mon_en_len, 1)))
  1930. -		return ret;
  1931. -
  1932. -	/* FIXME should be register bits, I don't know which ones */
  1933. -	ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
  1934. -
  1935. -	/* set api_retrain_never_freeze */
  1936. -	deb_info("set api_retrain_never_freeze\n");
  1937. -	if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
  1938. -		return ret;
  1939. -
  1940. -	/* load init script */
  1941. -	deb_info("load init script\n");
  1942. -	scriptlen = sizeof(script) / sizeof(RegDesc);
  1943. -	for (i = 0; i < scriptlen; i++) {
  1944. -		if ((ret =
  1945. -		     af9005_write_register_bits(state->d, script[i].reg,
  1946. -						script[i].pos,
  1947. -						script[i].len, script[i].val)))
  1948. -			return ret;
  1949. -		/* save 3 bytes of original fcw */
  1950. -		if (script[i].reg == 0xae18)
  1951. -			temp2 = script[i].val;
  1952. -		if (script[i].reg == 0xae19)
  1953. -			temp1 = script[i].val;
  1954. -		if (script[i].reg == 0xae1a)
  1955. -			temp0 = script[i].val;
  1956. -
  1957. -		/* save original unplug threshold */
  1958. -		if (script[i].reg == xd_p_reg_unplug_th)
  1959. -			state->original_if_unplug_th = script[i].val;
  1960. -		if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
  1961. -			state->original_rf_unplug_th = script[i].val;
  1962. -		if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
  1963. -			state->original_dtop_if_unplug_th = script[i].val;
  1964. -		if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
  1965. -			state->original_dtop_rf_unplug_th = script[i].val;
  1966. -
  1967. -	}
  1968. -	state->original_fcw =
  1969. -	    ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
  1970. -
  1971. -
  1972. -	/* save original TOPs */
  1973. -	deb_info("save original TOPs\n");
  1974. -
  1975. -	/*  RF TOP */
  1976. -	ret =
  1977. -	    af9005_read_word_agc(state->d,
  1978. -				 xd_p_reg_aagc_rf_top_numerator_9_8,
  1979. -				 xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
  1980. -				 &state->original_rf_top);
  1981. -	if (ret)
  1982. -		return ret;
  1983. -
  1984. -	/*  IF TOP */
  1985. -	ret =
  1986. -	    af9005_read_word_agc(state->d,
  1987. -				 xd_p_reg_aagc_if_top_numerator_9_8,
  1988. -				 xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
  1989. -				 &state->original_if_top);
  1990. -	if (ret)
  1991. -		return ret;
  1992. -
  1993. -	/*  ACI 0 IF TOP */
  1994. -	ret =
  1995. -	    af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
  1996. -				 &state->original_aci0_if_top);
  1997. -	if (ret)
  1998. -		return ret;
  1999. -
  2000. -	/*  ACI 1 IF TOP */
  2001. -	ret =
  2002. -	    af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
  2003. -				 &state->original_aci1_if_top);
  2004. -	if (ret)
  2005. -		return ret;
  2006. -
  2007. -	/* attach tuner and init */
  2008. -	if (fe->ops.tuner_ops.release == NULL) {
  2009. -		/* read tuner and board id from eeprom */
  2010. -		ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
  2011. -		if (ret) {
  2012. -			err("Impossible to read EEPROM\n");
  2013. -			return ret;
  2014. -		}
  2015. -		deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
  2016. -		switch (buf[0]) {
  2017. -		case 2:	/* MT2060 */
  2018. -			/* read if1 from eeprom */
  2019. -			ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
  2020. -			if (ret) {
  2021. -				err("Impossible to read EEPROM\n");
  2022. -				return ret;
  2023. -			}
  2024. -			if1 = (u16) (buf[0] << 8) + buf[1];
  2025. -			if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
  2026. -					 &af9005_mt2060_config, if1) == NULL) {
  2027. -				deb_info("MT2060 attach failed\n");
  2028. -				return -ENODEV;
  2029. -			}
  2030. -			break;
  2031. -		case 3:	/* QT1010 */
  2032. -		case 9:	/* QT1010B */
  2033. -			if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
  2034. -					&af9005_qt1010_config) ==NULL) {
  2035. -				deb_info("QT1010 attach failed\n");
  2036. -				return -ENODEV;
  2037. -			}
  2038. -			break;
  2039. -		default:
  2040. -			err("Unsupported tuner type %d", buf[0]);
  2041. -			return -ENODEV;
  2042. -		}
  2043. -		ret = fe->ops.tuner_ops.init(fe);
  2044. -		if (ret)
  2045. -			return ret;
  2046. -	}
  2047. -
  2048. -	deb_info("profit!\n");
  2049. -	return 0;
  2050. -}
  2051. -
  2052. -static int af9005_fe_sleep(struct dvb_frontend *fe)
  2053. -{
  2054. -	return af9005_fe_power(fe, 0);
  2055. -}
  2056. -
  2057. -static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
  2058. -{
  2059. -	struct af9005_fe_state *state = fe->demodulator_priv;
  2060. -
  2061. -	if (acquire) {
  2062. -		state->opened++;
  2063. -	} else {
  2064. -
  2065. -		state->opened--;
  2066. -		if (!state->opened)
  2067. -			af9005_led_control(state->d, 0);
  2068. -	}
  2069. -	return 0;
  2070. -}
  2071. -
  2072. -static int af9005_fe_set_frontend(struct dvb_frontend *fe)
  2073. -{
  2074. -	struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
  2075. -	struct af9005_fe_state *state = fe->demodulator_priv;
  2076. -	int ret;
  2077. -	u8 temp, temp0, temp1, temp2;
  2078. -
  2079. -	deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
  2080. -		 fep->bandwidth_hz);
  2081. -	if (fe->ops.tuner_ops.release == NULL) {
  2082. -		err("Tuner not attached");
  2083. -		return -ENODEV;
  2084. -	}
  2085. -
  2086. -	deb_info("turn off led\n");
  2087. -	/* not in the log */
  2088. -	ret = af9005_led_control(state->d, 0);
  2089. -	if (ret)
  2090. -		return ret;
  2091. -	/* not sure about the bits */
  2092. -	ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
  2093. -	if (ret)
  2094. -		return ret;
  2095. -
  2096. -	/* set FCW to default value */
  2097. -	deb_info("set FCW to default value\n");
  2098. -	temp0 = (u8) (state->original_fcw & 0x000000ff);
  2099. -	temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
  2100. -	temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
  2101. -	ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
  2102. -	if (ret)
  2103. -		return ret;
  2104. -	ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
  2105. -	if (ret)
  2106. -		return ret;
  2107. -	ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
  2108. -	if (ret)
  2109. -		return ret;
  2110. -
  2111. -	/* restore original TOPs */
  2112. -	deb_info("restore original TOPs\n");
  2113. -	ret =
  2114. -	    af9005_write_word_agc(state->d,
  2115. -				  xd_p_reg_aagc_rf_top_numerator_9_8,
  2116. -				  xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
  2117. -				  state->original_rf_top);
  2118. -	if (ret)
  2119. -		return ret;
  2120. -	ret =
  2121. -	    af9005_write_word_agc(state->d,
  2122. -				  xd_p_reg_aagc_if_top_numerator_9_8,
  2123. -				  xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
  2124. -				  state->original_if_top);
  2125. -	if (ret)
  2126. -		return ret;
  2127. -	ret =
  2128. -	    af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
  2129. -				  state->original_aci0_if_top);
  2130. -	if (ret)
  2131. -		return ret;
  2132. -	ret =
  2133. -	    af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
  2134. -				  state->original_aci1_if_top);
  2135. -	if (ret)
  2136. -		return ret;
  2137. -
  2138. -	/* select bandwidth */
  2139. -	deb_info("select bandwidth");
  2140. -	ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz);
  2141. -	if (ret)
  2142. -		return ret;
  2143. -	ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz);
  2144. -	if (ret)
  2145. -		return ret;
  2146. -
  2147. -	/* clear easy mode flag */
  2148. -	deb_info("clear easy mode flag\n");
  2149. -	ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
  2150. -	if (ret)
  2151. -		return ret;
  2152. -
  2153. -	/* set unplug threshold to original value */
  2154. -	deb_info("set unplug threshold to original value\n");
  2155. -	ret =
  2156. -	    af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
  2157. -				       state->original_if_unplug_th);
  2158. -	if (ret)
  2159. -		return ret;
  2160. -	/* set tuner */
  2161. -	deb_info("set tuner\n");
  2162. -	ret = fe->ops.tuner_ops.set_params(fe);
  2163. -	if (ret)
  2164. -		return ret;
  2165. -
  2166. -	/* trigger ofsm */
  2167. -	deb_info("trigger ofsm\n");
  2168. -	temp = 0;
  2169. -	ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
  2170. -	if (ret)
  2171. -		return ret;
  2172. -
  2173. -	/* clear retrain and freeze flag */
  2174. -	deb_info("clear retrain and freeze flag\n");
  2175. -	ret =
  2176. -	    af9005_write_register_bits(state->d,
  2177. -				       xd_p_reg_api_retrain_request,
  2178. -				       reg_api_retrain_request_pos, 2, 0);
  2179. -	if (ret)
  2180. -		return ret;
  2181. -
  2182. -	/* reset pre viterbi and post viterbi registers and statistics */
  2183. -	af9005_reset_pre_viterbi(fe);
  2184. -	af9005_reset_post_viterbi(fe);
  2185. -	state->pre_vit_error_count = 0;
  2186. -	state->pre_vit_bit_count = 0;
  2187. -	state->ber = 0;
  2188. -	state->post_vit_error_count = 0;
  2189. -	/* state->unc = 0; commented out since it should be ever increasing */
  2190. -	state->abort_count = 0;
  2191. -
  2192. -	state->next_status_check = jiffies;
  2193. -	state->strong = -1;
  2194. -
  2195. -	return 0;
  2196. -}
  2197. -
  2198. -static int af9005_fe_get_frontend(struct dvb_frontend *fe,
  2199. -				  struct dtv_frontend_properties *fep)
  2200. -{
  2201. -	struct af9005_fe_state *state = fe->demodulator_priv;
  2202. -	int ret;
  2203. -	u8 temp;
  2204. -
  2205. -	/* mode */
  2206. -	ret =
  2207. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
  2208. -				      reg_tpsd_const_pos, reg_tpsd_const_len,
  2209. -				      &temp);
  2210. -	if (ret)
  2211. -		return ret;
  2212. -	deb_info("===== fe_get_frontend_legacy = =============\n");
  2213. -	deb_info("CONSTELLATION ");
  2214. -	switch (temp) {
  2215. -	case 0:
  2216. -		fep->modulation = QPSK;
  2217. -		deb_info("QPSK\n");
  2218. -		break;
  2219. -	case 1:
  2220. -		fep->modulation = QAM_16;
  2221. -		deb_info("QAM_16\n");
  2222. -		break;
  2223. -	case 2:
  2224. -		fep->modulation = QAM_64;
  2225. -		deb_info("QAM_64\n");
  2226. -		break;
  2227. -	}
  2228. -
  2229. -	/* tps hierarchy and alpha value */
  2230. -	ret =
  2231. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
  2232. -				      reg_tpsd_hier_pos, reg_tpsd_hier_len,
  2233. -				      &temp);
  2234. -	if (ret)
  2235. -		return ret;
  2236. -	deb_info("HIERARCHY ");
  2237. -	switch (temp) {
  2238. -	case 0:
  2239. -		fep->hierarchy = HIERARCHY_NONE;
  2240. -		deb_info("NONE\n");
  2241. -		break;
  2242. -	case 1:
  2243. -		fep->hierarchy = HIERARCHY_1;
  2244. -		deb_info("1\n");
  2245. -		break;
  2246. -	case 2:
  2247. -		fep->hierarchy = HIERARCHY_2;
  2248. -		deb_info("2\n");
  2249. -		break;
  2250. -	case 3:
  2251. -		fep->hierarchy = HIERARCHY_4;
  2252. -		deb_info("4\n");
  2253. -		break;
  2254. -	}
  2255. -
  2256. -	/*  high/low priority     */
  2257. -	ret =
  2258. -	    af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
  2259. -				      reg_dec_pri_pos, reg_dec_pri_len, &temp);
  2260. -	if (ret)
  2261. -		return ret;
  2262. -	/* if temp is set = high priority */
  2263. -	deb_info("PRIORITY %s\n", temp ? "high" : "low");
  2264. -
  2265. -	/* high coderate */
  2266. -	ret =
  2267. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
  2268. -				      reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
  2269. -				      &temp);
  2270. -	if (ret)
  2271. -		return ret;
  2272. -	deb_info("CODERATE HP ");
  2273. -	switch (temp) {
  2274. -	case 0:
  2275. -		fep->code_rate_HP = FEC_1_2;
  2276. -		deb_info("FEC_1_2\n");
  2277. -		break;
  2278. -	case 1:
  2279. -		fep->code_rate_HP = FEC_2_3;
  2280. -		deb_info("FEC_2_3\n");
  2281. -		break;
  2282. -	case 2:
  2283. -		fep->code_rate_HP = FEC_3_4;
  2284. -		deb_info("FEC_3_4\n");
  2285. -		break;
  2286. -	case 3:
  2287. -		fep->code_rate_HP = FEC_5_6;
  2288. -		deb_info("FEC_5_6\n");
  2289. -		break;
  2290. -	case 4:
  2291. -		fep->code_rate_HP = FEC_7_8;
  2292. -		deb_info("FEC_7_8\n");
  2293. -		break;
  2294. -	}
  2295. -
  2296. -	/* low coderate */
  2297. -	ret =
  2298. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
  2299. -				      reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
  2300. -				      &temp);
  2301. -	if (ret)
  2302. -		return ret;
  2303. -	deb_info("CODERATE LP ");
  2304. -	switch (temp) {
  2305. -	case 0:
  2306. -		fep->code_rate_LP = FEC_1_2;
  2307. -		deb_info("FEC_1_2\n");
  2308. -		break;
  2309. -	case 1:
  2310. -		fep->code_rate_LP = FEC_2_3;
  2311. -		deb_info("FEC_2_3\n");
  2312. -		break;
  2313. -	case 2:
  2314. -		fep->code_rate_LP = FEC_3_4;
  2315. -		deb_info("FEC_3_4\n");
  2316. -		break;
  2317. -	case 3:
  2318. -		fep->code_rate_LP = FEC_5_6;
  2319. -		deb_info("FEC_5_6\n");
  2320. -		break;
  2321. -	case 4:
  2322. -		fep->code_rate_LP = FEC_7_8;
  2323. -		deb_info("FEC_7_8\n");
  2324. -		break;
  2325. -	}
  2326. -
  2327. -	/* guard interval */
  2328. -	ret =
  2329. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
  2330. -				      reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
  2331. -	if (ret)
  2332. -		return ret;
  2333. -	deb_info("GUARD INTERVAL ");
  2334. -	switch (temp) {
  2335. -	case 0:
  2336. -		fep->guard_interval = GUARD_INTERVAL_1_32;
  2337. -		deb_info("1_32\n");
  2338. -		break;
  2339. -	case 1:
  2340. -		fep->guard_interval = GUARD_INTERVAL_1_16;
  2341. -		deb_info("1_16\n");
  2342. -		break;
  2343. -	case 2:
  2344. -		fep->guard_interval = GUARD_INTERVAL_1_8;
  2345. -		deb_info("1_8\n");
  2346. -		break;
  2347. -	case 3:
  2348. -		fep->guard_interval = GUARD_INTERVAL_1_4;
  2349. -		deb_info("1_4\n");
  2350. -		break;
  2351. -	}
  2352. -
  2353. -	/* fft */
  2354. -	ret =
  2355. -	    af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
  2356. -				      reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
  2357. -				      &temp);
  2358. -	if (ret)
  2359. -		return ret;
  2360. -	deb_info("TRANSMISSION MODE ");
  2361. -	switch (temp) {
  2362. -	case 0:
  2363. -		fep->transmission_mode = TRANSMISSION_MODE_2K;
  2364. -		deb_info("2K\n");
  2365. -		break;
  2366. -	case 1:
  2367. -		fep->transmission_mode = TRANSMISSION_MODE_8K;
  2368. -		deb_info("8K\n");
  2369. -		break;
  2370. -	}
  2371. -
  2372. -	/* bandwidth      */
  2373. -	ret =
  2374. -	    af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
  2375. -				      reg_bw_len, &temp);
  2376. -	deb_info("BANDWIDTH ");
  2377. -	switch (temp) {
  2378. -	case 0:
  2379. -		fep->bandwidth_hz = 6000000;
  2380. -		deb_info("6\n");
  2381. -		break;
  2382. -	case 1:
  2383. -		fep->bandwidth_hz = 7000000;
  2384. -		deb_info("7\n");
  2385. -		break;
  2386. -	case 2:
  2387. -		fep->bandwidth_hz = 8000000;
  2388. -		deb_info("8\n");
  2389. -		break;
  2390. -	}
  2391. -	return 0;
  2392. -}
  2393. -
  2394. -static void af9005_fe_release(struct dvb_frontend *fe)
  2395. -{
  2396. -	struct af9005_fe_state *state =
  2397. -	    (struct af9005_fe_state *)fe->demodulator_priv;
  2398. -	kfree(state);
  2399. -}
  2400. -
  2401. -static const struct dvb_frontend_ops af9005_fe_ops;
  2402. -
  2403. -struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
  2404. -{
  2405. -	struct af9005_fe_state *state = NULL;
  2406. -
  2407. -	/* allocate memory for the internal state */
  2408. -	state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
  2409. -	if (state == NULL)
  2410. -		goto error;
  2411. -
  2412. -	deb_info("attaching frontend af9005\n");
  2413. -
  2414. -	state->d = d;
  2415. -	state->opened = 0;
  2416. -
  2417. -	memcpy(&state->frontend.ops, &af9005_fe_ops,
  2418. -	       sizeof(struct dvb_frontend_ops));
  2419. -	state->frontend.demodulator_priv = state;
  2420. -
  2421. -	return &state->frontend;
  2422. -      error:
  2423. -	return NULL;
  2424. -}
  2425. -
  2426. -static const struct dvb_frontend_ops af9005_fe_ops = {
  2427. -	.delsys = { SYS_DVBT },
  2428. -	.info = {
  2429. -		 .name = "AF9005 USB DVB-T",
  2430. -		 .frequency_min = 44250000,
  2431. -		 .frequency_max = 867250000,
  2432. -		 .frequency_stepsize = 250000,
  2433. -		 .caps = FE_CAN_INVERSION_AUTO |
  2434. -		 FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
  2435. -		 FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
  2436. -		 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
  2437. -		 FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
  2438. -		 FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
  2439. -		 FE_CAN_HIERARCHY_AUTO,
  2440. -		 },
  2441. -
  2442. -	.release = af9005_fe_release,
  2443. -
  2444. -	.init = af9005_fe_init,
  2445. -	.sleep = af9005_fe_sleep,
  2446. -	.ts_bus_ctrl = af9005_ts_bus_ctrl,
  2447. -
  2448. -	.set_frontend = af9005_fe_set_frontend,
  2449. -	.get_frontend = af9005_fe_get_frontend,
  2450. -
  2451. -	.read_status = af9005_fe_read_status,
  2452. -	.read_ber = af9005_fe_read_ber,
  2453. -	.read_signal_strength = af9005_fe_read_signal_strength,
  2454. -	.read_snr = af9005_fe_read_snr,
  2455. -	.read_ucblocks = af9005_fe_read_unc_blocks,
  2456. -};
  2457. diff -ruN ../linux-4.14.336/drivers/media/usb/dvb-usb/af9005-remote.c ./drivers/media/usb/dvb-usb/af9005-remote.c
  2458. --- linux-4.14.336/../linux-4.14.336/drivers/media/usb/dvb-usb/af9005-remote.c	2024-01-10 14:45:41.000000000 +0100
  2459. +++ linux-4.14.336/./drivers/media/usb/dvb-usb/af9005-remote.c	1970-01-01 01:00:00.000000000 +0100
  2460. @@ -1,153 +0,0 @@
  2461. -/* DVB USB compliant Linux driver for the Afatech 9005
  2462. - * USB1.1 DVB-T receiver.
  2463. - *
  2464. - * Standard remote decode function
  2465. - *
  2466. - * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
  2467. - *
  2468. - * Thanks to Afatech who kindly provided information.
  2469. - *
  2470. - * This program is free software; you can redistribute it and/or modify
  2471. - * it under the terms of the GNU General Public License as published by
  2472. - * the Free Software Foundation; either version 2 of the License, or
  2473. - * (at your option) any later version.
  2474. - *
  2475. - * This program is distributed in the hope that it will be useful,
  2476. - * but WITHOUT ANY WARRANTY; without even the implied warranty of
  2477. - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  2478. - * GNU General Public License for more details.
  2479. - *
  2480. - * see Documentation/dvb/README.dvb-usb for more information
  2481. - */
  2482. -#include "af9005.h"
  2483. -/* debug */
  2484. -static int dvb_usb_af9005_remote_debug;
  2485. -module_param_named(debug, dvb_usb_af9005_remote_debug, int, 0644);
  2486. -MODULE_PARM_DESC(debug,
  2487. -		 "enable (1) or disable (0) debug messages."
  2488. -		 DVB_USB_DEBUG_STATUS);
  2489. -
  2490. -#define deb_decode(args...)   dprintk(dvb_usb_af9005_remote_debug,0x01,args)
  2491. -
  2492. -struct rc_map_table rc_map_af9005_table[] = {
  2493. -
  2494. -	{0x01b7, KEY_POWER},
  2495. -	{0x01a7, KEY_VOLUMEUP},
  2496. -	{0x0187, KEY_CHANNELUP},
  2497. -	{0x017f, KEY_MUTE},
  2498. -	{0x01bf, KEY_VOLUMEDOWN},
  2499. -	{0x013f, KEY_CHANNELDOWN},
  2500. -	{0x01df, KEY_1},
  2501. -	{0x015f, KEY_2},
  2502. -	{0x019f, KEY_3},
  2503. -	{0x011f, KEY_4},
  2504. -	{0x01ef, KEY_5},
  2505. -	{0x016f, KEY_6},
  2506. -	{0x01af, KEY_7},
  2507. -	{0x0127, KEY_8},
  2508. -	{0x0107, KEY_9},
  2509. -	{0x01cf, KEY_ZOOM},
  2510. -	{0x014f, KEY_0},
  2511. -	{0x018f, KEY_GOTO},	/* marked jump on the remote */
  2512. -
  2513. -	{0x00bd, KEY_POWER},
  2514. -	{0x007d, KEY_VOLUMEUP},
  2515. -	{0x00fd, KEY_CHANNELUP},
  2516. -	{0x009d, KEY_MUTE},
  2517. -	{0x005d, KEY_VOLUMEDOWN},
  2518. -	{0x00dd, KEY_CHANNELDOWN},
  2519. -	{0x00ad, KEY_1},
  2520. -	{0x006d, KEY_2},
  2521. -	{0x00ed, KEY_3},
  2522. -	{0x008d, KEY_4},
  2523. -	{0x004d, KEY_5},
  2524. -	{0x00cd, KEY_6},
  2525. -	{0x00b5, KEY_7},
  2526. -	{0x0075, KEY_8},
  2527. -	{0x00f5, KEY_9},
  2528. -	{0x0095, KEY_ZOOM},
  2529. -	{0x0055, KEY_0},
  2530. -	{0x00d5, KEY_GOTO},	/* marked jump on the remote */
  2531. -};
  2532. -
  2533. -int rc_map_af9005_table_size = ARRAY_SIZE(rc_map_af9005_table);
  2534. -
  2535. -static int repeatable_keys[] = {
  2536. -	KEY_VOLUMEUP,
  2537. -	KEY_VOLUMEDOWN,
  2538. -	KEY_CHANNELUP,
  2539. -	KEY_CHANNELDOWN
  2540. -};
  2541. -
  2542. -int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len, u32 * event,
  2543. -		     int *state)
  2544. -{
  2545. -	u16 mark, space;
  2546. -	u32 result;
  2547. -	u8 cust, dat, invdat;
  2548. -	int i;
  2549. -
  2550. -	if (len >= 6) {
  2551. -		mark = (u16) (data[0] << 8) + data[1];
  2552. -		space = (u16) (data[2] << 8) + data[3];
  2553. -		if (space * 3 < mark) {
  2554. -			for (i = 0; i < ARRAY_SIZE(repeatable_keys); i++) {
  2555. -				if (d->last_event == repeatable_keys[i]) {
  2556. -					*state = REMOTE_KEY_REPEAT;
  2557. -					*event = d->last_event;
  2558. -					deb_decode("repeat key, event %x\n",
  2559. -						   *event);
  2560. -					return 0;
  2561. -				}
  2562. -			}
  2563. -			deb_decode("repeated key ignored (non repeatable)\n");
  2564. -			return 0;
  2565. -		} else if (len >= 33 * 4) {	/*32 bits + start code */
  2566. -			result = 0;
  2567. -			for (i = 4; i < 4 + 32 * 4; i += 4) {
  2568. -				result <<= 1;
  2569. -				mark = (u16) (data[i] << 8) + data[i + 1];
  2570. -				mark >>= 1;
  2571. -				space = (u16) (data[i + 2] << 8) + data[i + 3];
  2572. -				space >>= 1;
  2573. -				if (mark * 2 > space)
  2574. -					result += 1;
  2575. -			}
  2576. -			deb_decode("key pressed, raw value %x\n", result);
  2577. -			if ((result & 0xff000000) != 0xfe000000) {
  2578. -				deb_decode
  2579. -				    ("doesn't start with 0xfe, ignored\n");
  2580. -				return 0;
  2581. -			}
  2582. -			cust = (result >> 16) & 0xff;
  2583. -			dat = (result >> 8) & 0xff;
  2584. -			invdat = (~result) & 0xff;
  2585. -			if (dat != invdat) {
  2586. -				deb_decode("code != inverted code\n");
  2587. -				return 0;
  2588. -			}
  2589. -			for (i = 0; i < rc_map_af9005_table_size; i++) {
  2590. -				if (rc5_custom(&rc_map_af9005_table[i]) == cust
  2591. -				    && rc5_data(&rc_map_af9005_table[i]) == dat) {
  2592. -					*event = rc_map_af9005_table[i].keycode;
  2593. -					*state = REMOTE_KEY_PRESSED;
  2594. -					deb_decode
  2595. -					    ("key pressed, event %x\n", *event);
  2596. -					return 0;
  2597. -				}
  2598. -			}
  2599. -			deb_decode("not found in table\n");
  2600. -		}
  2601. -	}
  2602. -	return 0;
  2603. -}
  2604. -
  2605. -EXPORT_SYMBOL(rc_map_af9005_table);
  2606. -EXPORT_SYMBOL(rc_map_af9005_table_size);
  2607. -EXPORT_SYMBOL(af9005_rc_decode);
  2608. -
  2609. -MODULE_AUTHOR("Luca Olivetti <luca@ventoso.org>");
  2610. -MODULE_DESCRIPTION
  2611. -    ("Standard remote control decoder for Afatech 9005 DVB-T USB1.1 stick");
  2612. -MODULE_VERSION("1.0");
  2613. -MODULE_LICENSE("GPL");
  2614. diff -ruN ../linux-4.14.336/drivers/media/usb/dvb-usb/af9005-script.h ./drivers/media/usb/dvb-usb/af9005-script.h
  2615. --- linux-4.14.336/../linux-4.14.336/drivers/media/usb/dvb-usb/af9005-script.h	2024-01-10 14:45:41.000000000 +0100
  2616. +++ linux-4.14.336/./drivers/media/usb/dvb-usb/af9005-script.h	1970-01-01 01:00:00.000000000 +0100
  2617. @@ -1,204 +0,0 @@
  2618. -/* SPDX-License-Identifier: GPL-2.0 */
  2619. -/*
  2620. -File automatically generated by createinit.py using data
  2621. -extracted from AF05BDA.sys (windows driver):
  2622. -
  2623. -dd if=AF05BDA.sys of=initsequence bs=1 skip=88316 count=1110
  2624. -python createinit.py > af9005-script.h
  2625. -
  2626. -*/
  2627. -
  2628. -typedef struct {
  2629. -	u16 reg;
  2630. -	u8 pos;
  2631. -	u8 len;
  2632. -	u8 val;
  2633. -} RegDesc;
  2634. -
  2635. -static RegDesc script[] = {
  2636. -	{0xa180, 0x0, 0x8, 0xa},
  2637. -	{0xa181, 0x0, 0x8, 0xd7},
  2638. -	{0xa182, 0x0, 0x8, 0xa3},
  2639. -	{0xa0a0, 0x0, 0x8, 0x0},
  2640. -	{0xa0a1, 0x0, 0x5, 0x0},
  2641. -	{0xa0a1, 0x5, 0x1, 0x1},
  2642. -	{0xa0c0, 0x0, 0x4, 0x1},
  2643. -	{0xa20e, 0x4, 0x4, 0xa},
  2644. -	{0xa20f, 0x0, 0x8, 0x40},
  2645. -	{0xa210, 0x0, 0x8, 0x8},
  2646. -	{0xa32a, 0x0, 0x4, 0xa},
  2647. -	{0xa32c, 0x0, 0x8, 0x20},
  2648. -	{0xa32b, 0x0, 0x8, 0x15},
  2649. -	{0xa1a0, 0x1, 0x1, 0x1},
  2650. -	{0xa000, 0x0, 0x1, 0x1},
  2651. -	{0xa000, 0x1, 0x1, 0x0},
  2652. -	{0xa001, 0x1, 0x1, 0x1},
  2653. -	{0xa001, 0x0, 0x1, 0x0},
  2654. -	{0xa001, 0x5, 0x1, 0x0},
  2655. -	{0xa00e, 0x0, 0x5, 0x10},
  2656. -	{0xa00f, 0x0, 0x3, 0x4},
  2657. -	{0xa00f, 0x3, 0x3, 0x5},
  2658. -	{0xa010, 0x0, 0x3, 0x4},
  2659. -	{0xa010, 0x3, 0x3, 0x5},
  2660. -	{0xa016, 0x4, 0x4, 0x3},
  2661. -	{0xa01f, 0x0, 0x6, 0xa},
  2662. -	{0xa020, 0x0, 0x6, 0xa},
  2663. -	{0xa2bc, 0x0, 0x1, 0x1},
  2664. -	{0xa2bc, 0x5, 0x1, 0x1},
  2665. -	{0xa015, 0x0, 0x8, 0x50},
  2666. -	{0xa016, 0x0, 0x1, 0x0},
  2667. -	{0xa02a, 0x0, 0x8, 0x50},
  2668. -	{0xa029, 0x0, 0x8, 0x4b},
  2669. -	{0xa614, 0x0, 0x8, 0x46},
  2670. -	{0xa002, 0x0, 0x5, 0x19},
  2671. -	{0xa003, 0x0, 0x5, 0x1a},
  2672. -	{0xa004, 0x0, 0x5, 0x19},
  2673. -	{0xa005, 0x0, 0x5, 0x1a},
  2674. -	{0xa008, 0x0, 0x8, 0x69},
  2675. -	{0xa009, 0x0, 0x2, 0x2},
  2676. -	{0xae1b, 0x0, 0x8, 0x69},
  2677. -	{0xae1c, 0x0, 0x8, 0x2},
  2678. -	{0xae1d, 0x0, 0x8, 0x2a},
  2679. -	{0xa022, 0x0, 0x8, 0xaa},
  2680. -	{0xa006, 0x0, 0x8, 0xc8},
  2681. -	{0xa007, 0x0, 0x2, 0x0},
  2682. -	{0xa00c, 0x0, 0x8, 0xba},
  2683. -	{0xa00d, 0x0, 0x2, 0x2},
  2684. -	{0xa608, 0x0, 0x8, 0xba},
  2685. -	{0xa60e, 0x0, 0x2, 0x2},
  2686. -	{0xa609, 0x0, 0x8, 0x80},
  2687. -	{0xa60e, 0x2, 0x2, 0x3},
  2688. -	{0xa00a, 0x0, 0x8, 0xb6},
  2689. -	{0xa00b, 0x0, 0x2, 0x0},
  2690. -	{0xa011, 0x0, 0x8, 0xb9},
  2691. -	{0xa012, 0x0, 0x2, 0x0},
  2692. -	{0xa013, 0x0, 0x8, 0xbd},
  2693. -	{0xa014, 0x0, 0x2, 0x2},
  2694. -	{0xa366, 0x0, 0x1, 0x1},
  2695. -	{0xa2bc, 0x3, 0x1, 0x0},
  2696. -	{0xa2bd, 0x0, 0x8, 0xa},
  2697. -	{0xa2be, 0x0, 0x8, 0x14},
  2698. -	{0xa2bf, 0x0, 0x8, 0x8},
  2699. -	{0xa60a, 0x0, 0x8, 0xbd},
  2700. -	{0xa60e, 0x4, 0x2, 0x2},
  2701. -	{0xa60b, 0x0, 0x8, 0x86},
  2702. -	{0xa60e, 0x6, 0x2, 0x3},
  2703. -	{0xa001, 0x2, 0x2, 0x1},
  2704. -	{0xa1c7, 0x0, 0x8, 0xf5},
  2705. -	{0xa03d, 0x0, 0x8, 0xb1},
  2706. -	{0xa616, 0x0, 0x8, 0xff},
  2707. -	{0xa617, 0x0, 0x8, 0xad},
  2708. -	{0xa618, 0x0, 0x8, 0xad},
  2709. -	{0xa61e, 0x3, 0x1, 0x1},
  2710. -	{0xae1a, 0x0, 0x8, 0x0},
  2711. -	{0xae19, 0x0, 0x8, 0xc8},
  2712. -	{0xae18, 0x0, 0x8, 0x61},
  2713. -	{0xa140, 0x0, 0x8, 0x0},
  2714. -	{0xa141, 0x0, 0x8, 0xc8},
  2715. -	{0xa142, 0x0, 0x7, 0x61},
  2716. -	{0xa023, 0x0, 0x8, 0xff},
  2717. -	{0xa021, 0x0, 0x8, 0xad},
  2718. -	{0xa026, 0x0, 0x1, 0x0},
  2719. -	{0xa024, 0x0, 0x8, 0xff},
  2720. -	{0xa025, 0x0, 0x8, 0xff},
  2721. -	{0xa1c8, 0x0, 0x8, 0xf},
  2722. -	{0xa2bc, 0x1, 0x1, 0x0},
  2723. -	{0xa60c, 0x0, 0x4, 0x5},
  2724. -	{0xa60c, 0x4, 0x4, 0x6},
  2725. -	{0xa60d, 0x0, 0x8, 0xa},
  2726. -	{0xa371, 0x0, 0x1, 0x1},
  2727. -	{0xa366, 0x1, 0x3, 0x7},
  2728. -	{0xa338, 0x0, 0x8, 0x10},
  2729. -	{0xa339, 0x0, 0x6, 0x7},
  2730. -	{0xa33a, 0x0, 0x6, 0x1f},
  2731. -	{0xa33b, 0x0, 0x8, 0xf6},
  2732. -	{0xa33c, 0x3, 0x5, 0x4},
  2733. -	{0xa33d, 0x4, 0x4, 0x0},
  2734. -	{0xa33d, 0x1, 0x1, 0x1},
  2735. -	{0xa33d, 0x2, 0x1, 0x1},
  2736. -	{0xa33d, 0x3, 0x1, 0x1},
  2737. -	{0xa16d, 0x0, 0x4, 0xf},
  2738. -	{0xa161, 0x0, 0x5, 0x5},
  2739. -	{0xa162, 0x0, 0x4, 0x5},
  2740. -	{0xa165, 0x0, 0x8, 0xff},
  2741. -	{0xa166, 0x0, 0x8, 0x9c},
  2742. -	{0xa2c3, 0x0, 0x4, 0x5},
  2743. -	{0xa61a, 0x0, 0x6, 0xf},
  2744. -	{0xb200, 0x0, 0x8, 0xa1},
  2745. -	{0xb201, 0x0, 0x8, 0x7},
  2746. -	{0xa093, 0x0, 0x1, 0x0},
  2747. -	{0xa093, 0x1, 0x5, 0xf},
  2748. -	{0xa094, 0x0, 0x8, 0xff},
  2749. -	{0xa095, 0x0, 0x8, 0xf},
  2750. -	{0xa080, 0x2, 0x5, 0x3},
  2751. -	{0xa081, 0x0, 0x4, 0x0},
  2752. -	{0xa081, 0x4, 0x4, 0x9},
  2753. -	{0xa082, 0x0, 0x5, 0x1f},
  2754. -	{0xa08d, 0x0, 0x8, 0x1},
  2755. -	{0xa083, 0x0, 0x8, 0x32},
  2756. -	{0xa084, 0x0, 0x1, 0x0},
  2757. -	{0xa08e, 0x0, 0x8, 0x3},
  2758. -	{0xa085, 0x0, 0x8, 0x32},
  2759. -	{0xa086, 0x0, 0x3, 0x0},
  2760. -	{0xa087, 0x0, 0x8, 0x6e},
  2761. -	{0xa088, 0x0, 0x5, 0x15},
  2762. -	{0xa089, 0x0, 0x8, 0x0},
  2763. -	{0xa08a, 0x0, 0x5, 0x19},
  2764. -	{0xa08b, 0x0, 0x8, 0x92},
  2765. -	{0xa08c, 0x0, 0x5, 0x1c},
  2766. -	{0xa120, 0x0, 0x8, 0x0},
  2767. -	{0xa121, 0x0, 0x5, 0x10},
  2768. -	{0xa122, 0x0, 0x8, 0x0},
  2769. -	{0xa123, 0x0, 0x7, 0x40},
  2770. -	{0xa123, 0x7, 0x1, 0x0},
  2771. -	{0xa124, 0x0, 0x8, 0x13},
  2772. -	{0xa125, 0x0, 0x7, 0x10},
  2773. -	{0xa1c0, 0x0, 0x8, 0x0},
  2774. -	{0xa1c1, 0x0, 0x5, 0x4},
  2775. -	{0xa1c2, 0x0, 0x8, 0x0},
  2776. -	{0xa1c3, 0x0, 0x5, 0x10},
  2777. -	{0xa1c3, 0x5, 0x3, 0x0},
  2778. -	{0xa1c4, 0x0, 0x6, 0x0},
  2779. -	{0xa1c5, 0x0, 0x7, 0x10},
  2780. -	{0xa100, 0x0, 0x8, 0x0},
  2781. -	{0xa101, 0x0, 0x5, 0x10},
  2782. -	{0xa102, 0x0, 0x8, 0x0},
  2783. -	{0xa103, 0x0, 0x7, 0x40},
  2784. -	{0xa103, 0x7, 0x1, 0x0},
  2785. -	{0xa104, 0x0, 0x8, 0x18},
  2786. -	{0xa105, 0x0, 0x7, 0xa},
  2787. -	{0xa106, 0x0, 0x8, 0x20},
  2788. -	{0xa107, 0x0, 0x8, 0x40},
  2789. -	{0xa108, 0x0, 0x4, 0x0},
  2790. -	{0xa38c, 0x0, 0x8, 0xfc},
  2791. -	{0xa38d, 0x0, 0x8, 0x0},
  2792. -	{0xa38e, 0x0, 0x8, 0x7e},
  2793. -	{0xa38f, 0x0, 0x8, 0x0},
  2794. -	{0xa390, 0x0, 0x8, 0x2f},
  2795. -	{0xa60f, 0x5, 0x1, 0x1},
  2796. -	{0xa170, 0x0, 0x8, 0xdc},
  2797. -	{0xa171, 0x0, 0x2, 0x0},
  2798. -	{0xa2ae, 0x0, 0x1, 0x1},
  2799. -	{0xa2ae, 0x1, 0x1, 0x1},
  2800. -	{0xa392, 0x0, 0x1, 0x1},
  2801. -	{0xa391, 0x2, 0x1, 0x0},
  2802. -	{0xabc1, 0x0, 0x8, 0xff},
  2803. -	{0xabc2, 0x0, 0x8, 0x0},
  2804. -	{0xabc8, 0x0, 0x8, 0x8},
  2805. -	{0xabca, 0x0, 0x8, 0x10},
  2806. -	{0xabcb, 0x0, 0x1, 0x0},
  2807. -	{0xabc3, 0x5, 0x3, 0x7},
  2808. -	{0xabc0, 0x6, 0x1, 0x0},
  2809. -	{0xabc0, 0x4, 0x2, 0x0},
  2810. -	{0xa344, 0x4, 0x4, 0x1},
  2811. -	{0xabc0, 0x7, 0x1, 0x1},
  2812. -	{0xabc0, 0x2, 0x1, 0x1},
  2813. -	{0xa345, 0x0, 0x8, 0x66},
  2814. -	{0xa346, 0x0, 0x8, 0x66},
  2815. -	{0xa347, 0x0, 0x4, 0x0},
  2816. -	{0xa343, 0x0, 0x4, 0xa},
  2817. -	{0xa347, 0x4, 0x4, 0x2},
  2818. -	{0xa348, 0x0, 0x4, 0xc},
  2819. -	{0xa348, 0x4, 0x4, 0x7},
  2820. -	{0xa349, 0x0, 0x6, 0x2},
  2821. -};
  2822. diff -ruN ../linux-4.14.336/drivers/media/usb/dvb-usb/af9005.c ./drivers/media/usb/dvb-usb/af9005.c
  2823. --- linux-4.14.336/../linux-4.14.336/drivers/media/usb/dvb-usb/af9005.c	2024-01-10 14:45:41.000000000 +0100
  2824. +++ linux-4.14.336/./drivers/media/usb/dvb-usb/af9005.c	1970-01-01 01:00:00.000000000 +0100
  2825. @@ -1,1151 +0,0 @@
  2826. -/* DVB USB compliant Linux driver for the Afatech 9005
  2827. - * USB1.1 DVB-T receiver.
  2828. - *
  2829. - * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
  2830. - *
  2831. - * Thanks to Afatech who kindly provided information.
  2832. - *
  2833. - * This program is free software; you can redistribute it and/or modify
  2834. - * it under the terms of the GNU General Public License as published by
  2835. - * the Free Software Foundation; either version 2 of the License, or
  2836. - * (at your option) any later version.
  2837. - *
  2838. - * This program is distributed in the hope that it will be useful,
  2839. - * but WITHOUT ANY WARRANTY; without even the implied warranty of
  2840. - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  2841. - * GNU General Public License for more details.
  2842. - *
  2843. - * see Documentation/dvb/README.dvb-usb for more information
  2844. - */
  2845. -#include "af9005.h"
  2846. -
  2847. -/* debug */
  2848. -int dvb_usb_af9005_debug;
  2849. -module_param_named(debug, dvb_usb_af9005_debug, int, 0644);
  2850. -MODULE_PARM_DESC(debug,
  2851. -		 "set debugging level (1=info,xfer=2,rc=4,reg=8,i2c=16,fw=32 (or-able))."
  2852. -		 DVB_USB_DEBUG_STATUS);
  2853. -/* enable obnoxious led */
  2854. -bool dvb_usb_af9005_led = true;
  2855. -module_param_named(led, dvb_usb_af9005_led, bool, 0644);
  2856. -MODULE_PARM_DESC(led, "enable led (default: 1).");
  2857. -
  2858. -/* eeprom dump */
  2859. -static int dvb_usb_af9005_dump_eeprom;
  2860. -module_param_named(dump_eeprom, dvb_usb_af9005_dump_eeprom, int, 0);
  2861. -MODULE_PARM_DESC(dump_eeprom, "dump contents of the eeprom.");
  2862. -
  2863. -DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  2864. -
  2865. -/* remote control decoder */
  2866. -static int (*rc_decode) (struct dvb_usb_device *d, u8 *data, int len,
  2867. -		u32 *event, int *state);
  2868. -static void *rc_keys;
  2869. -static int *rc_keys_size;
  2870. -
  2871. -u8 regmask[8] = { 0x01, 0x03, 0x07, 0x0f, 0x1f, 0x3f, 0x7f, 0xff };
  2872. -
  2873. -struct af9005_device_state {
  2874. -	u8 sequence;
  2875. -	int led_state;
  2876. -	unsigned char data[256];
  2877. -};
  2878. -
  2879. -static int af9005_generic_read_write(struct dvb_usb_device *d, u16 reg,
  2880. -			      int readwrite, int type, u8 * values, int len)
  2881. -{
  2882. -	struct af9005_device_state *st = d->priv;
  2883. -	u8 command, seq;
  2884. -	int i, ret;
  2885. -
  2886. -	if (len < 1) {
  2887. -		err("generic read/write, less than 1 byte. Makes no sense.");
  2888. -		return -EINVAL;
  2889. -	}
  2890. -	if (len > 8) {
  2891. -		err("generic read/write, more than 8 bytes. Not supported.");
  2892. -		return -EINVAL;
  2893. -	}
  2894. -
  2895. -	mutex_lock(&d->data_mutex);
  2896. -	st->data[0] = 14;		/* rest of buffer length low */
  2897. -	st->data[1] = 0;		/* rest of buffer length high */
  2898. -
  2899. -	st->data[2] = AF9005_REGISTER_RW;	/* register operation */
  2900. -	st->data[3] = 12;		/* rest of buffer length */
  2901. -
  2902. -	st->data[4] = seq = st->sequence++;	/* sequence number */
  2903. -
  2904. -	st->data[5] = (u8) (reg >> 8);	/* register address */
  2905. -	st->data[6] = (u8) (reg & 0xff);
  2906. -
  2907. -	if (type == AF9005_OFDM_REG) {
  2908. -		command = AF9005_CMD_OFDM_REG;
  2909. -	} else {
  2910. -		command = AF9005_CMD_TUNER;
  2911. -	}
  2912. -
  2913. -	if (len > 1)
  2914. -		command |=
  2915. -		    AF9005_CMD_BURST | AF9005_CMD_AUTOINC | (len - 1) << 3;
  2916. -	command |= readwrite;
  2917. -	if (readwrite == AF9005_CMD_WRITE)
  2918. -		for (i = 0; i < len; i++)
  2919. -			st->data[8 + i] = values[i];
  2920. -	else if (type == AF9005_TUNER_REG)
  2921. -		/* read command for tuner, the first byte contains the i2c address */
  2922. -		st->data[8] = values[0];
  2923. -	st->data[7] = command;
  2924. -
  2925. -	ret = dvb_usb_generic_rw(d, st->data, 16, st->data, 17, 0);
  2926. -	if (ret)
  2927. -		goto ret;
  2928. -
  2929. -	/* sanity check */
  2930. -	if (st->data[2] != AF9005_REGISTER_RW_ACK) {
  2931. -		err("generic read/write, wrong reply code.");
  2932. -		ret = -EIO;
  2933. -		goto ret;
  2934. -	}
  2935. -	if (st->data[3] != 0x0d) {
  2936. -		err("generic read/write, wrong length in reply.");
  2937. -		ret = -EIO;
  2938. -		goto ret;
  2939. -	}
  2940. -	if (st->data[4] != seq) {
  2941. -		err("generic read/write, wrong sequence in reply.");
  2942. -		ret = -EIO;
  2943. -		goto ret;
  2944. -	}
  2945. -	/*
  2946. -	 * In thesis, both input and output buffers should have
  2947. -	 * identical values for st->data[5] to st->data[8].
  2948. -	 * However, windows driver doesn't check these fields, in fact
  2949. -	 * sometimes the register in the reply is different that what
  2950. -	 * has been sent
  2951. -	 */
  2952. -	if (st->data[16] != 0x01) {
  2953. -		err("generic read/write wrong status code in reply.");
  2954. -		ret = -EIO;
  2955. -		goto ret;
  2956. -	}
  2957. -
  2958. -	if (readwrite == AF9005_CMD_READ)
  2959. -		for (i = 0; i < len; i++)
  2960. -			values[i] = st->data[8 + i];
  2961. -
  2962. -ret:
  2963. -	mutex_unlock(&d->data_mutex);
  2964. -	return ret;
  2965. -
  2966. -}
  2967. -
  2968. -int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg, u8 * value)
  2969. -{
  2970. -	int ret;
  2971. -	deb_reg("read register %x ", reg);
  2972. -	ret = af9005_generic_read_write(d, reg,
  2973. -					AF9005_CMD_READ, AF9005_OFDM_REG,
  2974. -					value, 1);
  2975. -	if (ret)
  2976. -		deb_reg("failed\n");
  2977. -	else
  2978. -		deb_reg("value %x\n", *value);
  2979. -	return ret;
  2980. -}
  2981. -
  2982. -int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg,
  2983. -			       u8 * values, int len)
  2984. -{
  2985. -	int ret;
  2986. -	deb_reg("read %d registers %x ", len, reg);
  2987. -	ret = af9005_generic_read_write(d, reg,
  2988. -					AF9005_CMD_READ, AF9005_OFDM_REG,
  2989. -					values, len);
  2990. -	if (ret)
  2991. -		deb_reg("failed\n");
  2992. -	else
  2993. -		debug_dump(values, len, deb_reg);
  2994. -	return ret;
  2995. -}
  2996. -
  2997. -int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg, u8 value)
  2998. -{
  2999. -	int ret;
  3000. -	u8 temp = value;
  3001. -	deb_reg("write register %x value %x ", reg, value);
  3002. -	ret = af9005_generic_read_write(d, reg,
  3003. -					AF9005_CMD_WRITE, AF9005_OFDM_REG,
  3004. -					&temp, 1);
  3005. -	if (ret)
  3006. -		deb_reg("failed\n");
  3007. -	else
  3008. -		deb_reg("ok\n");
  3009. -	return ret;
  3010. -}
  3011. -
  3012. -int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg,
  3013. -				u8 * values, int len)
  3014. -{
  3015. -	int ret;
  3016. -	deb_reg("write %d registers %x values ", len, reg);
  3017. -	debug_dump(values, len, deb_reg);
  3018. -
  3019. -	ret = af9005_generic_read_write(d, reg,
  3020. -					AF9005_CMD_WRITE, AF9005_OFDM_REG,
  3021. -					values, len);
  3022. -	if (ret)
  3023. -		deb_reg("failed\n");
  3024. -	else
  3025. -		deb_reg("ok\n");
  3026. -	return ret;
  3027. -}
  3028. -
  3029. -int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg, u8 pos,
  3030. -			      u8 len, u8 * value)
  3031. -{
  3032. -	u8 temp;
  3033. -	int ret;
  3034. -	deb_reg("read bits %x %x %x", reg, pos, len);
  3035. -	ret = af9005_read_ofdm_register(d, reg, &temp);
  3036. -	if (ret) {
  3037. -		deb_reg(" failed\n");
  3038. -		return ret;
  3039. -	}
  3040. -	*value = (temp >> pos) & regmask[len - 1];
  3041. -	deb_reg(" value %x\n", *value);
  3042. -	return 0;
  3043. -
  3044. -}
  3045. -
  3046. -int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg, u8 pos,
  3047. -			       u8 len, u8 value)
  3048. -{
  3049. -	u8 temp, mask;
  3050. -	int ret;
  3051. -	deb_reg("write bits %x %x %x value %x\n", reg, pos, len, value);
  3052. -	if (pos == 0 && len == 8)
  3053. -		return af9005_write_ofdm_register(d, reg, value);
  3054. -	ret = af9005_read_ofdm_register(d, reg, &temp);
  3055. -	if (ret)
  3056. -		return ret;
  3057. -	mask = regmask[len - 1] << pos;
  3058. -	temp = (temp & ~mask) | ((value << pos) & mask);
  3059. -	return af9005_write_ofdm_register(d, reg, temp);
  3060. -
  3061. -}
  3062. -
  3063. -static int af9005_usb_read_tuner_registers(struct dvb_usb_device *d,
  3064. -					   u16 reg, u8 * values, int len)
  3065. -{
  3066. -	return af9005_generic_read_write(d, reg,
  3067. -					 AF9005_CMD_READ, AF9005_TUNER_REG,
  3068. -					 values, len);
  3069. -}
  3070. -
  3071. -static int af9005_usb_write_tuner_registers(struct dvb_usb_device *d,
  3072. -					    u16 reg, u8 * values, int len)
  3073. -{
  3074. -	return af9005_generic_read_write(d, reg,
  3075. -					 AF9005_CMD_WRITE,
  3076. -					 AF9005_TUNER_REG, values, len);
  3077. -}
  3078. -
  3079. -int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg,
  3080. -				 u8 * values, int len)
  3081. -{
  3082. -	/* don't let the name of this function mislead you: it's just used
  3083. -	   as an interface from the firmware to the i2c bus. The actual
  3084. -	   i2c addresses are contained in the data */
  3085. -	int ret, i, done = 0, fail = 0;
  3086. -	u8 temp;
  3087. -	ret = af9005_usb_write_tuner_registers(d, reg, values, len);
  3088. -	if (ret)
  3089. -		return ret;
  3090. -	if (reg != 0xffff) {
  3091. -		/* check if write done (0xa40d bit 1) or fail (0xa40d bit 2) */
  3092. -		for (i = 0; i < 200; i++) {
  3093. -			ret =
  3094. -			    af9005_read_ofdm_register(d,
  3095. -						      xd_I2C_i2c_m_status_wdat_done,
  3096. -						      &temp);
  3097. -			if (ret)
  3098. -				return ret;
  3099. -			done = temp & (regmask[i2c_m_status_wdat_done_len - 1]
  3100. -				       << i2c_m_status_wdat_done_pos);
  3101. -			if (done)
  3102. -				break;
  3103. -			fail = temp & (regmask[i2c_m_status_wdat_fail_len - 1]
  3104. -				       << i2c_m_status_wdat_fail_pos);
  3105. -			if (fail)
  3106. -				break;
  3107. -			msleep(50);
  3108. -		}
  3109. -		if (i == 200)
  3110. -			return -ETIMEDOUT;
  3111. -		if (fail) {
  3112. -			/* clear write fail bit */
  3113. -			af9005_write_register_bits(d,
  3114. -						   xd_I2C_i2c_m_status_wdat_fail,
  3115. -						   i2c_m_status_wdat_fail_pos,
  3116. -						   i2c_m_status_wdat_fail_len,
  3117. -						   1);
  3118. -			return -EIO;
  3119. -		}
  3120. -		/* clear write done bit */
  3121. -		ret =
  3122. -		    af9005_write_register_bits(d,
  3123. -					       xd_I2C_i2c_m_status_wdat_fail,
  3124. -					       i2c_m_status_wdat_done_pos,
  3125. -					       i2c_m_status_wdat_done_len, 1);
  3126. -		if (ret)
  3127. -			return ret;
  3128. -	}
  3129. -	return 0;
  3130. -}
  3131. -
  3132. -int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg, u8 addr,
  3133. -				u8 * values, int len)
  3134. -{
  3135. -	/* don't let the name of this function mislead you: it's just used
  3136. -	   as an interface from the firmware to the i2c bus. The actual
  3137. -	   i2c addresses are contained in the data */
  3138. -	int ret, i;
  3139. -	u8 temp, buf[2];
  3140. -
  3141. -	buf[0] = addr;		/* tuner i2c address */
  3142. -	buf[1] = values[0];	/* tuner register */
  3143. -
  3144. -	values[0] = addr + 0x01;	/* i2c read address */
  3145. -
  3146. -	if (reg == APO_REG_I2C_RW_SILICON_TUNER) {
  3147. -		/* write tuner i2c address to tuner, 0c00c0 undocumented, found by sniffing */
  3148. -		ret = af9005_write_tuner_registers(d, 0x00c0, buf, 2);
  3149. -		if (ret)
  3150. -			return ret;
  3151. -	}
  3152. -
  3153. -	/* send read command to ofsm */
  3154. -	ret = af9005_usb_read_tuner_registers(d, reg, values, 1);
  3155. -	if (ret)
  3156. -		return ret;
  3157. -
  3158. -	/* check if read done */
  3159. -	for (i = 0; i < 200; i++) {
  3160. -		ret = af9005_read_ofdm_register(d, 0xa408, &temp);
  3161. -		if (ret)
  3162. -			return ret;
  3163. -		if (temp & 0x01)
  3164. -			break;
  3165. -		msleep(50);
  3166. -	}
  3167. -	if (i == 200)
  3168. -		return -ETIMEDOUT;
  3169. -
  3170. -	/* clear read done bit (by writing 1) */
  3171. -	ret = af9005_write_ofdm_register(d, xd_I2C_i2c_m_data8, 1);
  3172. -	if (ret)
  3173. -		return ret;
  3174. -
  3175. -	/* get read data (available from 0xa400) */
  3176. -	for (i = 0; i < len; i++) {
  3177. -		ret = af9005_read_ofdm_register(d, 0xa400 + i, &temp);
  3178. -		if (ret)
  3179. -			return ret;
  3180. -		values[i] = temp;
  3181. -	}
  3182. -	return 0;
  3183. -}
  3184. -
  3185. -static int af9005_i2c_write(struct dvb_usb_device *d, u8 i2caddr, u8 reg,
  3186. -			    u8 * data, int len)
  3187. -{
  3188. -	int ret, i;
  3189. -	u8 buf[3];
  3190. -	deb_i2c("i2c_write i2caddr %x, reg %x, len %d data ", i2caddr,
  3191. -		reg, len);
  3192. -	debug_dump(data, len, deb_i2c);
  3193. -
  3194. -	for (i = 0; i < len; i++) {
  3195. -		buf[0] = i2caddr;
  3196. -		buf[1] = reg + (u8) i;
  3197. -		buf[2] = data[i];
  3198. -		ret =
  3199. -		    af9005_write_tuner_registers(d,
  3200. -						 APO_REG_I2C_RW_SILICON_TUNER,
  3201. -						 buf, 3);
  3202. -		if (ret) {
  3203. -			deb_i2c("i2c_write failed\n");
  3204. -			return ret;
  3205. -		}
  3206. -	}
  3207. -	deb_i2c("i2c_write ok\n");
  3208. -	return 0;
  3209. -}
  3210. -
  3211. -static int af9005_i2c_read(struct dvb_usb_device *d, u8 i2caddr, u8 reg,
  3212. -			   u8 * data, int len)
  3213. -{
  3214. -	int ret, i;
  3215. -	u8 temp;
  3216. -	deb_i2c("i2c_read i2caddr %x, reg %x, len %d\n ", i2caddr, reg, len);
  3217. -	for (i = 0; i < len; i++) {
  3218. -		temp = reg + i;
  3219. -		ret =
  3220. -		    af9005_read_tuner_registers(d,
  3221. -						APO_REG_I2C_RW_SILICON_TUNER,
  3222. -						i2caddr, &temp, 1);
  3223. -		if (ret) {
  3224. -			deb_i2c("i2c_read failed\n");
  3225. -			return ret;
  3226. -		}
  3227. -		data[i] = temp;
  3228. -	}
  3229. -	deb_i2c("i2c data read: ");
  3230. -	debug_dump(data, len, deb_i2c);
  3231. -	return 0;
  3232. -}
  3233. -
  3234. -static int af9005_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msg[],
  3235. -			   int num)
  3236. -{
  3237. -	/* only implements what the mt2060 module does, don't know how
  3238. -	   to make it really generic */
  3239. -	struct dvb_usb_device *d = i2c_get_adapdata(adap);
  3240. -	int ret;
  3241. -	u8 reg, addr;
  3242. -	u8 *value;
  3243. -
  3244. -	if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
  3245. -		return -EAGAIN;
  3246. -
  3247. -	if (num > 2)
  3248. -		warn("more than 2 i2c messages at a time is not handled yet. TODO.");
  3249. -
  3250. -	if (num == 2) {
  3251. -		/* reads a single register */
  3252. -		reg = *msg[0].buf;
  3253. -		addr = msg[0].addr;
  3254. -		value = msg[1].buf;
  3255. -		ret = af9005_i2c_read(d, addr, reg, value, 1);
  3256. -		if (ret == 0)
  3257. -			ret = 2;
  3258. -	} else {
  3259. -		if (msg[0].len < 2) {
  3260. -			ret = -EOPNOTSUPP;
  3261. -			goto unlock;
  3262. -		}
  3263. -		/* write one or more registers */
  3264. -		reg = msg[0].buf[0];
  3265. -		addr = msg[0].addr;
  3266. -		value = &msg[0].buf[1];
  3267. -		ret = af9005_i2c_write(d, addr, reg, value, msg[0].len - 1);
  3268. -		if (ret == 0)
  3269. -			ret = 1;
  3270. -	}
  3271. -
  3272. -unlock:
  3273. -	mutex_unlock(&d->i2c_mutex);
  3274. -	return ret;
  3275. -}
  3276. -
  3277. -static u32 af9005_i2c_func(struct i2c_adapter *adapter)
  3278. -{
  3279. -	return I2C_FUNC_I2C;
  3280. -}
  3281. -
  3282. -static struct i2c_algorithm af9005_i2c_algo = {
  3283. -	.master_xfer = af9005_i2c_xfer,
  3284. -	.functionality = af9005_i2c_func,
  3285. -};
  3286. -
  3287. -int af9005_send_command(struct dvb_usb_device *d, u8 command, u8 * wbuf,
  3288. -			int wlen, u8 * rbuf, int rlen)
  3289. -{
  3290. -	struct af9005_device_state *st = d->priv;
  3291. -
  3292. -	int ret, i, packet_len;
  3293. -	u8 seq;
  3294. -
  3295. -	if (wlen < 0) {
  3296. -		err("send command, wlen less than 0 bytes. Makes no sense.");
  3297. -		return -EINVAL;
  3298. -	}
  3299. -	if (wlen > 54) {
  3300. -		err("send command, wlen more than 54 bytes. Not supported.");
  3301. -		return -EINVAL;
  3302. -	}
  3303. -	if (rlen > 54) {
  3304. -		err("send command, rlen more than 54 bytes. Not supported.");
  3305. -		return -EINVAL;
  3306. -	}
  3307. -	packet_len = wlen + 5;
  3308. -
  3309. -	mutex_lock(&d->data_mutex);
  3310. -
  3311. -	st->data[0] = (u8) (packet_len & 0xff);
  3312. -	st->data[1] = (u8) ((packet_len & 0xff00) >> 8);
  3313. -
  3314. -	st->data[2] = 0x26;		/* packet type */
  3315. -	st->data[3] = wlen + 3;
  3316. -	st->data[4] = seq = st->sequence++;
  3317. -	st->data[5] = command;
  3318. -	st->data[6] = wlen;
  3319. -	for (i = 0; i < wlen; i++)
  3320. -		st->data[7 + i] = wbuf[i];
  3321. -	ret = dvb_usb_generic_rw(d, st->data, wlen + 7, st->data, rlen + 7, 0);
  3322. -	if (st->data[2] != 0x27) {
  3323. -		err("send command, wrong reply code.");
  3324. -		ret = -EIO;
  3325. -	} else if (st->data[4] != seq) {
  3326. -		err("send command, wrong sequence in reply.");
  3327. -		ret = -EIO;
  3328. -	} else if (st->data[5] != 0x01) {
  3329. -		err("send command, wrong status code in reply.");
  3330. -		ret = -EIO;
  3331. -	} else if (st->data[6] != rlen) {
  3332. -		err("send command, invalid data length in reply.");
  3333. -		ret = -EIO;
  3334. -	}
  3335. -	if (!ret) {
  3336. -		for (i = 0; i < rlen; i++)
  3337. -			rbuf[i] = st->data[i + 7];
  3338. -	}
  3339. -
  3340. -	mutex_unlock(&d->data_mutex);
  3341. -	return ret;
  3342. -}
  3343. -
  3344. -int af9005_read_eeprom(struct dvb_usb_device *d, u8 address, u8 * values,
  3345. -		       int len)
  3346. -{
  3347. -	struct af9005_device_state *st = d->priv;
  3348. -	u8 seq;
  3349. -	int ret, i;
  3350. -
  3351. -	mutex_lock(&d->data_mutex);
  3352. -
  3353. -	memset(st->data, 0, sizeof(st->data));
  3354. -
  3355. -	st->data[0] = 14;		/* length of rest of packet low */
  3356. -	st->data[1] = 0;		/* length of rest of packer high */
  3357. -
  3358. -	st->data[2] = 0x2a;		/* read/write eeprom */
  3359. -
  3360. -	st->data[3] = 12;		/* size */
  3361. -
  3362. -	st->data[4] = seq = st->sequence++;
  3363. -
  3364. -	st->data[5] = 0;		/* read */
  3365. -
  3366. -	st->data[6] = len;
  3367. -	st->data[7] = address;
  3368. -	ret = dvb_usb_generic_rw(d, st->data, 16, st->data, 14, 0);
  3369. -	if (st->data[2] != 0x2b) {
  3370. -		err("Read eeprom, invalid reply code");
  3371. -		ret = -EIO;
  3372. -	} else if (st->data[3] != 10) {
  3373. -		err("Read eeprom, invalid reply length");
  3374. -		ret = -EIO;
  3375. -	} else if (st->data[4] != seq) {
  3376. -		err("Read eeprom, wrong sequence in reply ");
  3377. -		ret = -EIO;
  3378. -	} else if (st->data[5] != 1) {
  3379. -		err("Read eeprom, wrong status in reply ");
  3380. -		ret = -EIO;
  3381. -	}
  3382. -
  3383. -	if (!ret) {
  3384. -		for (i = 0; i < len; i++)
  3385. -			values[i] = st->data[6 + i];
  3386. -	}
  3387. -	mutex_unlock(&d->data_mutex);
  3388. -
  3389. -	return ret;
  3390. -}
  3391. -
  3392. -static int af9005_boot_packet(struct usb_device *udev, int type, u8 *reply,
  3393. -			      u8 *buf, int size)
  3394. -{
  3395. -	u16 checksum;
  3396. -	int act_len = 0, i, ret;
  3397. -
  3398. -	memset(buf, 0, size);
  3399. -	buf[0] = (u8) (FW_BULKOUT_SIZE & 0xff);
  3400. -	buf[1] = (u8) ((FW_BULKOUT_SIZE >> 8) & 0xff);
  3401. -	switch (type) {
  3402. -	case FW_CONFIG:
  3403. -		buf[2] = 0x11;
  3404. -		buf[3] = 0x04;
  3405. -		buf[4] = 0x00;	/* sequence number, original driver doesn't increment it here */
  3406. -		buf[5] = 0x03;
  3407. -		checksum = buf[4] + buf[5];
  3408. -		buf[6] = (u8) ((checksum >> 8) & 0xff);
  3409. -		buf[7] = (u8) (checksum & 0xff);
  3410. -		break;
  3411. -	case FW_CONFIRM:
  3412. -		buf[2] = 0x11;
  3413. -		buf[3] = 0x04;
  3414. -		buf[4] = 0x00;	/* sequence number, original driver doesn't increment it here */
  3415. -		buf[5] = 0x01;
  3416. -		checksum = buf[4] + buf[5];
  3417. -		buf[6] = (u8) ((checksum >> 8) & 0xff);
  3418. -		buf[7] = (u8) (checksum & 0xff);
  3419. -		break;
  3420. -	case FW_BOOT:
  3421. -		buf[2] = 0x10;
  3422. -		buf[3] = 0x08;
  3423. -		buf[4] = 0x00;	/* sequence number, original driver doesn't increment it here */
  3424. -		buf[5] = 0x97;
  3425. -		buf[6] = 0xaa;
  3426. -		buf[7] = 0x55;
  3427. -		buf[8] = 0xa5;
  3428. -		buf[9] = 0x5a;
  3429. -		checksum = 0;
  3430. -		for (i = 4; i <= 9; i++)
  3431. -			checksum += buf[i];
  3432. -		buf[10] = (u8) ((checksum >> 8) & 0xff);
  3433. -		buf[11] = (u8) (checksum & 0xff);
  3434. -		break;
  3435. -	default:
  3436. -		err("boot packet invalid boot packet type");
  3437. -		return -EINVAL;
  3438. -	}
  3439. -	deb_fw(">>> ");
  3440. -	debug_dump(buf, FW_BULKOUT_SIZE + 2, deb_fw);
  3441. -
  3442. -	ret = usb_bulk_msg(udev,
  3443. -			   usb_sndbulkpipe(udev, 0x02),
  3444. -			   buf, FW_BULKOUT_SIZE + 2, &act_len, 2000);
  3445. -	if (ret)
  3446. -		err("boot packet bulk message failed: %d (%d/%d)", ret,
  3447. -		    FW_BULKOUT_SIZE + 2, act_len);
  3448. -	else
  3449. -		ret = act_len != FW_BULKOUT_SIZE + 2 ? -1 : 0;
  3450. -	if (ret)
  3451. -		return ret;
  3452. -	memset(buf, 0, 9);
  3453. -	ret = usb_bulk_msg(udev,
  3454. -			   usb_rcvbulkpipe(udev, 0x01), buf, 9, &act_len, 2000);
  3455. -	if (ret) {
  3456. -		err("boot packet recv bulk message failed: %d", ret);
  3457. -		return ret;
  3458. -	}
  3459. -	deb_fw("<<< ");
  3460. -	debug_dump(buf, act_len, deb_fw);
  3461. -	checksum = 0;
  3462. -	switch (type) {
  3463. -	case FW_CONFIG:
  3464. -		if (buf[2] != 0x11) {
  3465. -			err("boot bad config header.");
  3466. -			return -EIO;
  3467. -		}
  3468. -		if (buf[3] != 0x05) {
  3469. -			err("boot bad config size.");
  3470. -			return -EIO;
  3471. -		}
  3472. -		if (buf[4] != 0x00) {
  3473. -			err("boot bad config sequence.");
  3474. -			return -EIO;
  3475. -		}
  3476. -		if (buf[5] != 0x04) {
  3477. -			err("boot bad config subtype.");
  3478. -			return -EIO;
  3479. -		}
  3480. -		for (i = 4; i <= 6; i++)
  3481. -			checksum += buf[i];
  3482. -		if (buf[7] * 256 + buf[8] != checksum) {
  3483. -			err("boot bad config checksum.");
  3484. -			return -EIO;
  3485. -		}
  3486. -		*reply = buf[6];
  3487. -		break;
  3488. -	case FW_CONFIRM:
  3489. -		if (buf[2] != 0x11) {
  3490. -			err("boot bad confirm header.");
  3491. -			return -EIO;
  3492. -		}
  3493. -		if (buf[3] != 0x05) {
  3494. -			err("boot bad confirm size.");
  3495. -			return -EIO;
  3496. -		}
  3497. -		if (buf[4] != 0x00) {
  3498. -			err("boot bad confirm sequence.");
  3499. -			return -EIO;
  3500. -		}
  3501. -		if (buf[5] != 0x02) {
  3502. -			err("boot bad confirm subtype.");
  3503. -			return -EIO;
  3504. -		}
  3505. -		for (i = 4; i <= 6; i++)
  3506. -			checksum += buf[i];
  3507. -		if (buf[7] * 256 + buf[8] != checksum) {
  3508. -			err("boot bad confirm checksum.");
  3509. -			return -EIO;
  3510. -		}
  3511. -		*reply = buf[6];
  3512. -		break;
  3513. -	case FW_BOOT:
  3514. -		if (buf[2] != 0x10) {
  3515. -			err("boot bad boot header.");
  3516. -			return -EIO;
  3517. -		}
  3518. -		if (buf[3] != 0x05) {
  3519. -			err("boot bad boot size.");
  3520. -			return -EIO;
  3521. -		}
  3522. -		if (buf[4] != 0x00) {
  3523. -			err("boot bad boot sequence.");
  3524. -			return -EIO;
  3525. -		}
  3526. -		if (buf[5] != 0x01) {
  3527. -			err("boot bad boot pattern 01.");
  3528. -			return -EIO;
  3529. -		}
  3530. -		if (buf[6] != 0x10) {
  3531. -			err("boot bad boot pattern 10.");
  3532. -			return -EIO;
  3533. -		}
  3534. -		for (i = 4; i <= 6; i++)
  3535. -			checksum += buf[i];
  3536. -		if (buf[7] * 256 + buf[8] != checksum) {
  3537. -			err("boot bad boot checksum.");
  3538. -			return -EIO;
  3539. -		}
  3540. -		break;
  3541. -
  3542. -	}
  3543. -
  3544. -	return 0;
  3545. -}
  3546. -
  3547. -static int af9005_download_firmware(struct usb_device *udev, const struct firmware *fw)
  3548. -{
  3549. -	int i, packets, ret, act_len;
  3550. -
  3551. -	u8 *buf;
  3552. -	u8 reply;
  3553. -
  3554. -	buf = kmalloc(FW_BULKOUT_SIZE + 2, GFP_KERNEL);
  3555. -	if (!buf)
  3556. -		return -ENOMEM;
  3557. -
  3558. -	ret = af9005_boot_packet(udev, FW_CONFIG, &reply, buf,
  3559. -				 FW_BULKOUT_SIZE + 2);
  3560. -	if (ret)
  3561. -		goto err;
  3562. -	if (reply != 0x01) {
  3563. -		err("before downloading firmware, FW_CONFIG expected 0x01, received 0x%x", reply);
  3564. -		ret = -EIO;
  3565. -		goto err;
  3566. -	}
  3567. -	packets = fw->size / FW_BULKOUT_SIZE;
  3568. -	buf[0] = (u8) (FW_BULKOUT_SIZE & 0xff);
  3569. -	buf[1] = (u8) ((FW_BULKOUT_SIZE >> 8) & 0xff);
  3570. -	for (i = 0; i < packets; i++) {
  3571. -		memcpy(&buf[2], fw->data + i * FW_BULKOUT_SIZE,
  3572. -		       FW_BULKOUT_SIZE);
  3573. -		deb_fw(">>> ");
  3574. -		debug_dump(buf, FW_BULKOUT_SIZE + 2, deb_fw);
  3575. -		ret = usb_bulk_msg(udev,
  3576. -				   usb_sndbulkpipe(udev, 0x02),
  3577. -				   buf, FW_BULKOUT_SIZE + 2, &act_len, 1000);
  3578. -		if (ret) {
  3579. -			err("firmware download failed at packet %d with code %d", i, ret);
  3580. -			goto err;
  3581. -		}
  3582. -	}
  3583. -	ret = af9005_boot_packet(udev, FW_CONFIRM, &reply,
  3584. -				 buf, FW_BULKOUT_SIZE + 2);
  3585. -	if (ret)
  3586. -		goto err;
  3587. -	if (reply != (u8) (packets & 0xff)) {
  3588. -		err("after downloading firmware, FW_CONFIRM expected 0x%x, received 0x%x", packets & 0xff, reply);
  3589. -		ret = -EIO;
  3590. -		goto err;
  3591. -	}
  3592. -	ret = af9005_boot_packet(udev, FW_BOOT, &reply, buf,
  3593. -				 FW_BULKOUT_SIZE + 2);
  3594. -	if (ret)
  3595. -		goto err;
  3596. -	ret = af9005_boot_packet(udev, FW_CONFIG, &reply, buf,
  3597. -				 FW_BULKOUT_SIZE + 2);
  3598. -	if (ret)
  3599. -		goto err;
  3600. -	if (reply != 0x02) {
  3601. -		err("after downloading firmware, FW_CONFIG expected 0x02, received 0x%x", reply);
  3602. -		ret = -EIO;
  3603. -		goto err;
  3604. -	}
  3605. -
  3606. -err:
  3607. -	kfree(buf);
  3608. -	return ret;
  3609. -
  3610. -}
  3611. -
  3612. -int af9005_led_control(struct dvb_usb_device *d, int onoff)
  3613. -{
  3614. -	struct af9005_device_state *st = d->priv;
  3615. -	int temp, ret;
  3616. -
  3617. -	if (onoff && dvb_usb_af9005_led)
  3618. -		temp = 1;
  3619. -	else
  3620. -		temp = 0;
  3621. -	if (st->led_state != temp) {
  3622. -		ret =
  3623. -		    af9005_write_register_bits(d, xd_p_reg_top_locken1,
  3624. -					       reg_top_locken1_pos,
  3625. -					       reg_top_locken1_len, temp);
  3626. -		if (ret)
  3627. -			return ret;
  3628. -		ret =
  3629. -		    af9005_write_register_bits(d, xd_p_reg_top_lock1,
  3630. -					       reg_top_lock1_pos,
  3631. -					       reg_top_lock1_len, temp);
  3632. -		if (ret)
  3633. -			return ret;
  3634. -		st->led_state = temp;
  3635. -	}
  3636. -	return 0;
  3637. -}
  3638. -
  3639. -static int af9005_frontend_attach(struct dvb_usb_adapter *adap)
  3640. -{
  3641. -	u8 buf[8];
  3642. -	int i;
  3643. -
  3644. -	/* without these calls the first commands after downloading
  3645. -	   the firmware fail. I put these calls here to simulate
  3646. -	   what it is done in dvb-usb-init.c.
  3647. -	 */
  3648. -	struct usb_device *udev = adap->dev->udev;
  3649. -	usb_clear_halt(udev, usb_sndbulkpipe(udev, 2));
  3650. -	usb_clear_halt(udev, usb_rcvbulkpipe(udev, 1));
  3651. -	if (dvb_usb_af9005_dump_eeprom) {
  3652. -		printk("EEPROM DUMP\n");
  3653. -		for (i = 0; i < 255; i += 8) {
  3654. -			af9005_read_eeprom(adap->dev, i, buf, 8);
  3655. -			debug_dump(buf, 8, printk);
  3656. -		}
  3657. -	}
  3658. -	adap->fe_adap[0].fe = af9005_fe_attach(adap->dev);
  3659. -	return 0;
  3660. -}
  3661. -
  3662. -static int af9005_rc_query(struct dvb_usb_device *d, u32 * event, int *state)
  3663. -{
  3664. -	struct af9005_device_state *st = d->priv;
  3665. -	int ret, len;
  3666. -	u8 seq;
  3667. -
  3668. -	*state = REMOTE_NO_KEY_PRESSED;
  3669. -	if (rc_decode == NULL) {
  3670. -		/* it shouldn't never come here */
  3671. -		return 0;
  3672. -	}
  3673. -
  3674. -	mutex_lock(&d->data_mutex);
  3675. -
  3676. -	/* deb_info("rc_query\n"); */
  3677. -	st->data[0] = 3;		/* rest of packet length low */
  3678. -	st->data[1] = 0;		/* rest of packet lentgh high */
  3679. -	st->data[2] = 0x40;		/* read remote */
  3680. -	st->data[3] = 1;		/* rest of packet length */
  3681. -	st->data[4] = seq = st->sequence++;	/* sequence number */
  3682. -	ret = dvb_usb_generic_rw(d, st->data, 5, st->data, 256, 0);
  3683. -	if (ret) {
  3684. -		err("rc query failed");
  3685. -		goto ret;
  3686. -	}
  3687. -	if (st->data[2] != 0x41) {
  3688. -		err("rc query bad header.");
  3689. -		ret = -EIO;
  3690. -		goto ret;
  3691. -	} else if (st->data[4] != seq) {
  3692. -		err("rc query bad sequence.");
  3693. -		ret = -EIO;
  3694. -		goto ret;
  3695. -	}
  3696. -	len = st->data[5];
  3697. -	if (len > 246) {
  3698. -		err("rc query invalid length");
  3699. -		ret = -EIO;
  3700. -		goto ret;
  3701. -	}
  3702. -	if (len > 0) {
  3703. -		deb_rc("rc data (%d) ", len);
  3704. -		debug_dump((st->data + 6), len, deb_rc);
  3705. -		ret = rc_decode(d, &st->data[6], len, event, state);
  3706. -		if (ret) {
  3707. -			err("rc_decode failed");
  3708. -			goto ret;
  3709. -		} else {
  3710. -			deb_rc("rc_decode state %x event %x\n", *state, *event);
  3711. -			if (*state == REMOTE_KEY_REPEAT)
  3712. -				*event = d->last_event;
  3713. -		}
  3714. -	}
  3715. -
  3716. -ret:
  3717. -	mutex_unlock(&d->data_mutex);
  3718. -	return ret;
  3719. -}
  3720. -
  3721. -static int af9005_power_ctrl(struct dvb_usb_device *d, int onoff)
  3722. -{
  3723. -
  3724. -	return 0;
  3725. -}
  3726. -
  3727. -static int af9005_pid_filter_control(struct dvb_usb_adapter *adap, int onoff)
  3728. -{
  3729. -	int ret;
  3730. -	deb_info("pid filter control  onoff %d\n", onoff);
  3731. -	if (onoff) {
  3732. -		ret =
  3733. -		    af9005_write_ofdm_register(adap->dev, XD_MP2IF_DMX_CTRL, 1);
  3734. -		if (ret)
  3735. -			return ret;
  3736. -		ret =
  3737. -		    af9005_write_register_bits(adap->dev,
  3738. -					       XD_MP2IF_DMX_CTRL, 1, 1, 1);
  3739. -		if (ret)
  3740. -			return ret;
  3741. -		ret =
  3742. -		    af9005_write_ofdm_register(adap->dev, XD_MP2IF_DMX_CTRL, 1);
  3743. -	} else
  3744. -		ret =
  3745. -		    af9005_write_ofdm_register(adap->dev, XD_MP2IF_DMX_CTRL, 0);
  3746. -	if (ret)
  3747. -		return ret;
  3748. -	deb_info("pid filter control ok\n");
  3749. -	return 0;
  3750. -}
  3751. -
  3752. -static int af9005_pid_filter(struct dvb_usb_adapter *adap, int index,
  3753. -			     u16 pid, int onoff)
  3754. -{
  3755. -	u8 cmd = index & 0x1f;
  3756. -	int ret;
  3757. -	deb_info("set pid filter, index %d, pid %x, onoff %d\n", index,
  3758. -		 pid, onoff);
  3759. -	if (onoff) {
  3760. -		/* cannot use it as pid_filter_ctrl since it has to be done
  3761. -		   before setting the first pid */
  3762. -		if (adap->feedcount == 1) {
  3763. -			deb_info("first pid set, enable pid table\n");
  3764. -			ret = af9005_pid_filter_control(adap, onoff);
  3765. -			if (ret)
  3766. -				return ret;
  3767. -		}
  3768. -		ret =
  3769. -		    af9005_write_ofdm_register(adap->dev,
  3770. -					       XD_MP2IF_PID_DATA_L,
  3771. -					       (u8) (pid & 0xff));
  3772. -		if (ret)
  3773. -			return ret;
  3774. -		ret =
  3775. -		    af9005_write_ofdm_register(adap->dev,
  3776. -					       XD_MP2IF_PID_DATA_H,
  3777. -					       (u8) (pid >> 8));
  3778. -		if (ret)
  3779. -			return ret;
  3780. -		cmd |= 0x20 | 0x40;
  3781. -	} else {
  3782. -		if (adap->feedcount == 0) {
  3783. -			deb_info("last pid unset, disable pid table\n");
  3784. -			ret = af9005_pid_filter_control(adap, onoff);
  3785. -			if (ret)
  3786. -				return ret;
  3787. -		}
  3788. -	}
  3789. -	ret = af9005_write_ofdm_register(adap->dev, XD_MP2IF_PID_IDX, cmd);
  3790. -	if (ret)
  3791. -		return ret;
  3792. -	deb_info("set pid ok\n");
  3793. -	return 0;
  3794. -}
  3795. -
  3796. -static int af9005_identify_state(struct usb_device *udev,
  3797. -				 struct dvb_usb_device_properties *props,
  3798. -				 struct dvb_usb_device_description **desc,
  3799. -				 int *cold)
  3800. -{
  3801. -	int ret;
  3802. -	u8 reply, *buf;
  3803. -
  3804. -	buf = kmalloc(FW_BULKOUT_SIZE + 2, GFP_KERNEL);
  3805. -	if (!buf)
  3806. -		return -ENOMEM;
  3807. -
  3808. -	ret = af9005_boot_packet(udev, FW_CONFIG, &reply,
  3809. -				 buf, FW_BULKOUT_SIZE + 2);
  3810. -	if (ret)
  3811. -		goto err;
  3812. -	deb_info("result of FW_CONFIG in identify state %d\n", reply);
  3813. -	if (reply == 0x01)
  3814. -		*cold = 1;
  3815. -	else if (reply == 0x02)
  3816. -		*cold = 0;
  3817. -	else
  3818. -		ret = -EIO;
  3819. -	if (!ret)
  3820. -		deb_info("Identify state cold = %d\n", *cold);
  3821. -
  3822. -err:
  3823. -	kfree(buf);
  3824. -	return ret;
  3825. -}
  3826. -
  3827. -static struct dvb_usb_device_properties af9005_properties;
  3828. -
  3829. -static int af9005_usb_probe(struct usb_interface *intf,
  3830. -			    const struct usb_device_id *id)
  3831. -{
  3832. -	return dvb_usb_device_init(intf, &af9005_properties,
  3833. -				  THIS_MODULE, NULL, adapter_nr);
  3834. -}
  3835. -
  3836. -enum af9005_usb_table_entry {
  3837. -	AFATECH_AF9005,
  3838. -	TERRATEC_AF9005,
  3839. -	ANSONIC_AF9005,
  3840. -};
  3841. -
  3842. -static struct usb_device_id af9005_usb_table[] = {
  3843. -	[AFATECH_AF9005] = {USB_DEVICE(USB_VID_AFATECH,
  3844. -				USB_PID_AFATECH_AF9005)},
  3845. -	[TERRATEC_AF9005] = {USB_DEVICE(USB_VID_TERRATEC,
  3846. -				USB_PID_TERRATEC_CINERGY_T_USB_XE)},
  3847. -	[ANSONIC_AF9005] = {USB_DEVICE(USB_VID_ANSONIC,
  3848. -				USB_PID_ANSONIC_DVBT_USB)},
  3849. -	{ }
  3850. -};
  3851. -
  3852. -MODULE_DEVICE_TABLE(usb, af9005_usb_table);
  3853. -
  3854. -static struct dvb_usb_device_properties af9005_properties = {
  3855. -	.caps = DVB_USB_IS_AN_I2C_ADAPTER,
  3856. -
  3857. -	.usb_ctrl = DEVICE_SPECIFIC,
  3858. -	.firmware = "af9005.fw",
  3859. -	.download_firmware = af9005_download_firmware,
  3860. -	.no_reconnect = 1,
  3861. -
  3862. -	.size_of_priv = sizeof(struct af9005_device_state),
  3863. -
  3864. -	.num_adapters = 1,
  3865. -	.adapter = {
  3866. -		    {
  3867. -		    .num_frontends = 1,
  3868. -		    .fe = {{
  3869. -		     .caps =
  3870. -		     DVB_USB_ADAP_HAS_PID_FILTER |
  3871. -		     DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
  3872. -		     .pid_filter_count = 32,
  3873. -		     .pid_filter = af9005_pid_filter,
  3874. -		     /* .pid_filter_ctrl = af9005_pid_filter_control, */
  3875. -		     .frontend_attach = af9005_frontend_attach,
  3876. -		     /* .tuner_attach     = af9005_tuner_attach, */
  3877. -		     /* parameter for the MPEG2-data transfer */
  3878. -		     .stream = {
  3879. -				.type = USB_BULK,
  3880. -				.count = 10,
  3881. -				.endpoint = 0x04,
  3882. -				.u = {
  3883. -				      .bulk = {
  3884. -					       .buffersize = 4096,	/* actual size seen is 3948 */
  3885. -					       }
  3886. -				      }
  3887. -				},
  3888. -		     }},
  3889. -		     }
  3890. -		    },
  3891. -	.power_ctrl = af9005_power_ctrl,
  3892. -	.identify_state = af9005_identify_state,
  3893. -
  3894. -	.i2c_algo = &af9005_i2c_algo,
  3895. -
  3896. -	.rc.legacy = {
  3897. -		.rc_interval = 200,
  3898. -		.rc_map_table = NULL,
  3899. -		.rc_map_size = 0,
  3900. -		.rc_query = af9005_rc_query,
  3901. -	},
  3902. -
  3903. -	.generic_bulk_ctrl_endpoint          = 2,
  3904. -	.generic_bulk_ctrl_endpoint_response = 1,
  3905. -
  3906. -	.num_device_descs = 3,
  3907. -	.devices = {
  3908. -		    {.name = "Afatech DVB-T USB1.1 stick",
  3909. -		     .cold_ids = {&af9005_usb_table[AFATECH_AF9005], NULL},
  3910. -		     .warm_ids = {NULL},
  3911. -		     },
  3912. -		    {.name = "TerraTec Cinergy T USB XE",
  3913. -		     .cold_ids = {&af9005_usb_table[TERRATEC_AF9005], NULL},
  3914. -		     .warm_ids = {NULL},
  3915. -		     },
  3916. -		    {.name = "Ansonic DVB-T USB1.1 stick",
  3917. -		     .cold_ids = {&af9005_usb_table[ANSONIC_AF9005], NULL},
  3918. -		     .warm_ids = {NULL},
  3919. -		     },
  3920. -		    {NULL},
  3921. -		    }
  3922. -};
  3923. -
  3924. -/* usb specific object needed to register this driver with the usb subsystem */
  3925. -static struct usb_driver af9005_usb_driver = {
  3926. -	.name = "dvb_usb_af9005",
  3927. -	.probe = af9005_usb_probe,
  3928. -	.disconnect = dvb_usb_device_exit,
  3929. -	.id_table = af9005_usb_table,
  3930. -};
  3931. -
  3932. -/* module stuff */
  3933. -static int __init af9005_usb_module_init(void)
  3934. -{
  3935. -	int result;
  3936. -	if ((result = usb_register(&af9005_usb_driver))) {
  3937. -		err("usb_register failed. (%d)", result);
  3938. -		return result;
  3939. -	}
  3940. -#if IS_MODULE(CONFIG_DVB_USB_AF9005) || defined(CONFIG_DVB_USB_AF9005_REMOTE)
  3941. -	/* FIXME: convert to todays kernel IR infrastructure */
  3942. -	rc_decode = symbol_request(af9005_rc_decode);
  3943. -	rc_keys = symbol_request(rc_map_af9005_table);
  3944. -	rc_keys_size = symbol_request(rc_map_af9005_table_size);
  3945. -#endif
  3946. -	if (rc_decode == NULL || rc_keys == NULL || rc_keys_size == NULL) {
  3947. -		err("af9005_rc_decode function not found, disabling remote");
  3948. -		af9005_properties.rc.legacy.rc_query = NULL;
  3949. -	} else {
  3950. -		af9005_properties.rc.legacy.rc_map_table = rc_keys;
  3951. -		af9005_properties.rc.legacy.rc_map_size = *rc_keys_size;
  3952. -	}
  3953. -
  3954. -	return 0;
  3955. -}
  3956. -
  3957. -static void __exit af9005_usb_module_exit(void)
  3958. -{
  3959. -	/* release rc decode symbols */
  3960. -	if (rc_decode != NULL)
  3961. -		symbol_put(af9005_rc_decode);
  3962. -	if (rc_keys != NULL)
  3963. -		symbol_put(rc_map_af9005_table);
  3964. -	if (rc_keys_size != NULL)
  3965. -		symbol_put(rc_map_af9005_table_size);
  3966. -	/* deregister this driver from the USB subsystem */
  3967. -	usb_deregister(&af9005_usb_driver);
  3968. -}
  3969. -
  3970. -module_init(af9005_usb_module_init);
  3971. -module_exit(af9005_usb_module_exit);
  3972. -
  3973. -MODULE_AUTHOR("Luca Olivetti <luca@ventoso.org>");
  3974. -MODULE_DESCRIPTION("Driver for Afatech 9005 DVB-T USB1.1 stick");
  3975. -MODULE_VERSION("1.0");
  3976. -MODULE_LICENSE("GPL");
  3977. diff -ruN ../linux-4.14.336/drivers/media/usb/dvb-usb/af9005.h ./drivers/media/usb/dvb-usb/af9005.h
  3978. --- linux-4.14.336/../linux-4.14.336/drivers/media/usb/dvb-usb/af9005.h	2024-01-10 14:45:41.000000000 +0100
  3979. +++ linux-4.14.336/./drivers/media/usb/dvb-usb/af9005.h	1970-01-01 01:00:00.000000000 +0100
  3980. @@ -1,3492 +0,0 @@
  3981. -/* Common header-file of the Linux driver for the Afatech 9005
  3982. - * USB1.1 DVB-T receiver.
  3983. - *
  3984. - * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
  3985. - *
  3986. - * Thanks to Afatech who kindly provided information.
  3987. - *
  3988. - * This program is free software; you can redistribute it and/or modify
  3989. - * it under the terms of the GNU General Public License as published by
  3990. - * the Free Software Foundation; either version 2 of the License, or
  3991. - * (at your option) any later version.
  3992. - *
  3993. - * This program is distributed in the hope that it will be useful,
  3994. - * but WITHOUT ANY WARRANTY; without even the implied warranty of
  3995. - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  3996. - * GNU General Public License for more details.
  3997. - *
  3998. - * see Documentation/dvb/README.dvb-usb for more information
  3999. - */
  4000. -#ifndef _DVB_USB_AF9005_H_
  4001. -#define _DVB_USB_AF9005_H_
  4002. -
  4003. -#define DVB_USB_LOG_PREFIX "af9005"
  4004. -#include "dvb-usb.h"
  4005. -
  4006. -extern int dvb_usb_af9005_debug;
  4007. -#define deb_info(args...) dprintk(dvb_usb_af9005_debug,0x01,args)
  4008. -#define deb_xfer(args...) dprintk(dvb_usb_af9005_debug,0x02,args)
  4009. -#define deb_rc(args...)   dprintk(dvb_usb_af9005_debug,0x04,args)
  4010. -#define deb_reg(args...)  dprintk(dvb_usb_af9005_debug,0x08,args)
  4011. -#define deb_i2c(args...)  dprintk(dvb_usb_af9005_debug,0x10,args)
  4012. -#define deb_fw(args...)   dprintk(dvb_usb_af9005_debug,0x20,args)
  4013. -
  4014. -extern bool dvb_usb_af9005_led;
  4015. -
  4016. -/* firmware */
  4017. -#define FW_BULKOUT_SIZE 250
  4018. -enum {
  4019. -	FW_CONFIG,
  4020. -	FW_CONFIRM,
  4021. -	FW_BOOT
  4022. -};
  4023. -
  4024. -/* af9005 commands */
  4025. -#define AF9005_OFDM_REG  0
  4026. -#define AF9005_TUNER_REG 1
  4027. -
  4028. -#define AF9005_REGISTER_RW     0x20
  4029. -#define AF9005_REGISTER_RW_ACK 0x21
  4030. -
  4031. -#define AF9005_CMD_OFDM_REG 0x00
  4032. -#define AF9005_CMD_TUNER    0x80
  4033. -#define AF9005_CMD_BURST    0x02
  4034. -#define AF9005_CMD_AUTOINC  0x04
  4035. -#define AF9005_CMD_READ     0x00
  4036. -#define AF9005_CMD_WRITE    0x01
  4037. -
  4038. -/* af9005 registers */
  4039. -#define APO_REG_RESET					0xAEFF
  4040. -
  4041. -#define APO_REG_I2C_RW_CAN_TUNER            0xF000
  4042. -#define APO_REG_I2C_RW_SILICON_TUNER        0xF001
  4043. -#define APO_REG_GPIO_RW_SILICON_TUNER       0xFFFE	/*  also for OFSM */
  4044. -#define APO_REG_TRIGGER_OFSM                0xFFFF	/*  also for OFSM */
  4045. -
  4046. -/***********************************************************************
  4047. - *  Apollo Registers from VLSI					       *
  4048. - ***********************************************************************/
  4049. -#define xd_p_reg_aagc_inverted_agc	0xA000
  4050. -#define	reg_aagc_inverted_agc_pos 0
  4051. -#define	reg_aagc_inverted_agc_len 1
  4052. -#define	reg_aagc_inverted_agc_lsb 0
  4053. -#define xd_p_reg_aagc_sign_only	0xA000
  4054. -#define	reg_aagc_sign_only_pos 1
  4055. -#define	reg_aagc_sign_only_len 1
  4056. -#define	reg_aagc_sign_only_lsb 0
  4057. -#define xd_p_reg_aagc_slow_adc_en	0xA000
  4058. -#define	reg_aagc_slow_adc_en_pos 2
  4059. -#define	reg_aagc_slow_adc_en_len 1
  4060. -#define	reg_aagc_slow_adc_en_lsb 0
  4061. -#define xd_p_reg_aagc_slow_adc_scale	0xA000
  4062. -#define	reg_aagc_slow_adc_scale_pos 3
  4063. -#define	reg_aagc_slow_adc_scale_len 5
  4064. -#define	reg_aagc_slow_adc_scale_lsb 0
  4065. -#define xd_p_reg_aagc_check_slow_adc_lock	0xA001
  4066. -#define	reg_aagc_check_slow_adc_lock_pos 0
  4067. -#define	reg_aagc_check_slow_adc_lock_len 1
  4068. -#define	reg_aagc_check_slow_adc_lock_lsb 0
  4069. -#define xd_p_reg_aagc_init_control	0xA001
  4070. -#define	reg_aagc_init_control_pos 1
  4071. -#define	reg_aagc_init_control_len 1
  4072. -#define	reg_aagc_init_control_lsb 0
  4073. -#define xd_p_reg_aagc_total_gain_sel	0xA001
  4074. -#define	reg_aagc_total_gain_sel_pos 2
  4075. -#define	reg_aagc_total_gain_sel_len 2
  4076. -#define	reg_aagc_total_gain_sel_lsb 0
  4077. -#define xd_p_reg_aagc_out_inv	0xA001
  4078. -#define	reg_aagc_out_inv_pos 5
  4079. -#define	reg_aagc_out_inv_len 1
  4080. -#define	reg_aagc_out_inv_lsb 0
  4081. -#define xd_p_reg_aagc_int_en	0xA001
  4082. -#define	reg_aagc_int_en_pos 6
  4083. -#define	reg_aagc_int_en_len 1
  4084. -#define	reg_aagc_int_en_lsb 0
  4085. -#define xd_p_reg_aagc_lock_change_flag	0xA001
  4086. -#define	reg_aagc_lock_change_flag_pos 7
  4087. -#define	reg_aagc_lock_change_flag_len 1
  4088. -#define	reg_aagc_lock_change_flag_lsb 0
  4089. -#define xd_p_reg_aagc_rf_loop_bw_scale_acquire	0xA002
  4090. -#define	reg_aagc_rf_loop_bw_scale_acquire_pos 0
  4091. -#define	reg_aagc_rf_loop_bw_scale_acquire_len 5
  4092. -#define	reg_aagc_rf_loop_bw_scale_acquire_lsb 0
  4093. -#define xd_p_reg_aagc_rf_loop_bw_scale_track	0xA003
  4094. -#define	reg_aagc_rf_loop_bw_scale_track_pos 0
  4095. -#define	reg_aagc_rf_loop_bw_scale_track_len 5
  4096. -#define	reg_aagc_rf_loop_bw_scale_track_lsb 0
  4097. -#define xd_p_reg_aagc_if_loop_bw_scale_acquire	0xA004
  4098. -#define	reg_aagc_if_loop_bw_scale_acquire_pos 0
  4099. -#define	reg_aagc_if_loop_bw_scale_acquire_len 5
  4100. -#define	reg_aagc_if_loop_bw_scale_acquire_lsb 0
  4101. -#define xd_p_reg_aagc_if_loop_bw_scale_track	0xA005
  4102. -#define	reg_aagc_if_loop_bw_scale_track_pos 0
  4103. -#define	reg_aagc_if_loop_bw_scale_track_len 5
  4104. -#define	reg_aagc_if_loop_bw_scale_track_lsb 0
  4105. -#define xd_p_reg_aagc_max_rf_agc_7_0	0xA006
  4106. -#define	reg_aagc_max_rf_agc_7_0_pos 0
  4107. -#define	reg_aagc_max_rf_agc_7_0_len 8
  4108. -#define	reg_aagc_max_rf_agc_7_0_lsb 0
  4109. -#define xd_p_reg_aagc_max_rf_agc_9_8	0xA007
  4110. -#define	reg_aagc_max_rf_agc_9_8_pos 0
  4111. -#define	reg_aagc_max_rf_agc_9_8_len 2
  4112. -#define	reg_aagc_max_rf_agc_9_8_lsb 8
  4113. -#define xd_p_reg_aagc_min_rf_agc_7_0	0xA008
  4114. -#define	reg_aagc_min_rf_agc_7_0_pos 0
  4115. -#define	reg_aagc_min_rf_agc_7_0_len 8
  4116. -#define	reg_aagc_min_rf_agc_7_0_lsb 0
  4117. -#define xd_p_reg_aagc_min_rf_agc_9_8	0xA009
  4118. -#define	reg_aagc_min_rf_agc_9_8_pos 0
  4119. -#define	reg_aagc_min_rf_agc_9_8_len 2
  4120. -#define	reg_aagc_min_rf_agc_9_8_lsb 8
  4121. -#define xd_p_reg_aagc_max_if_agc_7_0	0xA00A
  4122. -#define	reg_aagc_max_if_agc_7_0_pos 0
  4123. -#define	reg_aagc_max_if_agc_7_0_len 8
  4124. -#define	reg_aagc_max_if_agc_7_0_lsb 0
  4125. -#define xd_p_reg_aagc_max_if_agc_9_8	0xA00B
  4126. -#define	reg_aagc_max_if_agc_9_8_pos 0
  4127. -#define	reg_aagc_max_if_agc_9_8_len 2
  4128. -#define	reg_aagc_max_if_agc_9_8_lsb 8
  4129. -#define xd_p_reg_aagc_min_if_agc_7_0	0xA00C
  4130. -#define	reg_aagc_min_if_agc_7_0_pos 0
  4131. -#define	reg_aagc_min_if_agc_7_0_len 8
  4132. -#define	reg_aagc_min_if_agc_7_0_lsb 0
  4133. -#define xd_p_reg_aagc_min_if_agc_9_8	0xA00D
  4134. -#define	reg_aagc_min_if_agc_9_8_pos 0
  4135. -#define	reg_aagc_min_if_agc_9_8_len 2
  4136. -#define	reg_aagc_min_if_agc_9_8_lsb 8
  4137. -#define xd_p_reg_aagc_lock_sample_scale	0xA00E
  4138. -#define	reg_aagc_lock_sample_scale_pos 0
  4139. -#define	reg_aagc_lock_sample_scale_len 5
  4140. -#define	reg_aagc_lock_sample_scale_lsb 0
  4141. -#define xd_p_reg_aagc_rf_agc_lock_scale_acquire	0xA00F
  4142. -#define	reg_aagc_rf_agc_lock_scale_acquire_pos 0
  4143. -#define	reg_aagc_rf_agc_lock_scale_acquire_len 3
  4144. -#define	reg_aagc_rf_agc_lock_scale_acquire_lsb 0
  4145. -#define xd_p_reg_aagc_rf_agc_lock_scale_track	0xA00F
  4146. -#define	reg_aagc_rf_agc_lock_scale_track_pos 3
  4147. -#define	reg_aagc_rf_agc_lock_scale_track_len 3
  4148. -#define	reg_aagc_rf_agc_lock_scale_track_lsb 0
  4149. -#define xd_p_reg_aagc_if_agc_lock_scale_acquire	0xA010
  4150. -#define	reg_aagc_if_agc_lock_scale_acquire_pos 0
  4151. -#define	reg_aagc_if_agc_lock_scale_acquire_len 3
  4152. -#define	reg_aagc_if_agc_lock_scale_acquire_lsb 0
  4153. -#define xd_p_reg_aagc_if_agc_lock_scale_track	0xA010
  4154. -#define	reg_aagc_if_agc_lock_scale_track_pos 3
  4155. -#define	reg_aagc_if_agc_lock_scale_track_len 3
  4156. -#define	reg_aagc_if_agc_lock_scale_track_lsb 0
  4157. -#define xd_p_reg_aagc_rf_top_numerator_7_0	0xA011
  4158. -#define	reg_aagc_rf_top_numerator_7_0_pos 0
  4159. -#define	reg_aagc_rf_top_numerator_7_0_len 8
  4160. -#define	reg_aagc_rf_top_numerator_7_0_lsb 0
  4161. -#define xd_p_reg_aagc_rf_top_numerator_9_8	0xA012
  4162. -#define	reg_aagc_rf_top_numerator_9_8_pos 0
  4163. -#define	reg_aagc_rf_top_numerator_9_8_len 2
  4164. -#define	reg_aagc_rf_top_numerator_9_8_lsb 8
  4165. -#define xd_p_reg_aagc_if_top_numerator_7_0	0xA013
  4166. -#define	reg_aagc_if_top_numerator_7_0_pos 0
  4167. -#define	reg_aagc_if_top_numerator_7_0_len 8
  4168. -#define	reg_aagc_if_top_numerator_7_0_lsb 0
  4169. -#define xd_p_reg_aagc_if_top_numerator_9_8	0xA014
  4170. -#define	reg_aagc_if_top_numerator_9_8_pos 0
  4171. -#define	reg_aagc_if_top_numerator_9_8_len 2
  4172. -#define	reg_aagc_if_top_numerator_9_8_lsb 8
  4173. -#define xd_p_reg_aagc_adc_out_desired_7_0	0xA015
  4174. -#define	reg_aagc_adc_out_desired_7_0_pos 0
  4175. -#define	reg_aagc_adc_out_desired_7_0_len 8
  4176. -#define	reg_aagc_adc_out_desired_7_0_lsb 0
  4177. -#define xd_p_reg_aagc_adc_out_desired_8	0xA016
  4178. -#define	reg_aagc_adc_out_desired_8_pos 0
  4179. -#define	reg_aagc_adc_out_desired_8_len 1
  4180. -#define	reg_aagc_adc_out_desired_8_lsb 0
  4181. -#define xd_p_reg_aagc_fixed_gain	0xA016
  4182. -#define	reg_aagc_fixed_gain_pos 3
  4183. -#define	reg_aagc_fixed_gain_len 1
  4184. -#define	reg_aagc_fixed_gain_lsb 0
  4185. -#define xd_p_reg_aagc_lock_count_th	0xA016
  4186. -#define	reg_aagc_lock_count_th_pos 4
  4187. -#define	reg_aagc_lock_count_th_len 4
  4188. -#define	reg_aagc_lock_count_th_lsb 0
  4189. -#define xd_p_reg_aagc_fixed_rf_agc_control_7_0	0xA017
  4190. -#define	reg_aagc_fixed_rf_agc_control_7_0_pos 0
  4191. -#define	reg_aagc_fixed_rf_agc_control_7_0_len 8
  4192. -#define	reg_aagc_fixed_rf_agc_control_7_0_lsb 0
  4193. -#define xd_p_reg_aagc_fixed_rf_agc_control_15_8	0xA018
  4194. -#define	reg_aagc_fixed_rf_agc_control_15_8_pos 0
  4195. -#define	reg_aagc_fixed_rf_agc_control_15_8_len 8
  4196. -#define	reg_aagc_fixed_rf_agc_control_15_8_lsb 8
  4197. -#define xd_p_reg_aagc_fixed_rf_agc_control_23_16	0xA019
  4198. -#define	reg_aagc_fixed_rf_agc_control_23_16_pos 0
  4199. -#define	reg_aagc_fixed_rf_agc_control_23_16_len 8
  4200. -#define	reg_aagc_fixed_rf_agc_control_23_16_lsb 16
  4201. -#define xd_p_reg_aagc_fixed_rf_agc_control_30_24	0xA01A
  4202. -#define	reg_aagc_fixed_rf_agc_control_30_24_pos 0
  4203. -#define	reg_aagc_fixed_rf_agc_control_30_24_len 7
  4204. -#define	reg_aagc_fixed_rf_agc_control_30_24_lsb 24
  4205. -#define xd_p_reg_aagc_fixed_if_agc_control_7_0	0xA01B
  4206. -#define	reg_aagc_fixed_if_agc_control_7_0_pos 0
  4207. -#define	reg_aagc_fixed_if_agc_control_7_0_len 8
  4208. -#define	reg_aagc_fixed_if_agc_control_7_0_lsb 0
  4209. -#define xd_p_reg_aagc_fixed_if_agc_control_15_8	0xA01C
  4210. -#define	reg_aagc_fixed_if_agc_control_15_8_pos 0
  4211. -#define	reg_aagc_fixed_if_agc_control_15_8_len 8
  4212. -#define	reg_aagc_fixed_if_agc_control_15_8_lsb 8
  4213. -#define xd_p_reg_aagc_fixed_if_agc_control_23_16	0xA01D
  4214. -#define	reg_aagc_fixed_if_agc_control_23_16_pos 0
  4215. -#define	reg_aagc_fixed_if_agc_control_23_16_len 8
  4216. -#define	reg_aagc_fixed_if_agc_control_23_16_lsb 16
  4217. -#define xd_p_reg_aagc_fixed_if_agc_control_30_24	0xA01E
  4218. -#define	reg_aagc_fixed_if_agc_control_30_24_pos 0
  4219. -#define	reg_aagc_fixed_if_agc_control_30_24_len 7
  4220. -#define	reg_aagc_fixed_if_agc_control_30_24_lsb 24
  4221. -#define xd_p_reg_aagc_rf_agc_unlock_numerator	0xA01F
  4222. -#define	reg_aagc_rf_agc_unlock_numerator_pos 0
  4223. -#define	reg_aagc_rf_agc_unlock_numerator_len 6
  4224. -#define	reg_aagc_rf_agc_unlock_numerator_lsb 0
  4225. -#define xd_p_reg_aagc_if_agc_unlock_numerator	0xA020
  4226. -#define	reg_aagc_if_agc_unlock_numerator_pos 0
  4227. -#define	reg_aagc_if_agc_unlock_numerator_len 6
  4228. -#define	reg_aagc_if_agc_unlock_numerator_lsb 0
  4229. -#define xd_p_reg_unplug_th	0xA021
  4230. -#define	reg_unplug_th_pos 0
  4231. -#define	reg_unplug_th_len 8
  4232. -#define	reg_aagc_rf_x0_lsb 0
  4233. -#define xd_p_reg_weak_signal_rfagc_thr 0xA022
  4234. -#define	reg_weak_signal_rfagc_thr_pos 0
  4235. -#define	reg_weak_signal_rfagc_thr_len 8
  4236. -#define	reg_weak_signal_rfagc_thr_lsb 0
  4237. -#define xd_p_reg_unplug_rf_gain_th 0xA023
  4238. -#define	reg_unplug_rf_gain_th_pos 0
  4239. -#define	reg_unplug_rf_gain_th_len 8
  4240. -#define	reg_unplug_rf_gain_th_lsb 0
  4241. -#define xd_p_reg_unplug_dtop_rf_gain_th 0xA024
  4242. -#define	reg_unplug_dtop_rf_gain_th_pos 0
  4243. -#define	reg_unplug_dtop_rf_gain_th_len 8
  4244. -#define	reg_unplug_dtop_rf_gain_th_lsb 0
  4245. -#define xd_p_reg_unplug_dtop_if_gain_th 0xA025
  4246. -#define	reg_unplug_dtop_if_gain_th_pos 0
  4247. -#define	reg_unplug_dtop_if_gain_th_len 8
  4248. -#define	reg_unplug_dtop_if_gain_th_lsb 0
  4249. -#define xd_p_reg_top_recover_at_unplug_en 0xA026
  4250. -#define	reg_top_recover_at_unplug_en_pos 0
  4251. -#define	reg_top_recover_at_unplug_en_len 1
  4252. -#define	reg_top_recover_at_unplug_en_lsb 0
  4253. -#define xd_p_reg_aagc_rf_x6	0xA027
  4254. -#define	reg_aagc_rf_x6_pos 0
  4255. -#define	reg_aagc_rf_x6_len 8
  4256. -#define	reg_aagc_rf_x6_lsb 0
  4257. -#define xd_p_reg_aagc_rf_x7	0xA028
  4258. -#define	reg_aagc_rf_x7_pos 0
  4259. -#define	reg_aagc_rf_x7_len 8
  4260. -#define	reg_aagc_rf_x7_lsb 0
  4261. -#define xd_p_reg_aagc_rf_x8	0xA029
  4262. -#define	reg_aagc_rf_x8_pos 0
  4263. -#define	reg_aagc_rf_x8_len 8
  4264. -#define	reg_aagc_rf_x8_lsb 0
  4265. -#define xd_p_reg_aagc_rf_x9	0xA02A
  4266. -#define	reg_aagc_rf_x9_pos 0
  4267. -#define	reg_aagc_rf_x9_len 8
  4268. -#define	reg_aagc_rf_x9_lsb 0
  4269. -#define xd_p_reg_aagc_rf_x10	0xA02B
  4270. -#define	reg_aagc_rf_x10_pos 0
  4271. -#define	reg_aagc_rf_x10_len 8
  4272. -#define	reg_aagc_rf_x10_lsb 0
  4273. -#define xd_p_reg_aagc_rf_x11	0xA02C
  4274. -#define	reg_aagc_rf_x11_pos 0
  4275. -#define	reg_aagc_rf_x11_len 8
  4276. -#define	reg_aagc_rf_x11_lsb 0
  4277. -#define xd_p_reg_aagc_rf_x12	0xA02D
  4278. -#define	reg_aagc_rf_x12_pos 0
  4279. -#define	reg_aagc_rf_x12_len 8
  4280. -#define	reg_aagc_rf_x12_lsb 0
  4281. -#define xd_p_reg_aagc_rf_x13	0xA02E
  4282. -#define	reg_aagc_rf_x13_pos 0
  4283. -#define	reg_aagc_rf_x13_len 8
  4284. -#define	reg_aagc_rf_x13_lsb 0
  4285. -#define xd_p_reg_aagc_if_x0	0xA02F
  4286. -#define	reg_aagc_if_x0_pos 0
  4287. -#define	reg_aagc_if_x0_len 8
  4288. -#define	reg_aagc_if_x0_lsb 0
  4289. -#define xd_p_reg_aagc_if_x1	0xA030
  4290. -#define	reg_aagc_if_x1_pos 0
  4291. -#define	reg_aagc_if_x1_len 8
  4292. -#define	reg_aagc_if_x1_lsb 0
  4293. -#define xd_p_reg_aagc_if_x2	0xA031
  4294. -#define	reg_aagc_if_x2_pos 0
  4295. -#define	reg_aagc_if_x2_len 8
  4296. -#define	reg_aagc_if_x2_lsb 0
  4297. -#define xd_p_reg_aagc_if_x3	0xA032
  4298. -#define	reg_aagc_if_x3_pos 0
  4299. -#define	reg_aagc_if_x3_len 8
  4300. -#define	reg_aagc_if_x3_lsb 0
  4301. -#define xd_p_reg_aagc_if_x4	0xA033
  4302. -#define	reg_aagc_if_x4_pos 0
  4303. -#define	reg_aagc_if_x4_len 8
  4304. -#define	reg_aagc_if_x4_lsb 0
  4305. -#define xd_p_reg_aagc_if_x5	0xA034
  4306. -#define	reg_aagc_if_x5_pos 0
  4307. -#define	reg_aagc_if_x5_len 8
  4308. -#define	reg_aagc_if_x5_lsb 0
  4309. -#define xd_p_reg_aagc_if_x6	0xA035
  4310. -#define	reg_aagc_if_x6_pos 0
  4311. -#define	reg_aagc_if_x6_len 8
  4312. -#define	reg_aagc_if_x6_lsb 0
  4313. -#define xd_p_reg_aagc_if_x7	0xA036
  4314. -#define	reg_aagc_if_x7_pos 0
  4315. -#define	reg_aagc_if_x7_len 8
  4316. -#define	reg_aagc_if_x7_lsb 0
  4317. -#define xd_p_reg_aagc_if_x8	0xA037
  4318. -#define	reg_aagc_if_x8_pos 0
  4319. -#define	reg_aagc_if_x8_len 8
  4320. -#define	reg_aagc_if_x8_lsb 0
  4321. -#define xd_p_reg_aagc_if_x9	0xA038
  4322. -#define	reg_aagc_if_x9_pos 0
  4323. -#define	reg_aagc_if_x9_len 8
  4324. -#define	reg_aagc_if_x9_lsb 0
  4325. -#define xd_p_reg_aagc_if_x10	0xA039
  4326. -#define	reg_aagc_if_x10_pos 0
  4327. -#define	reg_aagc_if_x10_len 8
  4328. -#define	reg_aagc_if_x10_lsb 0
  4329. -#define xd_p_reg_aagc_if_x11	0xA03A
  4330. -#define	reg_aagc_if_x11_pos 0
  4331. -#define	reg_aagc_if_x11_len 8
  4332. -#define	reg_aagc_if_x11_lsb 0
  4333. -#define xd_p_reg_aagc_if_x12	0xA03B
  4334. -#define	reg_aagc_if_x12_pos 0
  4335. -#define	reg_aagc_if_x12_len 8
  4336. -#define	reg_aagc_if_x12_lsb 0
  4337. -#define xd_p_reg_aagc_if_x13	0xA03C
  4338. -#define	reg_aagc_if_x13_pos 0
  4339. -#define	reg_aagc_if_x13_len 8
  4340. -#define	reg_aagc_if_x13_lsb 0
  4341. -#define xd_p_reg_aagc_min_rf_ctl_8bit_for_dca	0xA03D
  4342. -#define	reg_aagc_min_rf_ctl_8bit_for_dca_pos 0
  4343. -#define	reg_aagc_min_rf_ctl_8bit_for_dca_len 8
  4344. -#define	reg_aagc_min_rf_ctl_8bit_for_dca_lsb 0
  4345. -#define xd_p_reg_aagc_min_if_ctl_8bit_for_dca	0xA03E
  4346. -#define	reg_aagc_min_if_ctl_8bit_for_dca_pos 0
  4347. -#define	reg_aagc_min_if_ctl_8bit_for_dca_len 8
  4348. -#define	reg_aagc_min_if_ctl_8bit_for_dca_lsb 0
  4349. -#define xd_r_reg_aagc_total_gain_7_0	0xA070
  4350. -#define	reg_aagc_total_gain_7_0_pos 0
  4351. -#define	reg_aagc_total_gain_7_0_len 8
  4352. -#define	reg_aagc_total_gain_7_0_lsb 0
  4353. -#define xd_r_reg_aagc_total_gain_15_8	0xA071
  4354. -#define	reg_aagc_total_gain_15_8_pos 0
  4355. -#define	reg_aagc_total_gain_15_8_len 8
  4356. -#define	reg_aagc_total_gain_15_8_lsb 8
  4357. -#define xd_p_reg_aagc_in_sat_cnt_7_0	0xA074
  4358. -#define	reg_aagc_in_sat_cnt_7_0_pos 0
  4359. -#define	reg_aagc_in_sat_cnt_7_0_len 8
  4360. -#define	reg_aagc_in_sat_cnt_7_0_lsb 0
  4361. -#define xd_p_reg_aagc_in_sat_cnt_15_8	0xA075
  4362. -#define	reg_aagc_in_sat_cnt_15_8_pos 0
  4363. -#define	reg_aagc_in_sat_cnt_15_8_len 8
  4364. -#define	reg_aagc_in_sat_cnt_15_8_lsb 8
  4365. -#define xd_p_reg_aagc_in_sat_cnt_23_16	0xA076
  4366. -#define	reg_aagc_in_sat_cnt_23_16_pos 0
  4367. -#define	reg_aagc_in_sat_cnt_23_16_len 8
  4368. -#define	reg_aagc_in_sat_cnt_23_16_lsb 16
  4369. -#define xd_p_reg_aagc_in_sat_cnt_31_24	0xA077
  4370. -#define	reg_aagc_in_sat_cnt_31_24_pos 0
  4371. -#define	reg_aagc_in_sat_cnt_31_24_len 8
  4372. -#define	reg_aagc_in_sat_cnt_31_24_lsb 24
  4373. -#define xd_r_reg_aagc_digital_rf_volt_7_0	0xA078
  4374. -#define	reg_aagc_digital_rf_volt_7_0_pos 0
  4375. -#define	reg_aagc_digital_rf_volt_7_0_len 8
  4376. -#define	reg_aagc_digital_rf_volt_7_0_lsb 0
  4377. -#define xd_r_reg_aagc_digital_rf_volt_9_8	0xA079
  4378. -#define	reg_aagc_digital_rf_volt_9_8_pos 0
  4379. -#define	reg_aagc_digital_rf_volt_9_8_len 2
  4380. -#define	reg_aagc_digital_rf_volt_9_8_lsb 8
  4381. -#define xd_r_reg_aagc_digital_if_volt_7_0	0xA07A
  4382. -#define	reg_aagc_digital_if_volt_7_0_pos 0
  4383. -#define	reg_aagc_digital_if_volt_7_0_len 8
  4384. -#define	reg_aagc_digital_if_volt_7_0_lsb 0
  4385. -#define xd_r_reg_aagc_digital_if_volt_9_8	0xA07B
  4386. -#define	reg_aagc_digital_if_volt_9_8_pos 0
  4387. -#define	reg_aagc_digital_if_volt_9_8_len 2
  4388. -#define	reg_aagc_digital_if_volt_9_8_lsb 8
  4389. -#define xd_r_reg_aagc_rf_gain	0xA07C
  4390. -#define	reg_aagc_rf_gain_pos 0
  4391. -#define	reg_aagc_rf_gain_len 8
  4392. -#define	reg_aagc_rf_gain_lsb 0
  4393. -#define xd_r_reg_aagc_if_gain	0xA07D
  4394. -#define	reg_aagc_if_gain_pos 0
  4395. -#define	reg_aagc_if_gain_len 8
  4396. -#define	reg_aagc_if_gain_lsb 0
  4397. -#define xd_p_tinr_imp_indicator	0xA080
  4398. -#define	tinr_imp_indicator_pos 0
  4399. -#define	tinr_imp_indicator_len 2
  4400. -#define	tinr_imp_indicator_lsb 0
  4401. -#define xd_p_reg_tinr_fifo_size	0xA080
  4402. -#define	reg_tinr_fifo_size_pos 2
  4403. -#define	reg_tinr_fifo_size_len 5
  4404. -#define	reg_tinr_fifo_size_lsb 0
  4405. -#define xd_p_reg_tinr_saturation_cnt_th	0xA081
  4406. -#define	reg_tinr_saturation_cnt_th_pos 0
  4407. -#define	reg_tinr_saturation_cnt_th_len 4
  4408. -#define	reg_tinr_saturation_cnt_th_lsb 0
  4409. -#define xd_p_reg_tinr_saturation_th_3_0	0xA081
  4410. -#define	reg_tinr_saturation_th_3_0_pos 4
  4411. -#define	reg_tinr_saturation_th_3_0_len 4
  4412. -#define	reg_tinr_saturation_th_3_0_lsb 0
  4413. -#define xd_p_reg_tinr_saturation_th_8_4	0xA082
  4414. -#define	reg_tinr_saturation_th_8_4_pos 0
  4415. -#define	reg_tinr_saturation_th_8_4_len 5
  4416. -#define	reg_tinr_saturation_th_8_4_lsb 4
  4417. -#define xd_p_reg_tinr_imp_duration_th_2k_7_0	0xA083
  4418. -#define	reg_tinr_imp_duration_th_2k_7_0_pos 0
  4419. -#define	reg_tinr_imp_duration_th_2k_7_0_len 8
  4420. -#define	reg_tinr_imp_duration_th_2k_7_0_lsb 0
  4421. -#define xd_p_reg_tinr_imp_duration_th_2k_8	0xA084
  4422. -#define	reg_tinr_imp_duration_th_2k_8_pos 0
  4423. -#define	reg_tinr_imp_duration_th_2k_8_len 1
  4424. -#define	reg_tinr_imp_duration_th_2k_8_lsb 0
  4425. -#define xd_p_reg_tinr_imp_duration_th_8k_7_0	0xA085
  4426. -#define	reg_tinr_imp_duration_th_8k_7_0_pos 0
  4427. -#define	reg_tinr_imp_duration_th_8k_7_0_len 8
  4428. -#define	reg_tinr_imp_duration_th_8k_7_0_lsb 0
  4429. -#define xd_p_reg_tinr_imp_duration_th_8k_10_8	0xA086
  4430. -#define	reg_tinr_imp_duration_th_8k_10_8_pos 0
  4431. -#define	reg_tinr_imp_duration_th_8k_10_8_len 3
  4432. -#define	reg_tinr_imp_duration_th_8k_10_8_lsb 8
  4433. -#define xd_p_reg_tinr_freq_ratio_6m_7_0	0xA087
  4434. -#define	reg_tinr_freq_ratio_6m_7_0_pos 0
  4435. -#define	reg_tinr_freq_ratio_6m_7_0_len 8
  4436. -#define	reg_tinr_freq_ratio_6m_7_0_lsb 0
  4437. -#define xd_p_reg_tinr_freq_ratio_6m_12_8	0xA088
  4438. -#define	reg_tinr_freq_ratio_6m_12_8_pos 0
  4439. -#define	reg_tinr_freq_ratio_6m_12_8_len 5
  4440. -#define	reg_tinr_freq_ratio_6m_12_8_lsb 8
  4441. -#define xd_p_reg_tinr_freq_ratio_7m_7_0	0xA089
  4442. -#define	reg_tinr_freq_ratio_7m_7_0_pos 0
  4443. -#define	reg_tinr_freq_ratio_7m_7_0_len 8
  4444. -#define	reg_tinr_freq_ratio_7m_7_0_lsb 0
  4445. -#define xd_p_reg_tinr_freq_ratio_7m_12_8	0xA08A
  4446. -#define	reg_tinr_freq_ratio_7m_12_8_pos 0
  4447. -#define	reg_tinr_freq_ratio_7m_12_8_len 5
  4448. -#define	reg_tinr_freq_ratio_7m_12_8_lsb 8
  4449. -#define xd_p_reg_tinr_freq_ratio_8m_7_0	0xA08B
  4450. -#define	reg_tinr_freq_ratio_8m_7_0_pos 0
  4451. -#define	reg_tinr_freq_ratio_8m_7_0_len 8
  4452. -#define	reg_tinr_freq_ratio_8m_7_0_lsb 0
  4453. -#define xd_p_reg_tinr_freq_ratio_8m_12_8	0xA08C
  4454. -#define	reg_tinr_freq_ratio_8m_12_8_pos 0
  4455. -#define	reg_tinr_freq_ratio_8m_12_8_len 5
  4456. -#define	reg_tinr_freq_ratio_8m_12_8_lsb 8
  4457. -#define xd_p_reg_tinr_imp_duration_th_low_2k	0xA08D
  4458. -#define	reg_tinr_imp_duration_th_low_2k_pos 0
  4459. -#define	reg_tinr_imp_duration_th_low_2k_len 8
  4460. -#define	reg_tinr_imp_duration_th_low_2k_lsb 0
  4461. -#define xd_p_reg_tinr_imp_duration_th_low_8k	0xA08E
  4462. -#define	reg_tinr_imp_duration_th_low_8k_pos 0
  4463. -#define	reg_tinr_imp_duration_th_low_8k_len 8
  4464. -#define	reg_tinr_imp_duration_th_low_8k_lsb 0
  4465. -#define xd_r_reg_tinr_counter_7_0	0xA090
  4466. -#define	reg_tinr_counter_7_0_pos 0
  4467. -#define	reg_tinr_counter_7_0_len 8
  4468. -#define	reg_tinr_counter_7_0_lsb 0
  4469. -#define xd_r_reg_tinr_counter_15_8	0xA091
  4470. -#define	reg_tinr_counter_15_8_pos 0
  4471. -#define	reg_tinr_counter_15_8_len 8
  4472. -#define	reg_tinr_counter_15_8_lsb 8
  4473. -#define xd_p_reg_tinr_adative_tinr_en	0xA093
  4474. -#define	reg_tinr_adative_tinr_en_pos 0
  4475. -#define	reg_tinr_adative_tinr_en_len 1
  4476. -#define	reg_tinr_adative_tinr_en_lsb 0
  4477. -#define xd_p_reg_tinr_peak_fifo_size	0xA093
  4478. -#define	reg_tinr_peak_fifo_size_pos 1
  4479. -#define	reg_tinr_peak_fifo_size_len 5
  4480. -#define	reg_tinr_peak_fifo_size_lsb 0
  4481. -#define xd_p_reg_tinr_counter_rst	0xA093
  4482. -#define	reg_tinr_counter_rst_pos 6
  4483. -#define	reg_tinr_counter_rst_len 1
  4484. -#define	reg_tinr_counter_rst_lsb 0
  4485. -#define xd_p_reg_tinr_search_period_7_0	0xA094
  4486. -#define	reg_tinr_search_period_7_0_pos 0
  4487. -#define	reg_tinr_search_period_7_0_len 8
  4488. -#define	reg_tinr_search_period_7_0_lsb 0
  4489. -#define xd_p_reg_tinr_search_period_15_8	0xA095
  4490. -#define	reg_tinr_search_period_15_8_pos 0
  4491. -#define	reg_tinr_search_period_15_8_len 8
  4492. -#define	reg_tinr_search_period_15_8_lsb 8
  4493. -#define xd_p_reg_ccifs_fcw_7_0	0xA0A0
  4494. -#define	reg_ccifs_fcw_7_0_pos 0
  4495. -#define	reg_ccifs_fcw_7_0_len 8
  4496. -#define	reg_ccifs_fcw_7_0_lsb 0
  4497. -#define xd_p_reg_ccifs_fcw_12_8	0xA0A1
  4498. -#define	reg_ccifs_fcw_12_8_pos 0
  4499. -#define	reg_ccifs_fcw_12_8_len 5
  4500. -#define	reg_ccifs_fcw_12_8_lsb 8
  4501. -#define xd_p_reg_ccifs_spec_inv	0xA0A1
  4502. -#define	reg_ccifs_spec_inv_pos 5
  4503. -#define	reg_ccifs_spec_inv_len 1
  4504. -#define	reg_ccifs_spec_inv_lsb 0
  4505. -#define xd_p_reg_gp_trigger	0xA0A2
  4506. -#define	reg_gp_trigger_pos 0
  4507. -#define	reg_gp_trigger_len 1
  4508. -#define	reg_gp_trigger_lsb 0
  4509. -#define xd_p_reg_trigger_sel	0xA0A2
  4510. -#define	reg_trigger_sel_pos 1
  4511. -#define	reg_trigger_sel_len 2
  4512. -#define	reg_trigger_sel_lsb 0
  4513. -#define xd_p_reg_debug_ofdm	0xA0A2
  4514. -#define	reg_debug_ofdm_pos 3
  4515. -#define	reg_debug_ofdm_len 2
  4516. -#define	reg_debug_ofdm_lsb 0
  4517. -#define xd_p_reg_trigger_module_sel	0xA0A3
  4518. -#define	reg_trigger_module_sel_pos 0
  4519. -#define	reg_trigger_module_sel_len 6
  4520. -#define	reg_trigger_module_sel_lsb 0
  4521. -#define xd_p_reg_trigger_set_sel	0xA0A4
  4522. -#define	reg_trigger_set_sel_pos 0
  4523. -#define	reg_trigger_set_sel_len 6
  4524. -#define	reg_trigger_set_sel_lsb 0
  4525. -#define xd_p_reg_fw_int_mask_n	0xA0A4
  4526. -#define	reg_fw_int_mask_n_pos 6
  4527. -#define	reg_fw_int_mask_n_len 1
  4528. -#define	reg_fw_int_mask_n_lsb 0
  4529. -#define xd_p_reg_debug_group	0xA0A5
  4530. -#define	reg_debug_group_pos 0
  4531. -#define	reg_debug_group_len 4
  4532. -#define	reg_debug_group_lsb 0
  4533. -#define xd_p_reg_odbg_clk_sel	0xA0A5
  4534. -#define	reg_odbg_clk_sel_pos 4
  4535. -#define	reg_odbg_clk_sel_len 2
  4536. -#define	reg_odbg_clk_sel_lsb 0
  4537. -#define xd_p_reg_ccif_sc	0xA0C0
  4538. -#define	reg_ccif_sc_pos 0
  4539. -#define	reg_ccif_sc_len 4
  4540. -#define	reg_ccif_sc_lsb 0
  4541. -#define xd_r_reg_ccif_saturate	0xA0C1
  4542. -#define	reg_ccif_saturate_pos 0
  4543. -#define	reg_ccif_saturate_len 2
  4544. -#define	reg_ccif_saturate_lsb 0
  4545. -#define xd_r_reg_antif_saturate	0xA0C1
  4546. -#define	reg_antif_saturate_pos 2
  4547. -#define	reg_antif_saturate_len 4
  4548. -#define	reg_antif_saturate_lsb 0
  4549. -#define xd_r_reg_acif_saturate	0xA0C2
  4550. -#define	reg_acif_saturate_pos 0
  4551. -#define	reg_acif_saturate_len 8
  4552. -#define	reg_acif_saturate_lsb 0
  4553. -#define xd_p_reg_tmr_timer0_threshold_7_0	0xA0C8
  4554. -#define	reg_tmr_timer0_threshold_7_0_pos 0
  4555. -#define	reg_tmr_timer0_threshold_7_0_len 8
  4556. -#define	reg_tmr_timer0_threshold_7_0_lsb 0
  4557. -#define xd_p_reg_tmr_timer0_threshold_15_8	0xA0C9
  4558. -#define	reg_tmr_timer0_threshold_15_8_pos 0
  4559. -#define	reg_tmr_timer0_threshold_15_8_len 8
  4560. -#define	reg_tmr_timer0_threshold_15_8_lsb 8
  4561. -#define xd_p_reg_tmr_timer0_enable	0xA0CA
  4562. -#define	reg_tmr_timer0_enable_pos 0
  4563. -#define	reg_tmr_timer0_enable_len 1
  4564. -#define	reg_tmr_timer0_enable_lsb 0
  4565. -#define xd_p_reg_tmr_timer0_clk_sel	0xA0CA
  4566. -#define	reg_tmr_timer0_clk_sel_pos 1
  4567. -#define	reg_tmr_timer0_clk_sel_len 1
  4568. -#define	reg_tmr_timer0_clk_sel_lsb 0
  4569. -#define xd_p_reg_tmr_timer0_int	0xA0CA
  4570. -#define	reg_tmr_timer0_int_pos 2
  4571. -#define	reg_tmr_timer0_int_len 1
  4572. -#define	reg_tmr_timer0_int_lsb 0
  4573. -#define xd_p_reg_tmr_timer0_rst	0xA0CA
  4574. -#define	reg_tmr_timer0_rst_pos 3
  4575. -#define	reg_tmr_timer0_rst_len 1
  4576. -#define	reg_tmr_timer0_rst_lsb 0
  4577. -#define xd_r_reg_tmr_timer0_count_7_0	0xA0CB
  4578. -#define	reg_tmr_timer0_count_7_0_pos 0
  4579. -#define	reg_tmr_timer0_count_7_0_len 8
  4580. -#define	reg_tmr_timer0_count_7_0_lsb 0
  4581. -#define xd_r_reg_tmr_timer0_count_15_8	0xA0CC
  4582. -#define	reg_tmr_timer0_count_15_8_pos 0
  4583. -#define	reg_tmr_timer0_count_15_8_len 8
  4584. -#define	reg_tmr_timer0_count_15_8_lsb 8
  4585. -#define xd_p_reg_suspend	0xA0CD
  4586. -#define	reg_suspend_pos 0
  4587. -#define	reg_suspend_len 1
  4588. -#define	reg_suspend_lsb 0
  4589. -#define xd_p_reg_suspend_rdy	0xA0CD
  4590. -#define	reg_suspend_rdy_pos 1
  4591. -#define	reg_suspend_rdy_len 1
  4592. -#define	reg_suspend_rdy_lsb 0
  4593. -#define xd_p_reg_resume	0xA0CD
  4594. -#define	reg_resume_pos 2
  4595. -#define	reg_resume_len 1
  4596. -#define	reg_resume_lsb 0
  4597. -#define xd_p_reg_resume_rdy	0xA0CD
  4598. -#define	reg_resume_rdy_pos 3
  4599. -#define	reg_resume_rdy_len 1
  4600. -#define	reg_resume_rdy_lsb 0
  4601. -#define xd_p_reg_fmf	0xA0CE
  4602. -#define	reg_fmf_pos 0
  4603. -#define	reg_fmf_len 8
  4604. -#define	reg_fmf_lsb 0
  4605. -#define xd_p_ccid_accumulate_num_2k_7_0	0xA100
  4606. -#define	ccid_accumulate_num_2k_7_0_pos 0
  4607. -#define	ccid_accumulate_num_2k_7_0_len 8
  4608. -#define	ccid_accumulate_num_2k_7_0_lsb 0
  4609. -#define xd_p_ccid_accumulate_num_2k_12_8	0xA101
  4610. -#define	ccid_accumulate_num_2k_12_8_pos 0
  4611. -#define	ccid_accumulate_num_2k_12_8_len 5
  4612. -#define	ccid_accumulate_num_2k_12_8_lsb 8
  4613. -#define xd_p_ccid_accumulate_num_8k_7_0	0xA102
  4614. -#define	ccid_accumulate_num_8k_7_0_pos 0
  4615. -#define	ccid_accumulate_num_8k_7_0_len 8
  4616. -#define	ccid_accumulate_num_8k_7_0_lsb 0
  4617. -#define xd_p_ccid_accumulate_num_8k_14_8	0xA103
  4618. -#define	ccid_accumulate_num_8k_14_8_pos 0
  4619. -#define	ccid_accumulate_num_8k_14_8_len 7
  4620. -#define	ccid_accumulate_num_8k_14_8_lsb 8
  4621. -#define xd_p_ccid_desired_level_0	0xA103
  4622. -#define	ccid_desired_level_0_pos 7
  4623. -#define	ccid_desired_level_0_len 1
  4624. -#define	ccid_desired_level_0_lsb 0
  4625. -#define xd_p_ccid_desired_level_8_1	0xA104
  4626. -#define	ccid_desired_level_8_1_pos 0
  4627. -#define	ccid_desired_level_8_1_len 8
  4628. -#define	ccid_desired_level_8_1_lsb 1
  4629. -#define xd_p_ccid_apply_delay	0xA105
  4630. -#define	ccid_apply_delay_pos 0
  4631. -#define	ccid_apply_delay_len 7
  4632. -#define	ccid_apply_delay_lsb 0
  4633. -#define xd_p_ccid_CCID_Threshold1	0xA106
  4634. -#define	ccid_CCID_Threshold1_pos 0
  4635. -#define	ccid_CCID_Threshold1_len 8
  4636. -#define	ccid_CCID_Threshold1_lsb 0
  4637. -#define xd_p_ccid_CCID_Threshold2	0xA107
  4638. -#define	ccid_CCID_Threshold2_pos 0
  4639. -#define	ccid_CCID_Threshold2_len 8
  4640. -#define	ccid_CCID_Threshold2_lsb 0
  4641. -#define xd_p_reg_ccid_gain_scale	0xA108
  4642. -#define	reg_ccid_gain_scale_pos 0
  4643. -#define	reg_ccid_gain_scale_len 4
  4644. -#define	reg_ccid_gain_scale_lsb 0
  4645. -#define xd_p_reg_ccid2_passband_gain_set	0xA108
  4646. -#define	reg_ccid2_passband_gain_set_pos 4
  4647. -#define	reg_ccid2_passband_gain_set_len 4
  4648. -#define	reg_ccid2_passband_gain_set_lsb 0
  4649. -#define xd_r_ccid_multiplier_7_0	0xA109
  4650. -#define	ccid_multiplier_7_0_pos 0
  4651. -#define	ccid_multiplier_7_0_len 8
  4652. -#define	ccid_multiplier_7_0_lsb 0
  4653. -#define xd_r_ccid_multiplier_15_8	0xA10A
  4654. -#define	ccid_multiplier_15_8_pos 0
  4655. -#define	ccid_multiplier_15_8_len 8
  4656. -#define	ccid_multiplier_15_8_lsb 8
  4657. -#define xd_r_ccid_right_shift_bits	0xA10B
  4658. -#define	ccid_right_shift_bits_pos 0
  4659. -#define	ccid_right_shift_bits_len 4
  4660. -#define	ccid_right_shift_bits_lsb 0
  4661. -#define xd_r_reg_ccid_sx_7_0	0xA10C
  4662. -#define	reg_ccid_sx_7_0_pos 0
  4663. -#define	reg_ccid_sx_7_0_len 8
  4664. -#define	reg_ccid_sx_7_0_lsb 0
  4665. -#define xd_r_reg_ccid_sx_15_8	0xA10D
  4666. -#define	reg_ccid_sx_15_8_pos 0
  4667. -#define	reg_ccid_sx_15_8_len 8
  4668. -#define	reg_ccid_sx_15_8_lsb 8
  4669. -#define xd_r_reg_ccid_sx_21_16	0xA10E
  4670. -#define	reg_ccid_sx_21_16_pos 0
  4671. -#define	reg_ccid_sx_21_16_len 6
  4672. -#define	reg_ccid_sx_21_16_lsb 16
  4673. -#define xd_r_reg_ccid_sy_7_0	0xA110
  4674. -#define	reg_ccid_sy_7_0_pos 0
  4675. -#define	reg_ccid_sy_7_0_len 8
  4676. -#define	reg_ccid_sy_7_0_lsb 0
  4677. -#define xd_r_reg_ccid_sy_15_8	0xA111
  4678. -#define	reg_ccid_sy_15_8_pos 0
  4679. -#define	reg_ccid_sy_15_8_len 8
  4680. -#define	reg_ccid_sy_15_8_lsb 8
  4681. -#define xd_r_reg_ccid_sy_23_16	0xA112
  4682. -#define	reg_ccid_sy_23_16_pos 0
  4683. -#define	reg_ccid_sy_23_16_len 8
  4684. -#define	reg_ccid_sy_23_16_lsb 16
  4685. -#define xd_r_reg_ccid2_sz_7_0	0xA114
  4686. -#define	reg_ccid2_sz_7_0_pos 0
  4687. -#define	reg_ccid2_sz_7_0_len 8
  4688. -#define	reg_ccid2_sz_7_0_lsb 0
  4689. -#define xd_r_reg_ccid2_sz_15_8	0xA115
  4690. -#define	reg_ccid2_sz_15_8_pos 0
  4691. -#define	reg_ccid2_sz_15_8_len 8
  4692. -#define	reg_ccid2_sz_15_8_lsb 8
  4693. -#define xd_r_reg_ccid2_sz_23_16	0xA116
  4694. -#define	reg_ccid2_sz_23_16_pos 0
  4695. -#define	reg_ccid2_sz_23_16_len 8
  4696. -#define	reg_ccid2_sz_23_16_lsb 16
  4697. -#define xd_r_reg_ccid2_sz_25_24	0xA117
  4698. -#define	reg_ccid2_sz_25_24_pos 0
  4699. -#define	reg_ccid2_sz_25_24_len 2
  4700. -#define	reg_ccid2_sz_25_24_lsb 24
  4701. -#define xd_r_reg_ccid2_sy_7_0	0xA118
  4702. -#define	reg_ccid2_sy_7_0_pos 0
  4703. -#define	reg_ccid2_sy_7_0_len 8
  4704. -#define	reg_ccid2_sy_7_0_lsb 0
  4705. -#define xd_r_reg_ccid2_sy_15_8	0xA119
  4706. -#define	reg_ccid2_sy_15_8_pos 0
  4707. -#define	reg_ccid2_sy_15_8_len 8
  4708. -#define	reg_ccid2_sy_15_8_lsb 8
  4709. -#define xd_r_reg_ccid2_sy_23_16	0xA11A
  4710. -#define	reg_ccid2_sy_23_16_pos 0
  4711. -#define	reg_ccid2_sy_23_16_len 8
  4712. -#define	reg_ccid2_sy_23_16_lsb 16
  4713. -#define xd_r_reg_ccid2_sy_25_24	0xA11B
  4714. -#define	reg_ccid2_sy_25_24_pos 0
  4715. -#define	reg_ccid2_sy_25_24_len 2
  4716. -#define	reg_ccid2_sy_25_24_lsb 24
  4717. -#define xd_p_dagc1_accumulate_num_2k_7_0	0xA120
  4718. -#define	dagc1_accumulate_num_2k_7_0_pos 0
  4719. -#define	dagc1_accumulate_num_2k_7_0_len 8
  4720. -#define	dagc1_accumulate_num_2k_7_0_lsb 0
  4721. -#define xd_p_dagc1_accumulate_num_2k_12_8	0xA121
  4722. -#define	dagc1_accumulate_num_2k_12_8_pos 0
  4723. -#define	dagc1_accumulate_num_2k_12_8_len 5
  4724. -#define	dagc1_accumulate_num_2k_12_8_lsb 8
  4725. -#define xd_p_dagc1_accumulate_num_8k_7_0	0xA122
  4726. -#define	dagc1_accumulate_num_8k_7_0_pos 0
  4727. -#define	dagc1_accumulate_num_8k_7_0_len 8
  4728. -#define	dagc1_accumulate_num_8k_7_0_lsb 0
  4729. -#define xd_p_dagc1_accumulate_num_8k_14_8	0xA123
  4730. -#define	dagc1_accumulate_num_8k_14_8_pos 0
  4731. -#define	dagc1_accumulate_num_8k_14_8_len 7
  4732. -#define	dagc1_accumulate_num_8k_14_8_lsb 8
  4733. -#define xd_p_dagc1_desired_level_0	0xA123
  4734. -#define	dagc1_desired_level_0_pos 7
  4735. -#define	dagc1_desired_level_0_len 1
  4736. -#define	dagc1_desired_level_0_lsb 0
  4737. -#define xd_p_dagc1_desired_level_8_1	0xA124
  4738. -#define	dagc1_desired_level_8_1_pos 0
  4739. -#define	dagc1_desired_level_8_1_len 8
  4740. -#define	dagc1_desired_level_8_1_lsb 1
  4741. -#define xd_p_dagc1_apply_delay	0xA125
  4742. -#define	dagc1_apply_delay_pos 0
  4743. -#define	dagc1_apply_delay_len 7
  4744. -#define	dagc1_apply_delay_lsb 0
  4745. -#define xd_p_dagc1_bypass_scale_ctl	0xA126
  4746. -#define	dagc1_bypass_scale_ctl_pos 0
  4747. -#define	dagc1_bypass_scale_ctl_len 2
  4748. -#define	dagc1_bypass_scale_ctl_lsb 0
  4749. -#define xd_p_reg_dagc1_in_sat_cnt_7_0	0xA127
  4750. -#define	reg_dagc1_in_sat_cnt_7_0_pos 0
  4751. -#define	reg_dagc1_in_sat_cnt_7_0_len 8
  4752. -#define	reg_dagc1_in_sat_cnt_7_0_lsb 0
  4753. -#define xd_p_reg_dagc1_in_sat_cnt_15_8	0xA128
  4754. -#define	reg_dagc1_in_sat_cnt_15_8_pos 0
  4755. -#define	reg_dagc1_in_sat_cnt_15_8_len 8
  4756. -#define	reg_dagc1_in_sat_cnt_15_8_lsb 8
  4757. -#define xd_p_reg_dagc1_in_sat_cnt_23_16	0xA129
  4758. -#define	reg_dagc1_in_sat_cnt_23_16_pos 0
  4759. -#define	reg_dagc1_in_sat_cnt_23_16_len 8
  4760. -#define	reg_dagc1_in_sat_cnt_23_16_lsb 16
  4761. -#define xd_p_reg_dagc1_in_sat_cnt_31_24	0xA12A
  4762. -#define	reg_dagc1_in_sat_cnt_31_24_pos 0
  4763. -#define	reg_dagc1_in_sat_cnt_31_24_len 8
  4764. -#define	reg_dagc1_in_sat_cnt_31_24_lsb 24
  4765. -#define xd_p_reg_dagc1_out_sat_cnt_7_0	0xA12B
  4766. -#define	reg_dagc1_out_sat_cnt_7_0_pos 0
  4767. -#define	reg_dagc1_out_sat_cnt_7_0_len 8
  4768. -#define	reg_dagc1_out_sat_cnt_7_0_lsb 0
  4769. -#define xd_p_reg_dagc1_out_sat_cnt_15_8	0xA12C
  4770. -#define	reg_dagc1_out_sat_cnt_15_8_pos 0
  4771. -#define	reg_dagc1_out_sat_cnt_15_8_len 8
  4772. -#define	reg_dagc1_out_sat_cnt_15_8_lsb 8
  4773. -#define xd_p_reg_dagc1_out_sat_cnt_23_16	0xA12D
  4774. -#define	reg_dagc1_out_sat_cnt_23_16_pos 0
  4775. -#define	reg_dagc1_out_sat_cnt_23_16_len 8
  4776. -#define	reg_dagc1_out_sat_cnt_23_16_lsb 16
  4777. -#define xd_p_reg_dagc1_out_sat_cnt_31_24	0xA12E
  4778. -#define	reg_dagc1_out_sat_cnt_31_24_pos 0
  4779. -#define	reg_dagc1_out_sat_cnt_31_24_len 8
  4780. -#define	reg_dagc1_out_sat_cnt_31_24_lsb 24
  4781. -#define xd_r_dagc1_multiplier_7_0	0xA136
  4782. -#define	dagc1_multiplier_7_0_pos 0
  4783. -#define	dagc1_multiplier_7_0_len 8
  4784. -#define	dagc1_multiplier_7_0_lsb 0
  4785. -#define xd_r_dagc1_multiplier_15_8	0xA137
  4786. -#define	dagc1_multiplier_15_8_pos 0
  4787. -#define	dagc1_multiplier_15_8_len 8
  4788. -#define	dagc1_multiplier_15_8_lsb 8
  4789. -#define xd_r_dagc1_right_shift_bits	0xA138
  4790. -#define	dagc1_right_shift_bits_pos 0
  4791. -#define	dagc1_right_shift_bits_len 4
  4792. -#define	dagc1_right_shift_bits_lsb 0
  4793. -#define xd_p_reg_bfs_fcw_7_0	0xA140
  4794. -#define	reg_bfs_fcw_7_0_pos 0
  4795. -#define	reg_bfs_fcw_7_0_len 8
  4796. -#define	reg_bfs_fcw_7_0_lsb 0
  4797. -#define xd_p_reg_bfs_fcw_15_8	0xA141
  4798. -#define	reg_bfs_fcw_15_8_pos 0
  4799. -#define	reg_bfs_fcw_15_8_len 8
  4800. -#define	reg_bfs_fcw_15_8_lsb 8
  4801. -#define xd_p_reg_bfs_fcw_22_16	0xA142
  4802. -#define	reg_bfs_fcw_22_16_pos 0
  4803. -#define	reg_bfs_fcw_22_16_len 7
  4804. -#define	reg_bfs_fcw_22_16_lsb 16
  4805. -#define xd_p_reg_antif_sf_7_0	0xA144
  4806. -#define	reg_antif_sf_7_0_pos 0
  4807. -#define	reg_antif_sf_7_0_len 8
  4808. -#define	reg_antif_sf_7_0_lsb 0
  4809. -#define xd_p_reg_antif_sf_11_8	0xA145
  4810. -#define	reg_antif_sf_11_8_pos 0
  4811. -#define	reg_antif_sf_11_8_len 4
  4812. -#define	reg_antif_sf_11_8_lsb 8
  4813. -#define xd_r_bfs_fcw_q_7_0	0xA150
  4814. -#define	bfs_fcw_q_7_0_pos 0
  4815. -#define	bfs_fcw_q_7_0_len 8
  4816. -#define	bfs_fcw_q_7_0_lsb 0
  4817. -#define xd_r_bfs_fcw_q_15_8	0xA151
  4818. -#define	bfs_fcw_q_15_8_pos 0
  4819. -#define	bfs_fcw_q_15_8_len 8
  4820. -#define	bfs_fcw_q_15_8_lsb 8
  4821. -#define xd_r_bfs_fcw_q_22_16	0xA152
  4822. -#define	bfs_fcw_q_22_16_pos 0
  4823. -#define	bfs_fcw_q_22_16_len 7
  4824. -#define	bfs_fcw_q_22_16_lsb 16
  4825. -#define xd_p_reg_dca_enu	0xA160
  4826. -#define	reg_dca_enu_pos 0
  4827. -#define	reg_dca_enu_len 1
  4828. -#define	reg_dca_enu_lsb 0
  4829. -#define xd_p_reg_dca_enl	0xA160
  4830. -#define	reg_dca_enl_pos 1
  4831. -#define	reg_dca_enl_len 1
  4832. -#define	reg_dca_enl_lsb 0
  4833. -#define xd_p_reg_dca_lower_chip	0xA160
  4834. -#define	reg_dca_lower_chip_pos 2
  4835. -#define	reg_dca_lower_chip_len 1
  4836. -#define	reg_dca_lower_chip_lsb 0
  4837. -#define xd_p_reg_dca_upper_chip	0xA160
  4838. -#define	reg_dca_upper_chip_pos 3
  4839. -#define	reg_dca_upper_chip_len 1
  4840. -#define	reg_dca_upper_chip_lsb 0
  4841. -#define xd_p_reg_dca_platch	0xA160
  4842. -#define	reg_dca_platch_pos 4
  4843. -#define	reg_dca_platch_len 1
  4844. -#define	reg_dca_platch_lsb 0
  4845. -#define xd_p_reg_dca_th	0xA161
  4846. -#define	reg_dca_th_pos 0
  4847. -#define	reg_dca_th_len 5
  4848. -#define	reg_dca_th_lsb 0
  4849. -#define xd_p_reg_dca_scale	0xA162
  4850. -#define	reg_dca_scale_pos 0
  4851. -#define	reg_dca_scale_len 4
  4852. -#define	reg_dca_scale_lsb 0
  4853. -#define xd_p_reg_dca_tone_7_0	0xA163
  4854. -#define	reg_dca_tone_7_0_pos 0
  4855. -#define	reg_dca_tone_7_0_len 8
  4856. -#define	reg_dca_tone_7_0_lsb 0
  4857. -#define xd_p_reg_dca_tone_12_8	0xA164
  4858. -#define	reg_dca_tone_12_8_pos 0
  4859. -#define	reg_dca_tone_12_8_len 5
  4860. -#define	reg_dca_tone_12_8_lsb 8
  4861. -#define xd_p_reg_dca_time_7_0	0xA165
  4862. -#define	reg_dca_time_7_0_pos 0
  4863. -#define	reg_dca_time_7_0_len 8
  4864. -#define	reg_dca_time_7_0_lsb 0
  4865. -#define xd_p_reg_dca_time_15_8	0xA166
  4866. -#define	reg_dca_time_15_8_pos 0
  4867. -#define	reg_dca_time_15_8_len 8
  4868. -#define	reg_dca_time_15_8_lsb 8
  4869. -#define xd_r_dcasm	0xA167
  4870. -#define	dcasm_pos 0
  4871. -#define	dcasm_len 3
  4872. -#define	dcasm_lsb 0
  4873. -#define xd_p_reg_qnt_valuew_7_0	0xA168
  4874. -#define	reg_qnt_valuew_7_0_pos 0
  4875. -#define	reg_qnt_valuew_7_0_len 8
  4876. -#define	reg_qnt_valuew_7_0_lsb 0
  4877. -#define xd_p_reg_qnt_valuew_10_8	0xA169
  4878. -#define	reg_qnt_valuew_10_8_pos 0
  4879. -#define	reg_qnt_valuew_10_8_len 3
  4880. -#define	reg_qnt_valuew_10_8_lsb 8
  4881. -#define xd_p_dca_sbx_gain_diff_7_0	0xA16A
  4882. -#define	dca_sbx_gain_diff_7_0_pos 0
  4883. -#define	dca_sbx_gain_diff_7_0_len 8
  4884. -#define	dca_sbx_gain_diff_7_0_lsb 0
  4885. -#define xd_p_dca_sbx_gain_diff_9_8	0xA16B
  4886. -#define	dca_sbx_gain_diff_9_8_pos 0
  4887. -#define	dca_sbx_gain_diff_9_8_len 2
  4888. -#define	dca_sbx_gain_diff_9_8_lsb 8
  4889. -#define xd_p_reg_dca_stand_alone	0xA16C
  4890. -#define	reg_dca_stand_alone_pos 0
  4891. -#define	reg_dca_stand_alone_len 1
  4892. -#define	reg_dca_stand_alone_lsb 0
  4893. -#define xd_p_reg_dca_upper_out_en	0xA16C
  4894. -#define	reg_dca_upper_out_en_pos 1
  4895. -#define	reg_dca_upper_out_en_len 1
  4896. -#define	reg_dca_upper_out_en_lsb 0
  4897. -#define xd_p_reg_dca_rc_en	0xA16C
  4898. -#define	reg_dca_rc_en_pos 2
  4899. -#define	reg_dca_rc_en_len 1
  4900. -#define	reg_dca_rc_en_lsb 0
  4901. -#define xd_p_reg_dca_retrain_send	0xA16C
  4902. -#define	reg_dca_retrain_send_pos 3
  4903. -#define	reg_dca_retrain_send_len 1
  4904. -#define	reg_dca_retrain_send_lsb 0
  4905. -#define xd_p_reg_dca_retrain_rec	0xA16C
  4906. -#define	reg_dca_retrain_rec_pos 4
  4907. -#define	reg_dca_retrain_rec_len 1
  4908. -#define	reg_dca_retrain_rec_lsb 0
  4909. -#define xd_p_reg_dca_api_tpsrdy	0xA16C
  4910. -#define	reg_dca_api_tpsrdy_pos 5
  4911. -#define	reg_dca_api_tpsrdy_len 1
  4912. -#define	reg_dca_api_tpsrdy_lsb 0
  4913. -#define xd_p_reg_dca_symbol_gap	0xA16D
  4914. -#define	reg_dca_symbol_gap_pos 0
  4915. -#define	reg_dca_symbol_gap_len 4
  4916. -#define	reg_dca_symbol_gap_lsb 0
  4917. -#define xd_p_reg_qnt_nfvaluew_7_0	0xA16E
  4918. -#define	reg_qnt_nfvaluew_7_0_pos 0
  4919. -#define	reg_qnt_nfvaluew_7_0_len 8
  4920. -#define	reg_qnt_nfvaluew_7_0_lsb 0
  4921. -#define xd_p_reg_qnt_nfvaluew_10_8	0xA16F
  4922. -#define	reg_qnt_nfvaluew_10_8_pos 0
  4923. -#define	reg_qnt_nfvaluew_10_8_len 3
  4924. -#define	reg_qnt_nfvaluew_10_8_lsb 8
  4925. -#define xd_p_reg_qnt_flatness_thr_7_0	0xA170
  4926. -#define	reg_qnt_flatness_thr_7_0_pos 0
  4927. -#define	reg_qnt_flatness_thr_7_0_len 8
  4928. -#define	reg_qnt_flatness_thr_7_0_lsb 0
  4929. -#define xd_p_reg_qnt_flatness_thr_9_8	0xA171
  4930. -#define	reg_qnt_flatness_thr_9_8_pos 0
  4931. -#define	reg_qnt_flatness_thr_9_8_len 2
  4932. -#define	reg_qnt_flatness_thr_9_8_lsb 8
  4933. -#define xd_p_reg_dca_tone_idx_5_0	0xA171
  4934. -#define	reg_dca_tone_idx_5_0_pos 2
  4935. -#define	reg_dca_tone_idx_5_0_len 6
  4936. -#define	reg_dca_tone_idx_5_0_lsb 0
  4937. -#define xd_p_reg_dca_tone_idx_12_6	0xA172
  4938. -#define	reg_dca_tone_idx_12_6_pos 0
  4939. -#define	reg_dca_tone_idx_12_6_len 7
  4940. -#define	reg_dca_tone_idx_12_6_lsb 6
  4941. -#define xd_p_reg_dca_data_vld	0xA173
  4942. -#define	reg_dca_data_vld_pos 0
  4943. -#define	reg_dca_data_vld_len 1
  4944. -#define	reg_dca_data_vld_lsb 0
  4945. -#define xd_p_reg_dca_read_update	0xA173
  4946. -#define	reg_dca_read_update_pos 1
  4947. -#define	reg_dca_read_update_len 1
  4948. -#define	reg_dca_read_update_lsb 0
  4949. -#define xd_r_reg_dca_data_re_5_0	0xA173
  4950. -#define	reg_dca_data_re_5_0_pos 2
  4951. -#define	reg_dca_data_re_5_0_len 6
  4952. -#define	reg_dca_data_re_5_0_lsb 0
  4953. -#define xd_r_reg_dca_data_re_10_6	0xA174
  4954. -#define	reg_dca_data_re_10_6_pos 0
  4955. -#define	reg_dca_data_re_10_6_len 5
  4956. -#define	reg_dca_data_re_10_6_lsb 6
  4957. -#define xd_r_reg_dca_data_im_7_0	0xA175
  4958. -#define	reg_dca_data_im_7_0_pos 0
  4959. -#define	reg_dca_data_im_7_0_len 8
  4960. -#define	reg_dca_data_im_7_0_lsb 0
  4961. -#define xd_r_reg_dca_data_im_10_8	0xA176
  4962. -#define	reg_dca_data_im_10_8_pos 0
  4963. -#define	reg_dca_data_im_10_8_len 3
  4964. -#define	reg_dca_data_im_10_8_lsb 8
  4965. -#define xd_r_reg_dca_data_h2_7_0	0xA178
  4966. -#define	reg_dca_data_h2_7_0_pos 0
  4967. -#define	reg_dca_data_h2_7_0_len 8
  4968. -#define	reg_dca_data_h2_7_0_lsb 0
  4969. -#define xd_r_reg_dca_data_h2_9_8	0xA179
  4970. -#define	reg_dca_data_h2_9_8_pos 0
  4971. -#define	reg_dca_data_h2_9_8_len 2
  4972. -#define	reg_dca_data_h2_9_8_lsb 8
  4973. -#define xd_p_reg_f_adc_7_0	0xA180
  4974. -#define	reg_f_adc_7_0_pos 0
  4975. -#define	reg_f_adc_7_0_len 8
  4976. -#define	reg_f_adc_7_0_lsb 0
  4977. -#define xd_p_reg_f_adc_15_8	0xA181
  4978. -#define	reg_f_adc_15_8_pos 0
  4979. -#define	reg_f_adc_15_8_len 8
  4980. -#define	reg_f_adc_15_8_lsb 8
  4981. -#define xd_p_reg_f_adc_23_16	0xA182
  4982. -#define	reg_f_adc_23_16_pos 0
  4983. -#define	reg_f_adc_23_16_len 8
  4984. -#define	reg_f_adc_23_16_lsb 16
  4985. -#define xd_r_intp_mu_7_0	0xA190
  4986. -#define	intp_mu_7_0_pos 0
  4987. -#define	intp_mu_7_0_len 8
  4988. -#define	intp_mu_7_0_lsb 0
  4989. -#define xd_r_intp_mu_15_8	0xA191
  4990. -#define	intp_mu_15_8_pos 0
  4991. -#define	intp_mu_15_8_len 8
  4992. -#define	intp_mu_15_8_lsb 8
  4993. -#define xd_r_intp_mu_19_16	0xA192
  4994. -#define	intp_mu_19_16_pos 0
  4995. -#define	intp_mu_19_16_len 4
  4996. -#define	intp_mu_19_16_lsb 16
  4997. -#define xd_p_reg_agc_rst	0xA1A0
  4998. -#define	reg_agc_rst_pos 0
  4999. -#define	reg_agc_rst_len 1
  5000. -#define	reg_agc_rst_lsb 0
  5001. -#define xd_p_rf_agc_en	0xA1A0
  5002. -#define	rf_agc_en_pos 1
  5003. -#define	rf_agc_en_len 1
  5004. -#define	rf_agc_en_lsb 0
  5005. -#define xd_p_rf_agc_dis	0xA1A0
  5006. -#define	rf_agc_dis_pos 2
  5007. -#define	rf_agc_dis_len 1
  5008. -#define	rf_agc_dis_lsb 0
  5009. -#define xd_p_if_agc_rst	0xA1A0
  5010. -#define	if_agc_rst_pos 3
  5011. -#define	if_agc_rst_len 1
  5012. -#define	if_agc_rst_lsb 0
  5013. -#define xd_p_if_agc_en	0xA1A0
  5014. -#define	if_agc_en_pos 4
  5015. -#define	if_agc_en_len 1
  5016. -#define	if_agc_en_lsb 0
  5017. -#define xd_p_if_agc_dis	0xA1A0
  5018. -#define	if_agc_dis_pos 5
  5019. -#define	if_agc_dis_len 1
  5020. -#define	if_agc_dis_lsb 0
  5021. -#define xd_p_agc_lock	0xA1A0
  5022. -#define	agc_lock_pos 6
  5023. -#define	agc_lock_len 1
  5024. -#define	agc_lock_lsb 0
  5025. -#define xd_p_reg_tinr_rst	0xA1A1
  5026. -#define	reg_tinr_rst_pos 0
  5027. -#define	reg_tinr_rst_len 1
  5028. -#define	reg_tinr_rst_lsb 0
  5029. -#define xd_p_reg_tinr_en	0xA1A1
  5030. -#define	reg_tinr_en_pos 1
  5031. -#define	reg_tinr_en_len 1
  5032. -#define	reg_tinr_en_lsb 0
  5033. -#define xd_p_reg_ccifs_en	0xA1A2
  5034. -#define	reg_ccifs_en_pos 0
  5035. -#define	reg_ccifs_en_len 1
  5036. -#define	reg_ccifs_en_lsb 0
  5037. -#define xd_p_reg_ccifs_dis	0xA1A2
  5038. -#define	reg_ccifs_dis_pos 1
  5039. -#define	reg_ccifs_dis_len 1
  5040. -#define	reg_ccifs_dis_lsb 0
  5041. -#define xd_p_reg_ccifs_rst	0xA1A2
  5042. -#define	reg_ccifs_rst_pos 2
  5043. -#define	reg_ccifs_rst_len 1
  5044. -#define	reg_ccifs_rst_lsb 0
  5045. -#define xd_p_reg_ccifs_byp	0xA1A2
  5046. -#define	reg_ccifs_byp_pos 3
  5047. -#define	reg_ccifs_byp_len 1
  5048. -#define	reg_ccifs_byp_lsb 0
  5049. -#define xd_p_reg_ccif_en	0xA1A3
  5050. -#define	reg_ccif_en_pos 0
  5051. -#define	reg_ccif_en_len 1
  5052. -#define	reg_ccif_en_lsb 0
  5053. -#define xd_p_reg_ccif_dis	0xA1A3
  5054. -#define	reg_ccif_dis_pos 1
  5055. -#define	reg_ccif_dis_len 1
  5056. -#define	reg_ccif_dis_lsb 0
  5057. -#define xd_p_reg_ccif_rst	0xA1A3
  5058. -#define	reg_ccif_rst_pos 2
  5059. -#define	reg_ccif_rst_len 1
  5060. -#define	reg_ccif_rst_lsb 0
  5061. -#define xd_p_reg_ccif_byp	0xA1A3
  5062. -#define	reg_ccif_byp_pos 3
  5063. -#define	reg_ccif_byp_len 1
  5064. -#define	reg_ccif_byp_lsb 0
  5065. -#define xd_p_dagc1_rst	0xA1A4
  5066. -#define	dagc1_rst_pos 0
  5067. -#define	dagc1_rst_len 1
  5068. -#define	dagc1_rst_lsb 0
  5069. -#define xd_p_dagc1_en	0xA1A4
  5070. -#define	dagc1_en_pos 1
  5071. -#define	dagc1_en_len 1
  5072. -#define	dagc1_en_lsb 0
  5073. -#define xd_p_dagc1_mode	0xA1A4
  5074. -#define	dagc1_mode_pos 2
  5075. -#define	dagc1_mode_len 2
  5076. -#define	dagc1_mode_lsb 0
  5077. -#define xd_p_dagc1_done	0xA1A4
  5078. -#define	dagc1_done_pos 4
  5079. -#define	dagc1_done_len 1
  5080. -#define	dagc1_done_lsb 0
  5081. -#define xd_p_ccid_rst	0xA1A5
  5082. -#define	ccid_rst_pos 0
  5083. -#define	ccid_rst_len 1
  5084. -#define	ccid_rst_lsb 0
  5085. -#define xd_p_ccid_en	0xA1A5
  5086. -#define	ccid_en_pos 1
  5087. -#define	ccid_en_len 1
  5088. -#define	ccid_en_lsb 0
  5089. -#define xd_p_ccid_mode	0xA1A5
  5090. -#define	ccid_mode_pos 2
  5091. -#define	ccid_mode_len 2
  5092. -#define	ccid_mode_lsb 0
  5093. -#define xd_p_ccid_done	0xA1A5
  5094. -#define	ccid_done_pos 4
  5095. -#define	ccid_done_len 1
  5096. -#define	ccid_done_lsb 0
  5097. -#define xd_r_ccid_deted	0xA1A5
  5098. -#define	ccid_deted_pos 5
  5099. -#define	ccid_deted_len 1
  5100. -#define	ccid_deted_lsb 0
  5101. -#define xd_p_ccid2_en	0xA1A5
  5102. -#define	ccid2_en_pos 6
  5103. -#define	ccid2_en_len 1
  5104. -#define	ccid2_en_lsb 0
  5105. -#define xd_p_ccid2_done	0xA1A5
  5106. -#define	ccid2_done_pos 7
  5107. -#define	ccid2_done_len 1
  5108. -#define	ccid2_done_lsb 0
  5109. -#define xd_p_reg_bfs_en	0xA1A6
  5110. -#define	reg_bfs_en_pos 0
  5111. -#define	reg_bfs_en_len 1
  5112. -#define	reg_bfs_en_lsb 0
  5113. -#define xd_p_reg_bfs_dis	0xA1A6
  5114. -#define	reg_bfs_dis_pos 1
  5115. -#define	reg_bfs_dis_len 1
  5116. -#define	reg_bfs_dis_lsb 0
  5117. -#define xd_p_reg_bfs_rst	0xA1A6
  5118. -#define	reg_bfs_rst_pos 2
  5119. -#define	reg_bfs_rst_len 1
  5120. -#define	reg_bfs_rst_lsb 0
  5121. -#define xd_p_reg_bfs_byp	0xA1A6
  5122. -#define	reg_bfs_byp_pos 3
  5123. -#define	reg_bfs_byp_len 1
  5124. -#define	reg_bfs_byp_lsb 0
  5125. -#define xd_p_reg_antif_en	0xA1A7
  5126. -#define	reg_antif_en_pos 0
  5127. -#define	reg_antif_en_len 1
  5128. -#define	reg_antif_en_lsb 0
  5129. -#define xd_p_reg_antif_dis	0xA1A7
  5130. -#define	reg_antif_dis_pos 1
  5131. -#define	reg_antif_dis_len 1
  5132. -#define	reg_antif_dis_lsb 0
  5133. -#define xd_p_reg_antif_rst	0xA1A7
  5134. -#define	reg_antif_rst_pos 2
  5135. -#define	reg_antif_rst_len 1
  5136. -#define	reg_antif_rst_lsb 0
  5137. -#define xd_p_reg_antif_byp	0xA1A7
  5138. -#define	reg_antif_byp_pos 3
  5139. -#define	reg_antif_byp_len 1
  5140. -#define	reg_antif_byp_lsb 0
  5141. -#define xd_p_intp_en	0xA1A8
  5142. -#define	intp_en_pos 0
  5143. -#define	intp_en_len 1
  5144. -#define	intp_en_lsb 0
  5145. -#define xd_p_intp_dis	0xA1A8
  5146. -#define	intp_dis_pos 1
  5147. -#define	intp_dis_len 1
  5148. -#define	intp_dis_lsb 0
  5149. -#define xd_p_intp_rst	0xA1A8
  5150. -#define	intp_rst_pos 2
  5151. -#define	intp_rst_len 1
  5152. -#define	intp_rst_lsb 0
  5153. -#define xd_p_intp_byp	0xA1A8
  5154. -#define	intp_byp_pos 3
  5155. -#define	intp_byp_len 1
  5156. -#define	intp_byp_lsb 0
  5157. -#define xd_p_reg_acif_en	0xA1A9
  5158. -#define	reg_acif_en_pos 0
  5159. -#define	reg_acif_en_len 1
  5160. -#define	reg_acif_en_lsb 0
  5161. -#define xd_p_reg_acif_dis	0xA1A9
  5162. -#define	reg_acif_dis_pos 1
  5163. -#define	reg_acif_dis_len 1
  5164. -#define	reg_acif_dis_lsb 0
  5165. -#define xd_p_reg_acif_rst	0xA1A9
  5166. -#define	reg_acif_rst_pos 2
  5167. -#define	reg_acif_rst_len 1
  5168. -#define	reg_acif_rst_lsb 0
  5169. -#define xd_p_reg_acif_byp	0xA1A9
  5170. -#define	reg_acif_byp_pos 3
  5171. -#define	reg_acif_byp_len 1
  5172. -#define	reg_acif_byp_lsb 0
  5173. -#define xd_p_reg_acif_sync_mode	0xA1A9
  5174. -#define	reg_acif_sync_mode_pos 4
  5175. -#define	reg_acif_sync_mode_len 1
  5176. -#define	reg_acif_sync_mode_lsb 0
  5177. -#define xd_p_dagc2_rst	0xA1AA
  5178. -#define	dagc2_rst_pos 0
  5179. -#define	dagc2_rst_len 1
  5180. -#define	dagc2_rst_lsb 0
  5181. -#define xd_p_dagc2_en	0xA1AA
  5182. -#define	dagc2_en_pos 1
  5183. -#define	dagc2_en_len 1
  5184. -#define	dagc2_en_lsb 0
  5185. -#define xd_p_dagc2_mode	0xA1AA
  5186. -#define	dagc2_mode_pos 2
  5187. -#define	dagc2_mode_len 2
  5188. -#define	dagc2_mode_lsb 0
  5189. -#define xd_p_dagc2_done	0xA1AA
  5190. -#define	dagc2_done_pos 4
  5191. -#define	dagc2_done_len 1
  5192. -#define	dagc2_done_lsb 0
  5193. -#define xd_p_reg_dca_en	0xA1AB
  5194. -#define	reg_dca_en_pos 0
  5195. -#define	reg_dca_en_len 1
  5196. -#define	reg_dca_en_lsb 0
  5197. -#define xd_p_dagc2_accumulate_num_2k_7_0	0xA1C0
  5198. -#define	dagc2_accumulate_num_2k_7_0_pos 0
  5199. -#define	dagc2_accumulate_num_2k_7_0_len 8
  5200. -#define	dagc2_accumulate_num_2k_7_0_lsb 0
  5201. -#define xd_p_dagc2_accumulate_num_2k_12_8	0xA1C1
  5202. -#define	dagc2_accumulate_num_2k_12_8_pos 0
  5203. -#define	dagc2_accumulate_num_2k_12_8_len 5
  5204. -#define	dagc2_accumulate_num_2k_12_8_lsb 8
  5205. -#define xd_p_dagc2_accumulate_num_8k_7_0	0xA1C2
  5206. -#define	dagc2_accumulate_num_8k_7_0_pos 0
  5207. -#define	dagc2_accumulate_num_8k_7_0_len 8
  5208. -#define	dagc2_accumulate_num_8k_7_0_lsb 0
  5209. -#define xd_p_dagc2_accumulate_num_8k_12_8	0xA1C3
  5210. -#define	dagc2_accumulate_num_8k_12_8_pos 0
  5211. -#define	dagc2_accumulate_num_8k_12_8_len 5
  5212. -#define	dagc2_accumulate_num_8k_12_8_lsb 8
  5213. -#define xd_p_dagc2_desired_level_2_0	0xA1C3
  5214. -#define	dagc2_desired_level_2_0_pos 5
  5215. -#define	dagc2_desired_level_2_0_len 3
  5216. -#define	dagc2_desired_level_2_0_lsb 0
  5217. -#define xd_p_dagc2_desired_level_8_3	0xA1C4
  5218. -#define	dagc2_desired_level_8_3_pos 0
  5219. -#define	dagc2_desired_level_8_3_len 6
  5220. -#define	dagc2_desired_level_8_3_lsb 3
  5221. -#define xd_p_dagc2_apply_delay	0xA1C5
  5222. -#define	dagc2_apply_delay_pos 0
  5223. -#define	dagc2_apply_delay_len 7
  5224. -#define	dagc2_apply_delay_lsb 0
  5225. -#define xd_p_dagc2_bypass_scale_ctl	0xA1C6
  5226. -#define	dagc2_bypass_scale_ctl_pos 0
  5227. -#define	dagc2_bypass_scale_ctl_len 3
  5228. -#define	dagc2_bypass_scale_ctl_lsb 0
  5229. -#define xd_p_dagc2_programmable_shift1	0xA1C7
  5230. -#define	dagc2_programmable_shift1_pos 0
  5231. -#define	dagc2_programmable_shift1_len 8
  5232. -#define	dagc2_programmable_shift1_lsb 0
  5233. -#define xd_p_dagc2_programmable_shift2	0xA1C8
  5234. -#define	dagc2_programmable_shift2_pos 0
  5235. -#define	dagc2_programmable_shift2_len 8
  5236. -#define	dagc2_programmable_shift2_lsb 0
  5237. -#define xd_p_reg_dagc2_in_sat_cnt_7_0	0xA1C9
  5238. -#define	reg_dagc2_in_sat_cnt_7_0_pos 0
  5239. -#define	reg_dagc2_in_sat_cnt_7_0_len 8
  5240. -#define	reg_dagc2_in_sat_cnt_7_0_lsb 0
  5241. -#define xd_p_reg_dagc2_in_sat_cnt_15_8	0xA1CA
  5242. -#define	reg_dagc2_in_sat_cnt_15_8_pos 0
  5243. -#define	reg_dagc2_in_sat_cnt_15_8_len 8
  5244. -#define	reg_dagc2_in_sat_cnt_15_8_lsb 8
  5245. -#define xd_p_reg_dagc2_in_sat_cnt_23_16	0xA1CB
  5246. -#define	reg_dagc2_in_sat_cnt_23_16_pos 0
  5247. -#define	reg_dagc2_in_sat_cnt_23_16_len 8
  5248. -#define	reg_dagc2_in_sat_cnt_23_16_lsb 16
  5249. -#define xd_p_reg_dagc2_in_sat_cnt_31_24	0xA1CC
  5250. -#define	reg_dagc2_in_sat_cnt_31_24_pos 0
  5251. -#define	reg_dagc2_in_sat_cnt_31_24_len 8
  5252. -#define	reg_dagc2_in_sat_cnt_31_24_lsb 24
  5253. -#define xd_p_reg_dagc2_out_sat_cnt_7_0	0xA1CD
  5254. -#define	reg_dagc2_out_sat_cnt_7_0_pos 0
  5255. -#define	reg_dagc2_out_sat_cnt_7_0_len 8
  5256. -#define	reg_dagc2_out_sat_cnt_7_0_lsb 0
  5257. -#define xd_p_reg_dagc2_out_sat_cnt_15_8	0xA1CE
  5258. -#define	reg_dagc2_out_sat_cnt_15_8_pos 0
  5259. -#define	reg_dagc2_out_sat_cnt_15_8_len 8
  5260. -#define	reg_dagc2_out_sat_cnt_15_8_lsb 8
  5261. -#define xd_p_reg_dagc2_out_sat_cnt_23_16	0xA1CF
  5262. -#define	reg_dagc2_out_sat_cnt_23_16_pos 0
  5263. -#define	reg_dagc2_out_sat_cnt_23_16_len 8
  5264. -#define	reg_dagc2_out_sat_cnt_23_16_lsb 16
  5265. -#define xd_p_reg_dagc2_out_sat_cnt_31_24	0xA1D0
  5266. -#define	reg_dagc2_out_sat_cnt_31_24_pos 0
  5267. -#define	reg_dagc2_out_sat_cnt_31_24_len 8
  5268. -#define	reg_dagc2_out_sat_cnt_31_24_lsb 24
  5269. -#define xd_r_dagc2_multiplier_7_0	0xA1D6
  5270. -#define	dagc2_multiplier_7_0_pos 0
  5271. -#define	dagc2_multiplier_7_0_len 8
  5272. -#define	dagc2_multiplier_7_0_lsb 0
  5273. -#define xd_r_dagc2_multiplier_15_8	0xA1D7
  5274. -#define	dagc2_multiplier_15_8_pos 0
  5275. -#define	dagc2_multiplier_15_8_len 8
  5276. -#define	dagc2_multiplier_15_8_lsb 8
  5277. -#define xd_r_dagc2_right_shift_bits	0xA1D8
  5278. -#define	dagc2_right_shift_bits_pos 0
  5279. -#define	dagc2_right_shift_bits_len 4
  5280. -#define	dagc2_right_shift_bits_lsb 0
  5281. -#define xd_p_cfoe_NS_coeff1_7_0	0xA200
  5282. -#define	cfoe_NS_coeff1_7_0_pos 0
  5283. -#define	cfoe_NS_coeff1_7_0_len 8
  5284. -#define	cfoe_NS_coeff1_7_0_lsb 0
  5285. -#define xd_p_cfoe_NS_coeff1_15_8	0xA201
  5286. -#define	cfoe_NS_coeff1_15_8_pos 0
  5287. -#define	cfoe_NS_coeff1_15_8_len 8
  5288. -#define	cfoe_NS_coeff1_15_8_lsb 8
  5289. -#define xd_p_cfoe_NS_coeff1_23_16	0xA202
  5290. -#define	cfoe_NS_coeff1_23_16_pos 0
  5291. -#define	cfoe_NS_coeff1_23_16_len 8
  5292. -#define	cfoe_NS_coeff1_23_16_lsb 16
  5293. -#define xd_p_cfoe_NS_coeff1_25_24	0xA203
  5294. -#define	cfoe_NS_coeff1_25_24_pos 0
  5295. -#define	cfoe_NS_coeff1_25_24_len 2
  5296. -#define	cfoe_NS_coeff1_25_24_lsb 24
  5297. -#define xd_p_cfoe_NS_coeff2_5_0	0xA203
  5298. -#define	cfoe_NS_coeff2_5_0_pos 2
  5299. -#define	cfoe_NS_coeff2_5_0_len 6
  5300. -#define	cfoe_NS_coeff2_5_0_lsb 0
  5301. -#define xd_p_cfoe_NS_coeff2_13_6	0xA204
  5302. -#define	cfoe_NS_coeff2_13_6_pos 0
  5303. -#define	cfoe_NS_coeff2_13_6_len 8
  5304. -#define	cfoe_NS_coeff2_13_6_lsb 6
  5305. -#define xd_p_cfoe_NS_coeff2_21_14	0xA205
  5306. -#define	cfoe_NS_coeff2_21_14_pos 0
  5307. -#define	cfoe_NS_coeff2_21_14_len 8
  5308. -#define	cfoe_NS_coeff2_21_14_lsb 14
  5309. -#define xd_p_cfoe_NS_coeff2_24_22	0xA206
  5310. -#define	cfoe_NS_coeff2_24_22_pos 0
  5311. -#define	cfoe_NS_coeff2_24_22_len 3
  5312. -#define	cfoe_NS_coeff2_24_22_lsb 22
  5313. -#define xd_p_cfoe_lf_c1_4_0	0xA206
  5314. -#define	cfoe_lf_c1_4_0_pos 3
  5315. -#define	cfoe_lf_c1_4_0_len 5
  5316. -#define	cfoe_lf_c1_4_0_lsb 0
  5317. -#define xd_p_cfoe_lf_c1_12_5	0xA207
  5318. -#define	cfoe_lf_c1_12_5_pos 0
  5319. -#define	cfoe_lf_c1_12_5_len 8
  5320. -#define	cfoe_lf_c1_12_5_lsb 5
  5321. -#define xd_p_cfoe_lf_c1_20_13	0xA208
  5322. -#define	cfoe_lf_c1_20_13_pos 0
  5323. -#define	cfoe_lf_c1_20_13_len 8
  5324. -#define	cfoe_lf_c1_20_13_lsb 13
  5325. -#define xd_p_cfoe_lf_c1_25_21	0xA209
  5326. -#define	cfoe_lf_c1_25_21_pos 0
  5327. -#define	cfoe_lf_c1_25_21_len 5
  5328. -#define	cfoe_lf_c1_25_21_lsb 21
  5329. -#define xd_p_cfoe_lf_c2_2_0	0xA209
  5330. -#define	cfoe_lf_c2_2_0_pos 5
  5331. -#define	cfoe_lf_c2_2_0_len 3
  5332. -#define	cfoe_lf_c2_2_0_lsb 0
  5333. -#define xd_p_cfoe_lf_c2_10_3	0xA20A
  5334. -#define	cfoe_lf_c2_10_3_pos 0
  5335. -#define	cfoe_lf_c2_10_3_len 8
  5336. -#define	cfoe_lf_c2_10_3_lsb 3
  5337. -#define xd_p_cfoe_lf_c2_18_11	0xA20B
  5338. -#define	cfoe_lf_c2_18_11_pos 0
  5339. -#define	cfoe_lf_c2_18_11_len 8
  5340. -#define	cfoe_lf_c2_18_11_lsb 11
  5341. -#define xd_p_cfoe_lf_c2_25_19	0xA20C
  5342. -#define	cfoe_lf_c2_25_19_pos 0
  5343. -#define	cfoe_lf_c2_25_19_len 7
  5344. -#define	cfoe_lf_c2_25_19_lsb 19
  5345. -#define xd_p_cfoe_ifod_7_0	0xA20D
  5346. -#define	cfoe_ifod_7_0_pos 0
  5347. -#define	cfoe_ifod_7_0_len 8
  5348. -#define	cfoe_ifod_7_0_lsb 0
  5349. -#define xd_p_cfoe_ifod_10_8	0xA20E
  5350. -#define	cfoe_ifod_10_8_pos 0
  5351. -#define	cfoe_ifod_10_8_len 3
  5352. -#define	cfoe_ifod_10_8_lsb 8
  5353. -#define xd_p_cfoe_Divg_ctr_th	0xA20E
  5354. -#define	cfoe_Divg_ctr_th_pos 4
  5355. -#define	cfoe_Divg_ctr_th_len 4
  5356. -#define	cfoe_Divg_ctr_th_lsb 0
  5357. -#define xd_p_cfoe_FOT_divg_th	0xA20F
  5358. -#define	cfoe_FOT_divg_th_pos 0
  5359. -#define	cfoe_FOT_divg_th_len 8
  5360. -#define	cfoe_FOT_divg_th_lsb 0
  5361. -#define xd_p_cfoe_FOT_cnvg_th	0xA210
  5362. -#define	cfoe_FOT_cnvg_th_pos 0
  5363. -#define	cfoe_FOT_cnvg_th_len 8
  5364. -#define	cfoe_FOT_cnvg_th_lsb 0
  5365. -#define xd_p_reg_cfoe_offset_7_0	0xA211
  5366. -#define	reg_cfoe_offset_7_0_pos 0
  5367. -#define	reg_cfoe_offset_7_0_len 8
  5368. -#define	reg_cfoe_offset_7_0_lsb 0
  5369. -#define xd_p_reg_cfoe_offset_9_8	0xA212
  5370. -#define	reg_cfoe_offset_9_8_pos 0
  5371. -#define	reg_cfoe_offset_9_8_len 2
  5372. -#define	reg_cfoe_offset_9_8_lsb 8
  5373. -#define xd_p_reg_cfoe_ifoe_sign_corr	0xA212
  5374. -#define	reg_cfoe_ifoe_sign_corr_pos 2
  5375. -#define	reg_cfoe_ifoe_sign_corr_len 1
  5376. -#define	reg_cfoe_ifoe_sign_corr_lsb 0
  5377. -#define xd_r_cfoe_fot_LF_output_7_0	0xA218
  5378. -#define	cfoe_fot_LF_output_7_0_pos 0
  5379. -#define	cfoe_fot_LF_output_7_0_len 8
  5380. -#define	cfoe_fot_LF_output_7_0_lsb 0
  5381. -#define xd_r_cfoe_fot_LF_output_15_8	0xA219
  5382. -#define	cfoe_fot_LF_output_15_8_pos 0
  5383. -#define	cfoe_fot_LF_output_15_8_len 8
  5384. -#define	cfoe_fot_LF_output_15_8_lsb 8
  5385. -#define xd_r_cfoe_ifo_metric_7_0	0xA21A
  5386. -#define	cfoe_ifo_metric_7_0_pos 0
  5387. -#define	cfoe_ifo_metric_7_0_len 8
  5388. -#define	cfoe_ifo_metric_7_0_lsb 0
  5389. -#define xd_r_cfoe_ifo_metric_15_8	0xA21B
  5390. -#define	cfoe_ifo_metric_15_8_pos 0
  5391. -#define	cfoe_ifo_metric_15_8_len 8
  5392. -#define	cfoe_ifo_metric_15_8_lsb 8
  5393. -#define xd_r_cfoe_ifo_metric_23_16	0xA21C
  5394. -#define	cfoe_ifo_metric_23_16_pos 0
  5395. -#define	cfoe_ifo_metric_23_16_len 8
  5396. -#define	cfoe_ifo_metric_23_16_lsb 16
  5397. -#define xd_p_ste_Nu	0xA220
  5398. -#define	ste_Nu_pos 0
  5399. -#define	ste_Nu_len 2
  5400. -#define	ste_Nu_lsb 0
  5401. -#define xd_p_ste_GI	0xA220
  5402. -#define	ste_GI_pos 2
  5403. -#define	ste_GI_len 3
  5404. -#define	ste_GI_lsb 0
  5405. -#define xd_p_ste_symbol_num	0xA221
  5406. -#define	ste_symbol_num_pos 0
  5407. -#define	ste_symbol_num_len 2
  5408. -#define	ste_symbol_num_lsb 0
  5409. -#define xd_p_ste_sample_num	0xA221
  5410. -#define	ste_sample_num_pos 2
  5411. -#define	ste_sample_num_len 2
  5412. -#define	ste_sample_num_lsb 0
  5413. -#define xd_p_reg_ste_buf_en	0xA221
  5414. -#define	reg_ste_buf_en_pos 7
  5415. -#define	reg_ste_buf_en_len 1
  5416. -#define	reg_ste_buf_en_lsb 0
  5417. -#define xd_p_ste_FFT_offset_7_0	0xA222
  5418. -#define	ste_FFT_offset_7_0_pos 0
  5419. -#define	ste_FFT_offset_7_0_len 8
  5420. -#define	ste_FFT_offset_7_0_lsb 0
  5421. -#define xd_p_ste_FFT_offset_11_8	0xA223
  5422. -#define	ste_FFT_offset_11_8_pos 0
  5423. -#define	ste_FFT_offset_11_8_len 4
  5424. -#define	ste_FFT_offset_11_8_lsb 8
  5425. -#define xd_p_reg_ste_tstmod	0xA223
  5426. -#define	reg_ste_tstmod_pos 5
  5427. -#define	reg_ste_tstmod_len 1
  5428. -#define	reg_ste_tstmod_lsb 0
  5429. -#define xd_p_ste_adv_start_7_0	0xA224
  5430. -#define	ste_adv_start_7_0_pos 0
  5431. -#define	ste_adv_start_7_0_len 8
  5432. -#define	ste_adv_start_7_0_lsb 0
  5433. -#define xd_p_ste_adv_start_10_8	0xA225
  5434. -#define	ste_adv_start_10_8_pos 0
  5435. -#define	ste_adv_start_10_8_len 3
  5436. -#define	ste_adv_start_10_8_lsb 8
  5437. -#define xd_p_ste_adv_stop	0xA226
  5438. -#define	ste_adv_stop_pos 0
  5439. -#define	ste_adv_stop_len 8
  5440. -#define	ste_adv_stop_lsb 0
  5441. -#define xd_r_ste_P_value_7_0	0xA228
  5442. -#define	ste_P_value_7_0_pos 0
  5443. -#define	ste_P_value_7_0_len 8
  5444. -#define	ste_P_value_7_0_lsb 0
  5445. -#define xd_r_ste_P_value_10_8	0xA229
  5446. -#define	ste_P_value_10_8_pos 0
  5447. -#define	ste_P_value_10_8_len 3
  5448. -#define	ste_P_value_10_8_lsb 8
  5449. -#define xd_r_ste_M_value_7_0	0xA22A
  5450. -#define	ste_M_value_7_0_pos 0
  5451. -#define	ste_M_value_7_0_len 8
  5452. -#define	ste_M_value_7_0_lsb 0
  5453. -#define xd_r_ste_M_value_10_8	0xA22B
  5454. -#define	ste_M_value_10_8_pos 0
  5455. -#define	ste_M_value_10_8_len 3
  5456. -#define	ste_M_value_10_8_lsb 8
  5457. -#define xd_r_ste_H1	0xA22C
  5458. -#define	ste_H1_pos 0
  5459. -#define	ste_H1_len 7
  5460. -#define	ste_H1_lsb 0
  5461. -#define xd_r_ste_H2	0xA22D
  5462. -#define	ste_H2_pos 0
  5463. -#define	ste_H2_len 7
  5464. -#define	ste_H2_lsb 0
  5465. -#define xd_r_ste_H3	0xA22E
  5466. -#define	ste_H3_pos 0
  5467. -#define	ste_H3_len 7
  5468. -#define	ste_H3_lsb 0
  5469. -#define xd_r_ste_H4	0xA22F
  5470. -#define	ste_H4_pos 0
  5471. -#define	ste_H4_len 7
  5472. -#define	ste_H4_lsb 0
  5473. -#define xd_r_ste_Corr_value_I_7_0	0xA230
  5474. -#define	ste_Corr_value_I_7_0_pos 0
  5475. -#define	ste_Corr_value_I_7_0_len 8
  5476. -#define	ste_Corr_value_I_7_0_lsb 0
  5477. -#define xd_r_ste_Corr_value_I_15_8	0xA231
  5478. -#define	ste_Corr_value_I_15_8_pos 0
  5479. -#define	ste_Corr_value_I_15_8_len 8
  5480. -#define	ste_Corr_value_I_15_8_lsb 8
  5481. -#define xd_r_ste_Corr_value_I_23_16	0xA232
  5482. -#define	ste_Corr_value_I_23_16_pos 0
  5483. -#define	ste_Corr_value_I_23_16_len 8
  5484. -#define	ste_Corr_value_I_23_16_lsb 16
  5485. -#define xd_r_ste_Corr_value_I_27_24	0xA233
  5486. -#define	ste_Corr_value_I_27_24_pos 0
  5487. -#define	ste_Corr_value_I_27_24_len 4
  5488. -#define	ste_Corr_value_I_27_24_lsb 24
  5489. -#define xd_r_ste_Corr_value_Q_7_0	0xA234
  5490. -#define	ste_Corr_value_Q_7_0_pos 0
  5491. -#define	ste_Corr_value_Q_7_0_len 8
  5492. -#define	ste_Corr_value_Q_7_0_lsb 0
  5493. -#define xd_r_ste_Corr_value_Q_15_8	0xA235
  5494. -#define	ste_Corr_value_Q_15_8_pos 0
  5495. -#define	ste_Corr_value_Q_15_8_len 8
  5496. -#define	ste_Corr_value_Q_15_8_lsb 8
  5497. -#define xd_r_ste_Corr_value_Q_23_16	0xA236
  5498. -#define	ste_Corr_value_Q_23_16_pos 0
  5499. -#define	ste_Corr_value_Q_23_16_len 8
  5500. -#define	ste_Corr_value_Q_23_16_lsb 16
  5501. -#define xd_r_ste_Corr_value_Q_27_24	0xA237
  5502. -#define	ste_Corr_value_Q_27_24_pos 0
  5503. -#define	ste_Corr_value_Q_27_24_len 4
  5504. -#define	ste_Corr_value_Q_27_24_lsb 24
  5505. -#define xd_r_ste_J_num_7_0	0xA238
  5506. -#define	ste_J_num_7_0_pos 0
  5507. -#define	ste_J_num_7_0_len 8
  5508. -#define	ste_J_num_7_0_lsb 0
  5509. -#define xd_r_ste_J_num_15_8	0xA239
  5510. -#define	ste_J_num_15_8_pos 0
  5511. -#define	ste_J_num_15_8_len 8
  5512. -#define	ste_J_num_15_8_lsb 8
  5513. -#define xd_r_ste_J_num_23_16	0xA23A
  5514. -#define	ste_J_num_23_16_pos 0
  5515. -#define	ste_J_num_23_16_len 8
  5516. -#define	ste_J_num_23_16_lsb 16
  5517. -#define xd_r_ste_J_num_31_24	0xA23B
  5518. -#define	ste_J_num_31_24_pos 0
  5519. -#define	ste_J_num_31_24_len 8
  5520. -#define	ste_J_num_31_24_lsb 24
  5521. -#define xd_r_ste_J_den_7_0	0xA23C
  5522. -#define	ste_J_den_7_0_pos 0
  5523. -#define	ste_J_den_7_0_len 8
  5524. -#define	ste_J_den_7_0_lsb 0
  5525. -#define xd_r_ste_J_den_15_8	0xA23D
  5526. -#define	ste_J_den_15_8_pos 0
  5527. -#define	ste_J_den_15_8_len 8
  5528. -#define	ste_J_den_15_8_lsb 8
  5529. -#define xd_r_ste_J_den_18_16	0xA23E
  5530. -#define	ste_J_den_18_16_pos 0
  5531. -#define	ste_J_den_18_16_len 3
  5532. -#define	ste_J_den_18_16_lsb 16
  5533. -#define xd_r_ste_Beacon_Indicator	0xA23E
  5534. -#define	ste_Beacon_Indicator_pos 4
  5535. -#define	ste_Beacon_Indicator_len 1
  5536. -#define	ste_Beacon_Indicator_lsb 0
  5537. -#define xd_r_tpsd_Frame_Num	0xA250
  5538. -#define	tpsd_Frame_Num_pos 0
  5539. -#define	tpsd_Frame_Num_len 2
  5540. -#define	tpsd_Frame_Num_lsb 0
  5541. -#define xd_r_tpsd_Constel	0xA250
  5542. -#define	tpsd_Constel_pos 2
  5543. -#define	tpsd_Constel_len 2
  5544. -#define	tpsd_Constel_lsb 0
  5545. -#define xd_r_tpsd_GI	0xA250
  5546. -#define	tpsd_GI_pos 4
  5547. -#define	tpsd_GI_len 2
  5548. -#define	tpsd_GI_lsb 0
  5549. -#define xd_r_tpsd_Mode	0xA250
  5550. -#define	tpsd_Mode_pos 6
  5551. -#define	tpsd_Mode_len 2
  5552. -#define	tpsd_Mode_lsb 0
  5553. -#define xd_r_tpsd_CR_HP	0xA251
  5554. -#define	tpsd_CR_HP_pos 0
  5555. -#define	tpsd_CR_HP_len 3
  5556. -#define	tpsd_CR_HP_lsb 0
  5557. -#define xd_r_tpsd_CR_LP	0xA251
  5558. -#define	tpsd_CR_LP_pos 3
  5559. -#define	tpsd_CR_LP_len 3
  5560. -#define	tpsd_CR_LP_lsb 0
  5561. -#define xd_r_tpsd_Hie	0xA252
  5562. -#define	tpsd_Hie_pos 0
  5563. -#define	tpsd_Hie_len 3
  5564. -#define	tpsd_Hie_lsb 0
  5565. -#define xd_r_tpsd_Res_Bits	0xA252
  5566. -#define	tpsd_Res_Bits_pos 3
  5567. -#define	tpsd_Res_Bits_len 5
  5568. -#define	tpsd_Res_Bits_lsb 0
  5569. -#define xd_r_tpsd_Res_Bits_0	0xA253
  5570. -#define	tpsd_Res_Bits_0_pos 0
  5571. -#define	tpsd_Res_Bits_0_len 1
  5572. -#define	tpsd_Res_Bits_0_lsb 0
  5573. -#define xd_r_tpsd_LengthInd	0xA253
  5574. -#define	tpsd_LengthInd_pos 1
  5575. -#define	tpsd_LengthInd_len 6
  5576. -#define	tpsd_LengthInd_lsb 0
  5577. -#define xd_r_tpsd_Cell_Id_7_0	0xA254
  5578. -#define	tpsd_Cell_Id_7_0_pos 0
  5579. -#define	tpsd_Cell_Id_7_0_len 8
  5580. -#define	tpsd_Cell_Id_7_0_lsb 0
  5581. -#define xd_r_tpsd_Cell_Id_15_8	0xA255
  5582. -#define	tpsd_Cell_Id_15_8_pos 0
  5583. -#define	tpsd_Cell_Id_15_8_len 8
  5584. -#define	tpsd_Cell_Id_15_8_lsb 0
  5585. -#define xd_p_reg_fft_mask_tone0_7_0	0xA260
  5586. -#define	reg_fft_mask_tone0_7_0_pos 0
  5587. -#define	reg_fft_mask_tone0_7_0_len 8
  5588. -#define	reg_fft_mask_tone0_7_0_lsb 0
  5589. -#define xd_p_reg_fft_mask_tone0_12_8	0xA261
  5590. -#define	reg_fft_mask_tone0_12_8_pos 0
  5591. -#define	reg_fft_mask_tone0_12_8_len 5
  5592. -#define	reg_fft_mask_tone0_12_8_lsb 8
  5593. -#define xd_p_reg_fft_mask_tone1_7_0	0xA262
  5594. -#define	reg_fft_mask_tone1_7_0_pos 0
  5595. -#define	reg_fft_mask_tone1_7_0_len 8
  5596. -#define	reg_fft_mask_tone1_7_0_lsb 0
  5597. -#define xd_p_reg_fft_mask_tone1_12_8	0xA263
  5598. -#define	reg_fft_mask_tone1_12_8_pos 0
  5599. -#define	reg_fft_mask_tone1_12_8_len 5
  5600. -#define	reg_fft_mask_tone1_12_8_lsb 8
  5601. -#define xd_p_reg_fft_mask_tone2_7_0	0xA264
  5602. -#define	reg_fft_mask_tone2_7_0_pos 0
  5603. -#define	reg_fft_mask_tone2_7_0_len 8
  5604. -#define	reg_fft_mask_tone2_7_0_lsb 0
  5605. -#define xd_p_reg_fft_mask_tone2_12_8	0xA265
  5606. -#define	reg_fft_mask_tone2_12_8_pos 0
  5607. -#define	reg_fft_mask_tone2_12_8_len 5
  5608. -#define	reg_fft_mask_tone2_12_8_lsb 8
  5609. -#define xd_p_reg_fft_mask_tone3_7_0	0xA266
  5610. -#define	reg_fft_mask_tone3_7_0_pos 0
  5611. -#define	reg_fft_mask_tone3_7_0_len 8
  5612. -#define	reg_fft_mask_tone3_7_0_lsb 0
  5613. -#define xd_p_reg_fft_mask_tone3_12_8	0xA267
  5614. -#define	reg_fft_mask_tone3_12_8_pos 0
  5615. -#define	reg_fft_mask_tone3_12_8_len 5
  5616. -#define	reg_fft_mask_tone3_12_8_lsb 8
  5617. -#define xd_p_reg_fft_mask_from0_7_0	0xA268
  5618. -#define	reg_fft_mask_from0_7_0_pos 0
  5619. -#define	reg_fft_mask_from0_7_0_len 8
  5620. -#define	reg_fft_mask_from0_7_0_lsb 0
  5621. -#define xd_p_reg_fft_mask_from0_12_8	0xA269
  5622. -#define	reg_fft_mask_from0_12_8_pos 0
  5623. -#define	reg_fft_mask_from0_12_8_len 5
  5624. -#define	reg_fft_mask_from0_12_8_lsb 8
  5625. -#define xd_p_reg_fft_mask_to0_7_0	0xA26A
  5626. -#define	reg_fft_mask_to0_7_0_pos 0
  5627. -#define	reg_fft_mask_to0_7_0_len 8
  5628. -#define	reg_fft_mask_to0_7_0_lsb 0
  5629. -#define xd_p_reg_fft_mask_to0_12_8	0xA26B
  5630. -#define	reg_fft_mask_to0_12_8_pos 0
  5631. -#define	reg_fft_mask_to0_12_8_len 5
  5632. -#define	reg_fft_mask_to0_12_8_lsb 8
  5633. -#define xd_p_reg_fft_mask_from1_7_0	0xA26C
  5634. -#define	reg_fft_mask_from1_7_0_pos 0
  5635. -#define	reg_fft_mask_from1_7_0_len 8
  5636. -#define	reg_fft_mask_from1_7_0_lsb 0
  5637. -#define xd_p_reg_fft_mask_from1_12_8	0xA26D
  5638. -#define	reg_fft_mask_from1_12_8_pos 0
  5639. -#define	reg_fft_mask_from1_12_8_len 5
  5640. -#define	reg_fft_mask_from1_12_8_lsb 8
  5641. -#define xd_p_reg_fft_mask_to1_7_0	0xA26E
  5642. -#define	reg_fft_mask_to1_7_0_pos 0
  5643. -#define	reg_fft_mask_to1_7_0_len 8
  5644. -#define	reg_fft_mask_to1_7_0_lsb 0
  5645. -#define xd_p_reg_fft_mask_to1_12_8	0xA26F
  5646. -#define	reg_fft_mask_to1_12_8_pos 0
  5647. -#define	reg_fft_mask_to1_12_8_len 5
  5648. -#define	reg_fft_mask_to1_12_8_lsb 8
  5649. -#define xd_p_reg_cge_idx0_7_0	0xA280
  5650. -#define	reg_cge_idx0_7_0_pos 0
  5651. -#define	reg_cge_idx0_7_0_len 8
  5652. -#define	reg_cge_idx0_7_0_lsb 0
  5653. -#define xd_p_reg_cge_idx0_12_8	0xA281
  5654. -#define	reg_cge_idx0_12_8_pos 0
  5655. -#define	reg_cge_idx0_12_8_len 5
  5656. -#define	reg_cge_idx0_12_8_lsb 8
  5657. -#define xd_p_reg_cge_idx1_7_0	0xA282
  5658. -#define	reg_cge_idx1_7_0_pos 0
  5659. -#define	reg_cge_idx1_7_0_len 8
  5660. -#define	reg_cge_idx1_7_0_lsb 0
  5661. -#define xd_p_reg_cge_idx1_12_8	0xA283
  5662. -#define	reg_cge_idx1_12_8_pos 0
  5663. -#define	reg_cge_idx1_12_8_len 5
  5664. -#define	reg_cge_idx1_12_8_lsb 8
  5665. -#define xd_p_reg_cge_idx2_7_0	0xA284
  5666. -#define	reg_cge_idx2_7_0_pos 0
  5667. -#define	reg_cge_idx2_7_0_len 8
  5668. -#define	reg_cge_idx2_7_0_lsb 0
  5669. -#define xd_p_reg_cge_idx2_12_8	0xA285
  5670. -#define	reg_cge_idx2_12_8_pos 0
  5671. -#define	reg_cge_idx2_12_8_len 5
  5672. -#define	reg_cge_idx2_12_8_lsb 8
  5673. -#define xd_p_reg_cge_idx3_7_0	0xA286
  5674. -#define	reg_cge_idx3_7_0_pos 0
  5675. -#define	reg_cge_idx3_7_0_len 8
  5676. -#define	reg_cge_idx3_7_0_lsb 0
  5677. -#define xd_p_reg_cge_idx3_12_8	0xA287
  5678. -#define	reg_cge_idx3_12_8_pos 0
  5679. -#define	reg_cge_idx3_12_8_len 5
  5680. -#define	reg_cge_idx3_12_8_lsb 8
  5681. -#define xd_p_reg_cge_idx4_7_0	0xA288
  5682. -#define	reg_cge_idx4_7_0_pos 0
  5683. -#define	reg_cge_idx4_7_0_len 8
  5684. -#define	reg_cge_idx4_7_0_lsb 0
  5685. -#define xd_p_reg_cge_idx4_12_8	0xA289
  5686. -#define	reg_cge_idx4_12_8_pos 0
  5687. -#define	reg_cge_idx4_12_8_len 5
  5688. -#define	reg_cge_idx4_12_8_lsb 8
  5689. -#define xd_p_reg_cge_idx5_7_0	0xA28A
  5690. -#define	reg_cge_idx5_7_0_pos 0
  5691. -#define	reg_cge_idx5_7_0_len 8
  5692. -#define	reg_cge_idx5_7_0_lsb 0
  5693. -#define xd_p_reg_cge_idx5_12_8	0xA28B
  5694. -#define	reg_cge_idx5_12_8_pos 0
  5695. -#define	reg_cge_idx5_12_8_len 5
  5696. -#define	reg_cge_idx5_12_8_lsb 8
  5697. -#define xd_p_reg_cge_idx6_7_0	0xA28C
  5698. -#define	reg_cge_idx6_7_0_pos 0
  5699. -#define	reg_cge_idx6_7_0_len 8
  5700. -#define	reg_cge_idx6_7_0_lsb 0
  5701. -#define xd_p_reg_cge_idx6_12_8	0xA28D
  5702. -#define	reg_cge_idx6_12_8_pos 0
  5703. -#define	reg_cge_idx6_12_8_len 5
  5704. -#define	reg_cge_idx6_12_8_lsb 8
  5705. -#define xd_p_reg_cge_idx7_7_0	0xA28E
  5706. -#define	reg_cge_idx7_7_0_pos 0
  5707. -#define	reg_cge_idx7_7_0_len 8
  5708. -#define	reg_cge_idx7_7_0_lsb 0
  5709. -#define xd_p_reg_cge_idx7_12_8	0xA28F
  5710. -#define	reg_cge_idx7_12_8_pos 0
  5711. -#define	reg_cge_idx7_12_8_len 5
  5712. -#define	reg_cge_idx7_12_8_lsb 8
  5713. -#define xd_p_reg_cge_idx8_7_0	0xA290
  5714. -#define	reg_cge_idx8_7_0_pos 0
  5715. -#define	reg_cge_idx8_7_0_len 8
  5716. -#define	reg_cge_idx8_7_0_lsb 0
  5717. -#define xd_p_reg_cge_idx8_12_8	0xA291
  5718. -#define	reg_cge_idx8_12_8_pos 0
  5719. -#define	reg_cge_idx8_12_8_len 5
  5720. -#define	reg_cge_idx8_12_8_lsb 8
  5721. -#define xd_p_reg_cge_idx9_7_0	0xA292
  5722. -#define	reg_cge_idx9_7_0_pos 0
  5723. -#define	reg_cge_idx9_7_0_len 8
  5724. -#define	reg_cge_idx9_7_0_lsb 0
  5725. -#define xd_p_reg_cge_idx9_12_8	0xA293
  5726. -#define	reg_cge_idx9_12_8_pos 0
  5727. -#define	reg_cge_idx9_12_8_len 5
  5728. -#define	reg_cge_idx9_12_8_lsb 8
  5729. -#define xd_p_reg_cge_idx10_7_0	0xA294
  5730. -#define	reg_cge_idx10_7_0_pos 0
  5731. -#define	reg_cge_idx10_7_0_len 8
  5732. -#define	reg_cge_idx10_7_0_lsb 0
  5733. -#define xd_p_reg_cge_idx10_12_8	0xA295
  5734. -#define	reg_cge_idx10_12_8_pos 0
  5735. -#define	reg_cge_idx10_12_8_len 5
  5736. -#define	reg_cge_idx10_12_8_lsb 8
  5737. -#define xd_p_reg_cge_idx11_7_0	0xA296
  5738. -#define	reg_cge_idx11_7_0_pos 0
  5739. -#define	reg_cge_idx11_7_0_len 8
  5740. -#define	reg_cge_idx11_7_0_lsb 0
  5741. -#define xd_p_reg_cge_idx11_12_8	0xA297
  5742. -#define	reg_cge_idx11_12_8_pos 0
  5743. -#define	reg_cge_idx11_12_8_len 5
  5744. -#define	reg_cge_idx11_12_8_lsb 8
  5745. -#define xd_p_reg_cge_idx12_7_0	0xA298
  5746. -#define	reg_cge_idx12_7_0_pos 0
  5747. -#define	reg_cge_idx12_7_0_len 8
  5748. -#define	reg_cge_idx12_7_0_lsb 0
  5749. -#define xd_p_reg_cge_idx12_12_8	0xA299
  5750. -#define	reg_cge_idx12_12_8_pos 0
  5751. -#define	reg_cge_idx12_12_8_len 5
  5752. -#define	reg_cge_idx12_12_8_lsb 8
  5753. -#define xd_p_reg_cge_idx13_7_0	0xA29A
  5754. -#define	reg_cge_idx13_7_0_pos 0
  5755. -#define	reg_cge_idx13_7_0_len 8
  5756. -#define	reg_cge_idx13_7_0_lsb 0
  5757. -#define xd_p_reg_cge_idx13_12_8	0xA29B
  5758. -#define	reg_cge_idx13_12_8_pos 0
  5759. -#define	reg_cge_idx13_12_8_len 5
  5760. -#define	reg_cge_idx13_12_8_lsb 8
  5761. -#define xd_p_reg_cge_idx14_7_0	0xA29C
  5762. -#define	reg_cge_idx14_7_0_pos 0
  5763. -#define	reg_cge_idx14_7_0_len 8
  5764. -#define	reg_cge_idx14_7_0_lsb 0
  5765. -#define xd_p_reg_cge_idx14_12_8	0xA29D
  5766. -#define	reg_cge_idx14_12_8_pos 0
  5767. -#define	reg_cge_idx14_12_8_len 5
  5768. -#define	reg_cge_idx14_12_8_lsb 8
  5769. -#define xd_p_reg_cge_idx15_7_0	0xA29E
  5770. -#define	reg_cge_idx15_7_0_pos 0
  5771. -#define	reg_cge_idx15_7_0_len 8
  5772. -#define	reg_cge_idx15_7_0_lsb 0
  5773. -#define xd_p_reg_cge_idx15_12_8	0xA29F
  5774. -#define	reg_cge_idx15_12_8_pos 0
  5775. -#define	reg_cge_idx15_12_8_len 5
  5776. -#define	reg_cge_idx15_12_8_lsb 8
  5777. -#define xd_r_reg_fft_crc	0xA2A8
  5778. -#define	reg_fft_crc_pos 0
  5779. -#define	reg_fft_crc_len 8
  5780. -#define	reg_fft_crc_lsb 0
  5781. -#define xd_p_fd_fft_shift_max	0xA2A9
  5782. -#define	fd_fft_shift_max_pos 0
  5783. -#define	fd_fft_shift_max_len 4
  5784. -#define	fd_fft_shift_max_lsb 0
  5785. -#define xd_r_fd_fft_shift	0xA2A9
  5786. -#define	fd_fft_shift_pos 4
  5787. -#define	fd_fft_shift_len 4
  5788. -#define	fd_fft_shift_lsb 0
  5789. -#define xd_r_fd_fft_frame_num	0xA2AA
  5790. -#define	fd_fft_frame_num_pos 0
  5791. -#define	fd_fft_frame_num_len 2
  5792. -#define	fd_fft_frame_num_lsb 0
  5793. -#define xd_r_fd_fft_symbol_count	0xA2AB
  5794. -#define	fd_fft_symbol_count_pos 0
  5795. -#define	fd_fft_symbol_count_len 7
  5796. -#define	fd_fft_symbol_count_lsb 0
  5797. -#define xd_r_reg_fft_idx_max_7_0	0xA2AC
  5798. -#define	reg_fft_idx_max_7_0_pos 0
  5799. -#define	reg_fft_idx_max_7_0_len 8
  5800. -#define	reg_fft_idx_max_7_0_lsb 0
  5801. -#define xd_r_reg_fft_idx_max_12_8	0xA2AD
  5802. -#define	reg_fft_idx_max_12_8_pos 0
  5803. -#define	reg_fft_idx_max_12_8_len 5
  5804. -#define	reg_fft_idx_max_12_8_lsb 8
  5805. -#define xd_p_reg_cge_program	0xA2AE
  5806. -#define	reg_cge_program_pos 0
  5807. -#define	reg_cge_program_len 1
  5808. -#define	reg_cge_program_lsb 0
  5809. -#define xd_p_reg_cge_fixed	0xA2AE
  5810. -#define	reg_cge_fixed_pos 1
  5811. -#define	reg_cge_fixed_len 1
  5812. -#define	reg_cge_fixed_lsb 0
  5813. -#define xd_p_reg_fft_rotate_en	0xA2AE
  5814. -#define	reg_fft_rotate_en_pos 2
  5815. -#define	reg_fft_rotate_en_len 1
  5816. -#define	reg_fft_rotate_en_lsb 0
  5817. -#define xd_p_reg_fft_rotate_base_4_0	0xA2AE
  5818. -#define	reg_fft_rotate_base_4_0_pos 3
  5819. -#define	reg_fft_rotate_base_4_0_len 5
  5820. -#define	reg_fft_rotate_base_4_0_lsb 0
  5821. -#define xd_p_reg_fft_rotate_base_12_5	0xA2AF
  5822. -#define	reg_fft_rotate_base_12_5_pos 0
  5823. -#define	reg_fft_rotate_base_12_5_len 8
  5824. -#define	reg_fft_rotate_base_12_5_lsb 5
  5825. -#define xd_p_reg_gp_trigger_fd	0xA2B8
  5826. -#define	reg_gp_trigger_fd_pos 0
  5827. -#define	reg_gp_trigger_fd_len 1
  5828. -#define	reg_gp_trigger_fd_lsb 0
  5829. -#define xd_p_reg_trigger_sel_fd	0xA2B8
  5830. -#define	reg_trigger_sel_fd_pos 1
  5831. -#define	reg_trigger_sel_fd_len 2
  5832. -#define	reg_trigger_sel_fd_lsb 0
  5833. -#define xd_p_reg_trigger_module_sel_fd	0xA2B9
  5834. -#define	reg_trigger_module_sel_fd_pos 0
  5835. -#define	reg_trigger_module_sel_fd_len 6
  5836. -#define	reg_trigger_module_sel_fd_lsb 0
  5837. -#define xd_p_reg_trigger_set_sel_fd	0xA2BA
  5838. -#define	reg_trigger_set_sel_fd_pos 0
  5839. -#define	reg_trigger_set_sel_fd_len 6
  5840. -#define	reg_trigger_set_sel_fd_lsb 0
  5841. -#define xd_p_reg_fd_noname_7_0	0xA2BC
  5842. -#define	reg_fd_noname_7_0_pos 0
  5843. -#define	reg_fd_noname_7_0_len 8
  5844. -#define	reg_fd_noname_7_0_lsb 0
  5845. -#define xd_p_reg_fd_noname_15_8	0xA2BD
  5846. -#define	reg_fd_noname_15_8_pos 0
  5847. -#define	reg_fd_noname_15_8_len 8
  5848. -#define	reg_fd_noname_15_8_lsb 8
  5849. -#define xd_p_reg_fd_noname_23_16	0xA2BE
  5850. -#define	reg_fd_noname_23_16_pos 0
  5851. -#define	reg_fd_noname_23_16_len 8
  5852. -#define	reg_fd_noname_23_16_lsb 16
  5853. -#define xd_p_reg_fd_noname_31_24	0xA2BF
  5854. -#define	reg_fd_noname_31_24_pos 0
  5855. -#define	reg_fd_noname_31_24_len 8
  5856. -#define	reg_fd_noname_31_24_lsb 24
  5857. -#define xd_r_fd_fpcc_cp_corr_signn	0xA2C0
  5858. -#define	fd_fpcc_cp_corr_signn_pos 0
  5859. -#define	fd_fpcc_cp_corr_signn_len 8
  5860. -#define	fd_fpcc_cp_corr_signn_lsb 0
  5861. -#define xd_p_reg_feq_s1	0xA2C1
  5862. -#define	reg_feq_s1_pos 0
  5863. -#define	reg_feq_s1_len 5
  5864. -#define	reg_feq_s1_lsb 0
  5865. -#define xd_p_fd_fpcc_cp_corr_tone_th	0xA2C2
  5866. -#define	fd_fpcc_cp_corr_tone_th_pos 0
  5867. -#define	fd_fpcc_cp_corr_tone_th_len 6
  5868. -#define	fd_fpcc_cp_corr_tone_th_lsb 0
  5869. -#define xd_p_fd_fpcc_cp_corr_symbol_log_th	0xA2C3
  5870. -#define	fd_fpcc_cp_corr_symbol_log_th_pos 0
  5871. -#define	fd_fpcc_cp_corr_symbol_log_th_len 4
  5872. -#define	fd_fpcc_cp_corr_symbol_log_th_lsb 0
  5873. -#define xd_p_fd_fpcc_cp_corr_int	0xA2C4
  5874. -#define	fd_fpcc_cp_corr_int_pos 0
  5875. -#define	fd_fpcc_cp_corr_int_len 1
  5876. -#define	fd_fpcc_cp_corr_int_lsb 0
  5877. -#define xd_p_reg_sfoe_ns_7_0	0xA320
  5878. -#define	reg_sfoe_ns_7_0_pos 0
  5879. -#define	reg_sfoe_ns_7_0_len 8
  5880. -#define	reg_sfoe_ns_7_0_lsb 0
  5881. -#define xd_p_reg_sfoe_ns_14_8	0xA321
  5882. -#define	reg_sfoe_ns_14_8_pos 0
  5883. -#define	reg_sfoe_ns_14_8_len 7
  5884. -#define	reg_sfoe_ns_14_8_lsb 8
  5885. -#define xd_p_reg_sfoe_c1_7_0	0xA322
  5886. -#define	reg_sfoe_c1_7_0_pos 0
  5887. -#define	reg_sfoe_c1_7_0_len 8
  5888. -#define	reg_sfoe_c1_7_0_lsb 0
  5889. -#define xd_p_reg_sfoe_c1_15_8	0xA323
  5890. -#define	reg_sfoe_c1_15_8_pos 0
  5891. -#define	reg_sfoe_c1_15_8_len 8
  5892. -#define	reg_sfoe_c1_15_8_lsb 8
  5893. -#define xd_p_reg_sfoe_c1_17_16	0xA324
  5894. -#define	reg_sfoe_c1_17_16_pos 0
  5895. -#define	reg_sfoe_c1_17_16_len 2
  5896. -#define	reg_sfoe_c1_17_16_lsb 16
  5897. -#define xd_p_reg_sfoe_c2_7_0	0xA325
  5898. -#define	reg_sfoe_c2_7_0_pos 0
  5899. -#define	reg_sfoe_c2_7_0_len 8
  5900. -#define	reg_sfoe_c2_7_0_lsb 0
  5901. -#define xd_p_reg_sfoe_c2_15_8	0xA326
  5902. -#define	reg_sfoe_c2_15_8_pos 0
  5903. -#define	reg_sfoe_c2_15_8_len 8
  5904. -#define	reg_sfoe_c2_15_8_lsb 8
  5905. -#define xd_p_reg_sfoe_c2_17_16	0xA327
  5906. -#define	reg_sfoe_c2_17_16_pos 0
  5907. -#define	reg_sfoe_c2_17_16_len 2
  5908. -#define	reg_sfoe_c2_17_16_lsb 16
  5909. -#define xd_r_reg_sfoe_out_9_2	0xA328
  5910. -#define	reg_sfoe_out_9_2_pos 0
  5911. -#define	reg_sfoe_out_9_2_len 8
  5912. -#define	reg_sfoe_out_9_2_lsb 0
  5913. -#define xd_r_reg_sfoe_out_1_0	0xA329
  5914. -#define	reg_sfoe_out_1_0_pos 0
  5915. -#define	reg_sfoe_out_1_0_len 2
  5916. -#define	reg_sfoe_out_1_0_lsb 0
  5917. -#define xd_p_reg_sfoe_lm_counter_th	0xA32A
  5918. -#define	reg_sfoe_lm_counter_th_pos 0
  5919. -#define	reg_sfoe_lm_counter_th_len 4
  5920. -#define	reg_sfoe_lm_counter_th_lsb 0
  5921. -#define xd_p_reg_sfoe_convg_th	0xA32B
  5922. -#define	reg_sfoe_convg_th_pos 0
  5923. -#define	reg_sfoe_convg_th_len 8
  5924. -#define	reg_sfoe_convg_th_lsb 0
  5925. -#define xd_p_reg_sfoe_divg_th	0xA32C
  5926. -#define	reg_sfoe_divg_th_pos 0
  5927. -#define	reg_sfoe_divg_th_len 8
  5928. -#define	reg_sfoe_divg_th_lsb 0
  5929. -#define xd_p_fd_tpsd_en	0xA330
  5930. -#define	fd_tpsd_en_pos 0
  5931. -#define	fd_tpsd_en_len 1
  5932. -#define	fd_tpsd_en_lsb 0
  5933. -#define xd_p_fd_tpsd_dis	0xA330
  5934. -#define	fd_tpsd_dis_pos 1
  5935. -#define	fd_tpsd_dis_len 1
  5936. -#define	fd_tpsd_dis_lsb 0
  5937. -#define xd_p_fd_tpsd_rst	0xA330
  5938. -#define	fd_tpsd_rst_pos 2
  5939. -#define	fd_tpsd_rst_len 1
  5940. -#define	fd_tpsd_rst_lsb 0
  5941. -#define xd_p_fd_tpsd_lock	0xA330
  5942. -#define	fd_tpsd_lock_pos 3
  5943. -#define	fd_tpsd_lock_len 1
  5944. -#define	fd_tpsd_lock_lsb 0
  5945. -#define xd_r_fd_tpsd_s19	0xA330
  5946. -#define	fd_tpsd_s19_pos 4
  5947. -#define	fd_tpsd_s19_len 1
  5948. -#define	fd_tpsd_s19_lsb 0
  5949. -#define xd_r_fd_tpsd_s17	0xA330
  5950. -#define	fd_tpsd_s17_pos 5
  5951. -#define	fd_tpsd_s17_len 1
  5952. -#define	fd_tpsd_s17_lsb 0
  5953. -#define xd_p_fd_sfr_ste_en	0xA331
  5954. -#define	fd_sfr_ste_en_pos 0
  5955. -#define	fd_sfr_ste_en_len 1
  5956. -#define	fd_sfr_ste_en_lsb 0
  5957. -#define xd_p_fd_sfr_ste_dis	0xA331
  5958. -#define	fd_sfr_ste_dis_pos 1
  5959. -#define	fd_sfr_ste_dis_len 1
  5960. -#define	fd_sfr_ste_dis_lsb 0
  5961. -#define xd_p_fd_sfr_ste_rst	0xA331
  5962. -#define	fd_sfr_ste_rst_pos 2
  5963. -#define	fd_sfr_ste_rst_len 1
  5964. -#define	fd_sfr_ste_rst_lsb 0
  5965. -#define xd_p_fd_sfr_ste_mode	0xA331
  5966. -#define	fd_sfr_ste_mode_pos 3
  5967. -#define	fd_sfr_ste_mode_len 1
  5968. -#define	fd_sfr_ste_mode_lsb 0
  5969. -#define xd_p_fd_sfr_ste_done	0xA331
  5970. -#define	fd_sfr_ste_done_pos 4
  5971. -#define	fd_sfr_ste_done_len 1
  5972. -#define	fd_sfr_ste_done_lsb 0
  5973. -#define xd_p_reg_cfoe_ffoe_en	0xA332
  5974. -#define	reg_cfoe_ffoe_en_pos 0
  5975. -#define	reg_cfoe_ffoe_en_len 1
  5976. -#define	reg_cfoe_ffoe_en_lsb 0
  5977. -#define xd_p_reg_cfoe_ffoe_dis	0xA332
  5978. -#define	reg_cfoe_ffoe_dis_pos 1
  5979. -#define	reg_cfoe_ffoe_dis_len 1
  5980. -#define	reg_cfoe_ffoe_dis_lsb 0
  5981. -#define xd_p_reg_cfoe_ffoe_rst	0xA332
  5982. -#define	reg_cfoe_ffoe_rst_pos 2
  5983. -#define	reg_cfoe_ffoe_rst_len 1
  5984. -#define	reg_cfoe_ffoe_rst_lsb 0
  5985. -#define xd_p_reg_cfoe_ifoe_en	0xA332
  5986. -#define	reg_cfoe_ifoe_en_pos 3
  5987. -#define	reg_cfoe_ifoe_en_len 1
  5988. -#define	reg_cfoe_ifoe_en_lsb 0
  5989. -#define xd_p_reg_cfoe_ifoe_dis	0xA332
  5990. -#define	reg_cfoe_ifoe_dis_pos 4
  5991. -#define	reg_cfoe_ifoe_dis_len 1
  5992. -#define	reg_cfoe_ifoe_dis_lsb 0
  5993. -#define xd_p_reg_cfoe_ifoe_rst	0xA332
  5994. -#define	reg_cfoe_ifoe_rst_pos 5
  5995. -#define	reg_cfoe_ifoe_rst_len 1
  5996. -#define	reg_cfoe_ifoe_rst_lsb 0
  5997. -#define xd_p_reg_cfoe_fot_en	0xA332
  5998. -#define	reg_cfoe_fot_en_pos 6
  5999. -#define	reg_cfoe_fot_en_len 1
  6000. -#define	reg_cfoe_fot_en_lsb 0
  6001. -#define xd_p_reg_cfoe_fot_lm_en	0xA332
  6002. -#define	reg_cfoe_fot_lm_en_pos 7
  6003. -#define	reg_cfoe_fot_lm_en_len 1
  6004. -#define	reg_cfoe_fot_lm_en_lsb 0
  6005. -#define xd_p_reg_cfoe_fot_rst	0xA333
  6006. -#define	reg_cfoe_fot_rst_pos 0
  6007. -#define	reg_cfoe_fot_rst_len 1
  6008. -#define	reg_cfoe_fot_rst_lsb 0
  6009. -#define xd_r_fd_cfoe_ffoe_done	0xA333
  6010. -#define	fd_cfoe_ffoe_done_pos 1
  6011. -#define	fd_cfoe_ffoe_done_len 1
  6012. -#define	fd_cfoe_ffoe_done_lsb 0
  6013. -#define xd_p_fd_cfoe_metric_vld	0xA333
  6014. -#define	fd_cfoe_metric_vld_pos 2
  6015. -#define	fd_cfoe_metric_vld_len 1
  6016. -#define	fd_cfoe_metric_vld_lsb 0
  6017. -#define xd_p_reg_cfoe_ifod_vld	0xA333
  6018. -#define	reg_cfoe_ifod_vld_pos 3
  6019. -#define	reg_cfoe_ifod_vld_len 1
  6020. -#define	reg_cfoe_ifod_vld_lsb 0
  6021. -#define xd_r_fd_cfoe_ifoe_done	0xA333
  6022. -#define	fd_cfoe_ifoe_done_pos 4
  6023. -#define	fd_cfoe_ifoe_done_len 1
  6024. -#define	fd_cfoe_ifoe_done_lsb 0
  6025. -#define xd_r_fd_cfoe_fot_valid	0xA333
  6026. -#define	fd_cfoe_fot_valid_pos 5
  6027. -#define	fd_cfoe_fot_valid_len 1
  6028. -#define	fd_cfoe_fot_valid_lsb 0
  6029. -#define xd_p_reg_cfoe_divg_int	0xA333
  6030. -#define	reg_cfoe_divg_int_pos 6
  6031. -#define	reg_cfoe_divg_int_len 1
  6032. -#define	reg_cfoe_divg_int_lsb 0
  6033. -#define xd_r_reg_cfoe_divg_flag	0xA333
  6034. -#define	reg_cfoe_divg_flag_pos 7
  6035. -#define	reg_cfoe_divg_flag_len 1
  6036. -#define	reg_cfoe_divg_flag_lsb 0
  6037. -#define xd_p_reg_sfoe_en	0xA334
  6038. -#define	reg_sfoe_en_pos 0
  6039. -#define	reg_sfoe_en_len 1
  6040. -#define	reg_sfoe_en_lsb 0
  6041. -#define xd_p_reg_sfoe_dis	0xA334
  6042. -#define	reg_sfoe_dis_pos 1
  6043. -#define	reg_sfoe_dis_len 1
  6044. -#define	reg_sfoe_dis_lsb 0
  6045. -#define xd_p_reg_sfoe_rst	0xA334
  6046. -#define	reg_sfoe_rst_pos 2
  6047. -#define	reg_sfoe_rst_len 1
  6048. -#define	reg_sfoe_rst_lsb 0
  6049. -#define xd_p_reg_sfoe_vld_int	0xA334
  6050. -#define	reg_sfoe_vld_int_pos 3
  6051. -#define	reg_sfoe_vld_int_len 1
  6052. -#define	reg_sfoe_vld_int_lsb 0
  6053. -#define xd_p_reg_sfoe_lm_en	0xA334
  6054. -#define	reg_sfoe_lm_en_pos 4
  6055. -#define	reg_sfoe_lm_en_len 1
  6056. -#define	reg_sfoe_lm_en_lsb 0
  6057. -#define xd_p_reg_sfoe_divg_int	0xA334
  6058. -#define	reg_sfoe_divg_int_pos 5
  6059. -#define	reg_sfoe_divg_int_len 1
  6060. -#define	reg_sfoe_divg_int_lsb 0
  6061. -#define xd_r_reg_sfoe_divg_flag	0xA334
  6062. -#define	reg_sfoe_divg_flag_pos 6
  6063. -#define	reg_sfoe_divg_flag_len 1
  6064. -#define	reg_sfoe_divg_flag_lsb 0
  6065. -#define xd_p_reg_fft_rst	0xA335
  6066. -#define	reg_fft_rst_pos 0
  6067. -#define	reg_fft_rst_len 1
  6068. -#define	reg_fft_rst_lsb 0
  6069. -#define xd_p_reg_fft_fast_beacon	0xA335
  6070. -#define	reg_fft_fast_beacon_pos 1
  6071. -#define	reg_fft_fast_beacon_len 1
  6072. -#define	reg_fft_fast_beacon_lsb 0
  6073. -#define xd_p_reg_fft_fast_valid	0xA335
  6074. -#define	reg_fft_fast_valid_pos 2
  6075. -#define	reg_fft_fast_valid_len 1
  6076. -#define	reg_fft_fast_valid_lsb 0
  6077. -#define xd_p_reg_fft_mask_en	0xA335
  6078. -#define	reg_fft_mask_en_pos 3
  6079. -#define	reg_fft_mask_en_len 1
  6080. -#define	reg_fft_mask_en_lsb 0
  6081. -#define xd_p_reg_fft_crc_en	0xA335
  6082. -#define	reg_fft_crc_en_pos 4
  6083. -#define	reg_fft_crc_en_len 1
  6084. -#define	reg_fft_crc_en_lsb 0
  6085. -#define xd_p_reg_finr_en	0xA336
  6086. -#define	reg_finr_en_pos 0
  6087. -#define	reg_finr_en_len 1
  6088. -#define	reg_finr_en_lsb 0
  6089. -#define xd_p_fd_fste_en	0xA337
  6090. -#define	fd_fste_en_pos 1
  6091. -#define	fd_fste_en_len 1
  6092. -#define	fd_fste_en_lsb 0
  6093. -#define xd_p_fd_sqi_tps_level_shift	0xA338
  6094. -#define	fd_sqi_tps_level_shift_pos 0
  6095. -#define	fd_sqi_tps_level_shift_len 8
  6096. -#define	fd_sqi_tps_level_shift_lsb 0
  6097. -#define xd_p_fd_pilot_ma_len	0xA339
  6098. -#define	fd_pilot_ma_len_pos 0
  6099. -#define	fd_pilot_ma_len_len 6
  6100. -#define	fd_pilot_ma_len_lsb 0
  6101. -#define xd_p_fd_tps_ma_len	0xA33A
  6102. -#define	fd_tps_ma_len_pos 0
  6103. -#define	fd_tps_ma_len_len 6
  6104. -#define	fd_tps_ma_len_lsb 0
  6105. -#define xd_p_fd_sqi_s3	0xA33B
  6106. -#define	fd_sqi_s3_pos 0
  6107. -#define	fd_sqi_s3_len 8
  6108. -#define	fd_sqi_s3_lsb 0
  6109. -#define xd_p_fd_sqi_dummy_reg_0	0xA33C
  6110. -#define	fd_sqi_dummy_reg_0_pos 0
  6111. -#define	fd_sqi_dummy_reg_0_len 1
  6112. -#define	fd_sqi_dummy_reg_0_lsb 0
  6113. -#define xd_p_fd_sqi_debug_sel	0xA33C
  6114. -#define	fd_sqi_debug_sel_pos 1
  6115. -#define	fd_sqi_debug_sel_len 2
  6116. -#define	fd_sqi_debug_sel_lsb 0
  6117. -#define xd_p_fd_sqi_s2	0xA33C
  6118. -#define	fd_sqi_s2_pos 3
  6119. -#define	fd_sqi_s2_len 5
  6120. -#define	fd_sqi_s2_lsb 0
  6121. -#define xd_p_fd_sqi_dummy_reg_1	0xA33D
  6122. -#define	fd_sqi_dummy_reg_1_pos 0
  6123. -#define	fd_sqi_dummy_reg_1_len 1
  6124. -#define	fd_sqi_dummy_reg_1_lsb 0
  6125. -#define xd_p_fd_inr_ignore	0xA33D
  6126. -#define	fd_inr_ignore_pos 1
  6127. -#define	fd_inr_ignore_len 1
  6128. -#define	fd_inr_ignore_lsb 0
  6129. -#define xd_p_fd_pilot_ignore	0xA33D
  6130. -#define	fd_pilot_ignore_pos 2
  6131. -#define	fd_pilot_ignore_len 1
  6132. -#define	fd_pilot_ignore_lsb 0
  6133. -#define xd_p_fd_etps_ignore	0xA33D
  6134. -#define	fd_etps_ignore_pos 3
  6135. -#define	fd_etps_ignore_len 1
  6136. -#define	fd_etps_ignore_lsb 0
  6137. -#define xd_p_fd_sqi_s1	0xA33D
  6138. -#define	fd_sqi_s1_pos 4
  6139. -#define	fd_sqi_s1_len 4
  6140. -#define	fd_sqi_s1_lsb 0
  6141. -#define xd_p_reg_fste_ehw_7_0	0xA33E
  6142. -#define	reg_fste_ehw_7_0_pos 0
  6143. -#define	reg_fste_ehw_7_0_len 8
  6144. -#define	reg_fste_ehw_7_0_lsb 0
  6145. -#define xd_p_reg_fste_ehw_9_8	0xA33F
  6146. -#define	reg_fste_ehw_9_8_pos 0
  6147. -#define	reg_fste_ehw_9_8_len 2
  6148. -#define	reg_fste_ehw_9_8_lsb 8
  6149. -#define xd_p_reg_fste_i_adj_vld	0xA33F
  6150. -#define	reg_fste_i_adj_vld_pos 2
  6151. -#define	reg_fste_i_adj_vld_len 1
  6152. -#define	reg_fste_i_adj_vld_lsb 0
  6153. -#define xd_p_reg_fste_phase_ini_7_0	0xA340
  6154. -#define	reg_fste_phase_ini_7_0_pos 0
  6155. -#define	reg_fste_phase_ini_7_0_len 8
  6156. -#define	reg_fste_phase_ini_7_0_lsb 0
  6157. -#define xd_p_reg_fste_phase_ini_11_8	0xA341
  6158. -#define	reg_fste_phase_ini_11_8_pos 0
  6159. -#define	reg_fste_phase_ini_11_8_len 4
  6160. -#define	reg_fste_phase_ini_11_8_lsb 8
  6161. -#define xd_p_reg_fste_phase_inc_3_0	0xA341
  6162. -#define	reg_fste_phase_inc_3_0_pos 4
  6163. -#define	reg_fste_phase_inc_3_0_len 4
  6164. -#define	reg_fste_phase_inc_3_0_lsb 0
  6165. -#define xd_p_reg_fste_phase_inc_11_4	0xA342
  6166. -#define	reg_fste_phase_inc_11_4_pos 0
  6167. -#define	reg_fste_phase_inc_11_4_len 8
  6168. -#define	reg_fste_phase_inc_11_4_lsb 4
  6169. -#define xd_p_reg_fste_acum_cost_cnt_max	0xA343
  6170. -#define	reg_fste_acum_cost_cnt_max_pos 0
  6171. -#define	reg_fste_acum_cost_cnt_max_len 4
  6172. -#define	reg_fste_acum_cost_cnt_max_lsb 0
  6173. -#define xd_p_reg_fste_step_size_std	0xA343
  6174. -#define	reg_fste_step_size_std_pos 4
  6175. -#define	reg_fste_step_size_std_len 4
  6176. -#define	reg_fste_step_size_std_lsb 0
  6177. -#define xd_p_reg_fste_step_size_max	0xA344
  6178. -#define	reg_fste_step_size_max_pos 0
  6179. -#define	reg_fste_step_size_max_len 4
  6180. -#define	reg_fste_step_size_max_lsb 0
  6181. -#define xd_p_reg_fste_step_size_min	0xA344
  6182. -#define	reg_fste_step_size_min_pos 4
  6183. -#define	reg_fste_step_size_min_len 4
  6184. -#define	reg_fste_step_size_min_lsb 0
  6185. -#define xd_p_reg_fste_frac_step_size_7_0	0xA345
  6186. -#define	reg_fste_frac_step_size_7_0_pos 0
  6187. -#define	reg_fste_frac_step_size_7_0_len 8
  6188. -#define	reg_fste_frac_step_size_7_0_lsb 0
  6189. -#define xd_p_reg_fste_frac_step_size_15_8	0xA346
  6190. -#define	reg_fste_frac_step_size_15_8_pos 0
  6191. -#define	reg_fste_frac_step_size_15_8_len 8
  6192. -#define	reg_fste_frac_step_size_15_8_lsb 8
  6193. -#define xd_p_reg_fste_frac_step_size_19_16	0xA347
  6194. -#define	reg_fste_frac_step_size_19_16_pos 0
  6195. -#define	reg_fste_frac_step_size_19_16_len 4
  6196. -#define	reg_fste_frac_step_size_19_16_lsb 16
  6197. -#define xd_p_reg_fste_rpd_dir_cnt_max	0xA347
  6198. -#define	reg_fste_rpd_dir_cnt_max_pos 4
  6199. -#define	reg_fste_rpd_dir_cnt_max_len 4
  6200. -#define	reg_fste_rpd_dir_cnt_max_lsb 0
  6201. -#define xd_p_reg_fste_ehs	0xA348
  6202. -#define	reg_fste_ehs_pos 0
  6203. -#define	reg_fste_ehs_len 4
  6204. -#define	reg_fste_ehs_lsb 0
  6205. -#define xd_p_reg_fste_frac_cost_cnt_max_3_0	0xA348
  6206. -#define	reg_fste_frac_cost_cnt_max_3_0_pos 4
  6207. -#define	reg_fste_frac_cost_cnt_max_3_0_len 4
  6208. -#define	reg_fste_frac_cost_cnt_max_3_0_lsb 0
  6209. -#define xd_p_reg_fste_frac_cost_cnt_max_9_4	0xA349
  6210. -#define	reg_fste_frac_cost_cnt_max_9_4_pos 0
  6211. -#define	reg_fste_frac_cost_cnt_max_9_4_len 6
  6212. -#define	reg_fste_frac_cost_cnt_max_9_4_lsb 4
  6213. -#define xd_p_reg_fste_w0_7_0	0xA34A
  6214. -#define	reg_fste_w0_7_0_pos 0
  6215. -#define	reg_fste_w0_7_0_len 8
  6216. -#define	reg_fste_w0_7_0_lsb 0
  6217. -#define xd_p_reg_fste_w0_11_8	0xA34B
  6218. -#define	reg_fste_w0_11_8_pos 0
  6219. -#define	reg_fste_w0_11_8_len 4
  6220. -#define	reg_fste_w0_11_8_lsb 8
  6221. -#define xd_p_reg_fste_w1_3_0	0xA34B
  6222. -#define	reg_fste_w1_3_0_pos 4
  6223. -#define	reg_fste_w1_3_0_len 4
  6224. -#define	reg_fste_w1_3_0_lsb 0
  6225. -#define xd_p_reg_fste_w1_11_4	0xA34C
  6226. -#define	reg_fste_w1_11_4_pos 0
  6227. -#define	reg_fste_w1_11_4_len 8
  6228. -#define	reg_fste_w1_11_4_lsb 4
  6229. -#define xd_p_reg_fste_w2_7_0	0xA34D
  6230. -#define	reg_fste_w2_7_0_pos 0
  6231. -#define	reg_fste_w2_7_0_len 8
  6232. -#define	reg_fste_w2_7_0_lsb 0
  6233. -#define xd_p_reg_fste_w2_11_8	0xA34E
  6234. -#define	reg_fste_w2_11_8_pos 0
  6235. -#define	reg_fste_w2_11_8_len 4
  6236. -#define	reg_fste_w2_11_8_lsb 8
  6237. -#define xd_p_reg_fste_w3_3_0	0xA34E
  6238. -#define	reg_fste_w3_3_0_pos 4
  6239. -#define	reg_fste_w3_3_0_len 4
  6240. -#define	reg_fste_w3_3_0_lsb 0
  6241. -#define xd_p_reg_fste_w3_11_4	0xA34F
  6242. -#define	reg_fste_w3_11_4_pos 0
  6243. -#define	reg_fste_w3_11_4_len 8
  6244. -#define	reg_fste_w3_11_4_lsb 4
  6245. -#define xd_p_reg_fste_w4_7_0	0xA350
  6246. -#define	reg_fste_w4_7_0_pos 0
  6247. -#define	reg_fste_w4_7_0_len 8
  6248. -#define	reg_fste_w4_7_0_lsb 0
  6249. -#define xd_p_reg_fste_w4_11_8	0xA351
  6250. -#define	reg_fste_w4_11_8_pos 0
  6251. -#define	reg_fste_w4_11_8_len 4
  6252. -#define	reg_fste_w4_11_8_lsb 8
  6253. -#define xd_p_reg_fste_w5_3_0	0xA351
  6254. -#define	reg_fste_w5_3_0_pos 4
  6255. -#define	reg_fste_w5_3_0_len 4
  6256. -#define	reg_fste_w5_3_0_lsb 0
  6257. -#define xd_p_reg_fste_w5_11_4	0xA352
  6258. -#define	reg_fste_w5_11_4_pos 0
  6259. -#define	reg_fste_w5_11_4_len 8
  6260. -#define	reg_fste_w5_11_4_lsb 4
  6261. -#define xd_p_reg_fste_w6_7_0	0xA353
  6262. -#define	reg_fste_w6_7_0_pos 0
  6263. -#define	reg_fste_w6_7_0_len 8
  6264. -#define	reg_fste_w6_7_0_lsb 0
  6265. -#define xd_p_reg_fste_w6_11_8	0xA354
  6266. -#define	reg_fste_w6_11_8_pos 0
  6267. -#define	reg_fste_w6_11_8_len 4
  6268. -#define	reg_fste_w6_11_8_lsb 8
  6269. -#define xd_p_reg_fste_w7_3_0	0xA354
  6270. -#define	reg_fste_w7_3_0_pos 4
  6271. -#define	reg_fste_w7_3_0_len 4
  6272. -#define	reg_fste_w7_3_0_lsb 0
  6273. -#define xd_p_reg_fste_w7_11_4	0xA355
  6274. -#define	reg_fste_w7_11_4_pos 0
  6275. -#define	reg_fste_w7_11_4_len 8
  6276. -#define	reg_fste_w7_11_4_lsb 4
  6277. -#define xd_p_reg_fste_w8_7_0	0xA356
  6278. -#define	reg_fste_w8_7_0_pos 0
  6279. -#define	reg_fste_w8_7_0_len 8
  6280. -#define	reg_fste_w8_7_0_lsb 0
  6281. -#define xd_p_reg_fste_w8_11_8	0xA357
  6282. -#define	reg_fste_w8_11_8_pos 0
  6283. -#define	reg_fste_w8_11_8_len 4
  6284. -#define	reg_fste_w8_11_8_lsb 8
  6285. -#define xd_p_reg_fste_w9_3_0	0xA357
  6286. -#define	reg_fste_w9_3_0_pos 4
  6287. -#define	reg_fste_w9_3_0_len 4
  6288. -#define	reg_fste_w9_3_0_lsb 0
  6289. -#define xd_p_reg_fste_w9_11_4	0xA358
  6290. -#define	reg_fste_w9_11_4_pos 0
  6291. -#define	reg_fste_w9_11_4_len 8
  6292. -#define	reg_fste_w9_11_4_lsb 4
  6293. -#define xd_p_reg_fste_wa_7_0	0xA359
  6294. -#define	reg_fste_wa_7_0_pos 0
  6295. -#define	reg_fste_wa_7_0_len 8
  6296. -#define	reg_fste_wa_7_0_lsb 0
  6297. -#define xd_p_reg_fste_wa_11_8	0xA35A
  6298. -#define	reg_fste_wa_11_8_pos 0
  6299. -#define	reg_fste_wa_11_8_len 4
  6300. -#define	reg_fste_wa_11_8_lsb 8
  6301. -#define xd_p_reg_fste_wb_3_0	0xA35A
  6302. -#define	reg_fste_wb_3_0_pos 4
  6303. -#define	reg_fste_wb_3_0_len 4
  6304. -#define	reg_fste_wb_3_0_lsb 0
  6305. -#define xd_p_reg_fste_wb_11_4	0xA35B
  6306. -#define	reg_fste_wb_11_4_pos 0
  6307. -#define	reg_fste_wb_11_4_len 8
  6308. -#define	reg_fste_wb_11_4_lsb 4
  6309. -#define xd_r_fd_fste_i_adj	0xA35C
  6310. -#define	fd_fste_i_adj_pos 0
  6311. -#define	fd_fste_i_adj_len 5
  6312. -#define	fd_fste_i_adj_lsb 0
  6313. -#define xd_r_fd_fste_f_adj_7_0	0xA35D
  6314. -#define	fd_fste_f_adj_7_0_pos 0
  6315. -#define	fd_fste_f_adj_7_0_len 8
  6316. -#define	fd_fste_f_adj_7_0_lsb 0
  6317. -#define xd_r_fd_fste_f_adj_15_8	0xA35E
  6318. -#define	fd_fste_f_adj_15_8_pos 0
  6319. -#define	fd_fste_f_adj_15_8_len 8
  6320. -#define	fd_fste_f_adj_15_8_lsb 8
  6321. -#define xd_r_fd_fste_f_adj_19_16	0xA35F
  6322. -#define	fd_fste_f_adj_19_16_pos 0
  6323. -#define	fd_fste_f_adj_19_16_len 4
  6324. -#define	fd_fste_f_adj_19_16_lsb 16
  6325. -#define xd_p_reg_feq_Leak_Bypass	0xA366
  6326. -#define	reg_feq_Leak_Bypass_pos 0
  6327. -#define	reg_feq_Leak_Bypass_len 1
  6328. -#define	reg_feq_Leak_Bypass_lsb 0
  6329. -#define xd_p_reg_feq_Leak_Mneg1	0xA366
  6330. -#define	reg_feq_Leak_Mneg1_pos 1
  6331. -#define	reg_feq_Leak_Mneg1_len 3
  6332. -#define	reg_feq_Leak_Mneg1_lsb 0
  6333. -#define xd_p_reg_feq_Leak_B_ShiftQ	0xA366
  6334. -#define	reg_feq_Leak_B_ShiftQ_pos 4
  6335. -#define	reg_feq_Leak_B_ShiftQ_len 4
  6336. -#define	reg_feq_Leak_B_ShiftQ_lsb 0
  6337. -#define xd_p_reg_feq_Leak_B_Float0	0xA367
  6338. -#define	reg_feq_Leak_B_Float0_pos 0
  6339. -#define	reg_feq_Leak_B_Float0_len 8
  6340. -#define	reg_feq_Leak_B_Float0_lsb 0
  6341. -#define xd_p_reg_feq_Leak_B_Float1	0xA368
  6342. -#define	reg_feq_Leak_B_Float1_pos 0
  6343. -#define	reg_feq_Leak_B_Float1_len 8
  6344. -#define	reg_feq_Leak_B_Float1_lsb 0
  6345. -#define xd_p_reg_feq_Leak_B_Float2	0xA369
  6346. -#define	reg_feq_Leak_B_Float2_pos 0
  6347. -#define	reg_feq_Leak_B_Float2_len 8
  6348. -#define	reg_feq_Leak_B_Float2_lsb 0
  6349. -#define xd_p_reg_feq_Leak_B_Float3	0xA36A
  6350. -#define	reg_feq_Leak_B_Float3_pos 0
  6351. -#define	reg_feq_Leak_B_Float3_len 8
  6352. -#define	reg_feq_Leak_B_Float3_lsb 0
  6353. -#define xd_p_reg_feq_Leak_B_Float4	0xA36B
  6354. -#define	reg_feq_Leak_B_Float4_pos 0
  6355. -#define	reg_feq_Leak_B_Float4_len 8
  6356. -#define	reg_feq_Leak_B_Float4_lsb 0
  6357. -#define xd_p_reg_feq_Leak_B_Float5	0xA36C
  6358. -#define	reg_feq_Leak_B_Float5_pos 0
  6359. -#define	reg_feq_Leak_B_Float5_len 8
  6360. -#define	reg_feq_Leak_B_Float5_lsb 0
  6361. -#define xd_p_reg_feq_Leak_B_Float6	0xA36D
  6362. -#define	reg_feq_Leak_B_Float6_pos 0
  6363. -#define	reg_feq_Leak_B_Float6_len 8
  6364. -#define	reg_feq_Leak_B_Float6_lsb 0
  6365. -#define xd_p_reg_feq_Leak_B_Float7	0xA36E
  6366. -#define	reg_feq_Leak_B_Float7_pos 0
  6367. -#define	reg_feq_Leak_B_Float7_len 8
  6368. -#define	reg_feq_Leak_B_Float7_lsb 0
  6369. -#define xd_r_reg_feq_data_h2_7_0	0xA36F
  6370. -#define	reg_feq_data_h2_7_0_pos 0
  6371. -#define	reg_feq_data_h2_7_0_len 8
  6372. -#define	reg_feq_data_h2_7_0_lsb 0
  6373. -#define xd_r_reg_feq_data_h2_9_8	0xA370
  6374. -#define	reg_feq_data_h2_9_8_pos 0
  6375. -#define	reg_feq_data_h2_9_8_len 2
  6376. -#define	reg_feq_data_h2_9_8_lsb 8
  6377. -#define xd_p_reg_feq_leak_use_slice_tps	0xA371
  6378. -#define	reg_feq_leak_use_slice_tps_pos 0
  6379. -#define	reg_feq_leak_use_slice_tps_len 1
  6380. -#define	reg_feq_leak_use_slice_tps_lsb 0
  6381. -#define xd_p_reg_feq_read_update	0xA371
  6382. -#define	reg_feq_read_update_pos 1
  6383. -#define	reg_feq_read_update_len 1
  6384. -#define	reg_feq_read_update_lsb 0
  6385. -#define xd_p_reg_feq_data_vld	0xA371
  6386. -#define	reg_feq_data_vld_pos 2
  6387. -#define	reg_feq_data_vld_len 1
  6388. -#define	reg_feq_data_vld_lsb 0
  6389. -#define xd_p_reg_feq_tone_idx_4_0	0xA371
  6390. -#define	reg_feq_tone_idx_4_0_pos 3
  6391. -#define	reg_feq_tone_idx_4_0_len 5
  6392. -#define	reg_feq_tone_idx_4_0_lsb 0
  6393. -#define xd_p_reg_feq_tone_idx_12_5	0xA372
  6394. -#define	reg_feq_tone_idx_12_5_pos 0
  6395. -#define	reg_feq_tone_idx_12_5_len 8
  6396. -#define	reg_feq_tone_idx_12_5_lsb 5
  6397. -#define xd_r_reg_feq_data_re_7_0	0xA373
  6398. -#define	reg_feq_data_re_7_0_pos 0
  6399. -#define	reg_feq_data_re_7_0_len 8
  6400. -#define	reg_feq_data_re_7_0_lsb 0
  6401. -#define xd_r_reg_feq_data_re_10_8	0xA374
  6402. -#define	reg_feq_data_re_10_8_pos 0
  6403. -#define	reg_feq_data_re_10_8_len 3
  6404. -#define	reg_feq_data_re_10_8_lsb 8
  6405. -#define xd_r_reg_feq_data_im_7_0	0xA375
  6406. -#define	reg_feq_data_im_7_0_pos 0
  6407. -#define	reg_feq_data_im_7_0_len 8
  6408. -#define	reg_feq_data_im_7_0_lsb 0
  6409. -#define xd_r_reg_feq_data_im_10_8	0xA376
  6410. -#define	reg_feq_data_im_10_8_pos 0
  6411. -#define	reg_feq_data_im_10_8_len 3
  6412. -#define	reg_feq_data_im_10_8_lsb 8
  6413. -#define xd_r_reg_feq_y_re	0xA377
  6414. -#define	reg_feq_y_re_pos 0
  6415. -#define	reg_feq_y_re_len 8
  6416. -#define	reg_feq_y_re_lsb 0
  6417. -#define xd_r_reg_feq_y_im	0xA378
  6418. -#define	reg_feq_y_im_pos 0
  6419. -#define	reg_feq_y_im_len 8
  6420. -#define	reg_feq_y_im_lsb 0
  6421. -#define xd_r_reg_feq_h_re_7_0	0xA379
  6422. -#define	reg_feq_h_re_7_0_pos 0
  6423. -#define	reg_feq_h_re_7_0_len 8
  6424. -#define	reg_feq_h_re_7_0_lsb 0
  6425. -#define xd_r_reg_feq_h_re_8	0xA37A
  6426. -#define	reg_feq_h_re_8_pos 0
  6427. -#define	reg_feq_h_re_8_len 1
  6428. -#define	reg_feq_h_re_8_lsb 0
  6429. -#define xd_r_reg_feq_h_im_7_0	0xA37B
  6430. -#define	reg_feq_h_im_7_0_pos 0
  6431. -#define	reg_feq_h_im_7_0_len 8
  6432. -#define	reg_feq_h_im_7_0_lsb 0
  6433. -#define xd_r_reg_feq_h_im_8	0xA37C
  6434. -#define	reg_feq_h_im_8_pos 0
  6435. -#define	reg_feq_h_im_8_len 1
  6436. -#define	reg_feq_h_im_8_lsb 0
  6437. -#define xd_p_fec_super_frm_unit_7_0	0xA380
  6438. -#define	fec_super_frm_unit_7_0_pos 0
  6439. -#define	fec_super_frm_unit_7_0_len 8
  6440. -#define	fec_super_frm_unit_7_0_lsb 0
  6441. -#define xd_p_fec_super_frm_unit_15_8	0xA381
  6442. -#define	fec_super_frm_unit_15_8_pos 0
  6443. -#define	fec_super_frm_unit_15_8_len 8
  6444. -#define	fec_super_frm_unit_15_8_lsb 8
  6445. -#define xd_r_fec_vtb_err_bit_cnt_7_0	0xA382
  6446. -#define	fec_vtb_err_bit_cnt_7_0_pos 0
  6447. -#define	fec_vtb_err_bit_cnt_7_0_len 8
  6448. -#define	fec_vtb_err_bit_cnt_7_0_lsb 0
  6449. -#define xd_r_fec_vtb_err_bit_cnt_15_8	0xA383
  6450. -#define	fec_vtb_err_bit_cnt_15_8_pos 0
  6451. -#define	fec_vtb_err_bit_cnt_15_8_len 8
  6452. -#define	fec_vtb_err_bit_cnt_15_8_lsb 8
  6453. -#define xd_r_fec_vtb_err_bit_cnt_23_16	0xA384
  6454. -#define	fec_vtb_err_bit_cnt_23_16_pos 0
  6455. -#define	fec_vtb_err_bit_cnt_23_16_len 8
  6456. -#define	fec_vtb_err_bit_cnt_23_16_lsb 16
  6457. -#define xd_p_fec_rsd_packet_unit_7_0	0xA385
  6458. -#define	fec_rsd_packet_unit_7_0_pos 0
  6459. -#define	fec_rsd_packet_unit_7_0_len 8
  6460. -#define	fec_rsd_packet_unit_7_0_lsb 0
  6461. -#define xd_p_fec_rsd_packet_unit_15_8	0xA386
  6462. -#define	fec_rsd_packet_unit_15_8_pos 0
  6463. -#define	fec_rsd_packet_unit_15_8_len 8
  6464. -#define	fec_rsd_packet_unit_15_8_lsb 8
  6465. -#define xd_r_fec_rsd_bit_err_cnt_7_0	0xA387
  6466. -#define	fec_rsd_bit_err_cnt_7_0_pos 0
  6467. -#define	fec_rsd_bit_err_cnt_7_0_len 8
  6468. -#define	fec_rsd_bit_err_cnt_7_0_lsb 0
  6469. -#define xd_r_fec_rsd_bit_err_cnt_15_8	0xA388
  6470. -#define	fec_rsd_bit_err_cnt_15_8_pos 0
  6471. -#define	fec_rsd_bit_err_cnt_15_8_len 8
  6472. -#define	fec_rsd_bit_err_cnt_15_8_lsb 8
  6473. -#define xd_r_fec_rsd_bit_err_cnt_23_16	0xA389
  6474. -#define	fec_rsd_bit_err_cnt_23_16_pos 0
  6475. -#define	fec_rsd_bit_err_cnt_23_16_len 8
  6476. -#define	fec_rsd_bit_err_cnt_23_16_lsb 16
  6477. -#define xd_r_fec_rsd_abort_packet_cnt_7_0	0xA38A
  6478. -#define	fec_rsd_abort_packet_cnt_7_0_pos 0
  6479. -#define	fec_rsd_abort_packet_cnt_7_0_len 8
  6480. -#define	fec_rsd_abort_packet_cnt_7_0_lsb 0
  6481. -#define xd_r_fec_rsd_abort_packet_cnt_15_8	0xA38B
  6482. -#define	fec_rsd_abort_packet_cnt_15_8_pos 0
  6483. -#define	fec_rsd_abort_packet_cnt_15_8_len 8
  6484. -#define	fec_rsd_abort_packet_cnt_15_8_lsb 8
  6485. -#define xd_p_fec_RSD_PKT_NUM_PER_UNIT_7_0	0xA38C
  6486. -#define	fec_RSD_PKT_NUM_PER_UNIT_7_0_pos 0
  6487. -#define	fec_RSD_PKT_NUM_PER_UNIT_7_0_len 8
  6488. -#define	fec_RSD_PKT_NUM_PER_UNIT_7_0_lsb 0
  6489. -#define xd_p_fec_RSD_PKT_NUM_PER_UNIT_15_8	0xA38D
  6490. -#define	fec_RSD_PKT_NUM_PER_UNIT_15_8_pos 0
  6491. -#define	fec_RSD_PKT_NUM_PER_UNIT_15_8_len 8
  6492. -#define	fec_RSD_PKT_NUM_PER_UNIT_15_8_lsb 8
  6493. -#define xd_p_fec_RS_TH_1_7_0	0xA38E
  6494. -#define	fec_RS_TH_1_7_0_pos 0
  6495. -#define	fec_RS_TH_1_7_0_len 8
  6496. -#define	fec_RS_TH_1_7_0_lsb 0
  6497. -#define xd_p_fec_RS_TH_1_15_8	0xA38F
  6498. -#define	fec_RS_TH_1_15_8_pos 0
  6499. -#define	fec_RS_TH_1_15_8_len 8
  6500. -#define	fec_RS_TH_1_15_8_lsb 8
  6501. -#define xd_p_fec_RS_TH_2	0xA390
  6502. -#define	fec_RS_TH_2_pos 0
  6503. -#define	fec_RS_TH_2_len 8
  6504. -#define	fec_RS_TH_2_lsb 0
  6505. -#define xd_p_fec_mon_en	0xA391
  6506. -#define	fec_mon_en_pos 0
  6507. -#define	fec_mon_en_len 1
  6508. -#define	fec_mon_en_lsb 0
  6509. -#define xd_p_reg_b8to47	0xA391
  6510. -#define	reg_b8to47_pos 1
  6511. -#define	reg_b8to47_len 1
  6512. -#define	reg_b8to47_lsb 0
  6513. -#define xd_p_reg_rsd_sync_rep	0xA391
  6514. -#define	reg_rsd_sync_rep_pos 2
  6515. -#define	reg_rsd_sync_rep_len 1
  6516. -#define	reg_rsd_sync_rep_lsb 0
  6517. -#define xd_p_fec_rsd_retrain_rst	0xA391
  6518. -#define	fec_rsd_retrain_rst_pos 3
  6519. -#define	fec_rsd_retrain_rst_len 1
  6520. -#define	fec_rsd_retrain_rst_lsb 0
  6521. -#define xd_r_fec_rsd_ber_rdy	0xA391
  6522. -#define	fec_rsd_ber_rdy_pos 4
  6523. -#define	fec_rsd_ber_rdy_len 1
  6524. -#define	fec_rsd_ber_rdy_lsb 0
  6525. -#define xd_p_fec_rsd_ber_rst	0xA391
  6526. -#define	fec_rsd_ber_rst_pos 5
  6527. -#define	fec_rsd_ber_rst_len 1
  6528. -#define	fec_rsd_ber_rst_lsb 0
  6529. -#define xd_r_fec_vtb_ber_rdy	0xA391
  6530. -#define	fec_vtb_ber_rdy_pos 6
  6531. -#define	fec_vtb_ber_rdy_len 1
  6532. -#define	fec_vtb_ber_rdy_lsb 0
  6533. -#define xd_p_fec_vtb_ber_rst	0xA391
  6534. -#define	fec_vtb_ber_rst_pos 7
  6535. -#define	fec_vtb_ber_rst_len 1
  6536. -#define	fec_vtb_ber_rst_lsb 0
  6537. -#define xd_p_reg_vtb_clk40en	0xA392
  6538. -#define	reg_vtb_clk40en_pos 0
  6539. -#define	reg_vtb_clk40en_len 1
  6540. -#define	reg_vtb_clk40en_lsb 0
  6541. -#define xd_p_fec_vtb_rsd_mon_en	0xA392
  6542. -#define	fec_vtb_rsd_mon_en_pos 1
  6543. -#define	fec_vtb_rsd_mon_en_len 1
  6544. -#define	fec_vtb_rsd_mon_en_lsb 0
  6545. -#define xd_p_reg_fec_data_en	0xA392
  6546. -#define	reg_fec_data_en_pos 2
  6547. -#define	reg_fec_data_en_len 1
  6548. -#define	reg_fec_data_en_lsb 0
  6549. -#define xd_p_fec_dummy_reg_2	0xA392
  6550. -#define	fec_dummy_reg_2_pos 3
  6551. -#define	fec_dummy_reg_2_len 3
  6552. -#define	fec_dummy_reg_2_lsb 0
  6553. -#define xd_p_reg_sync_chk	0xA392
  6554. -#define	reg_sync_chk_pos 6
  6555. -#define	reg_sync_chk_len 1
  6556. -#define	reg_sync_chk_lsb 0
  6557. -#define xd_p_fec_rsd_bypass	0xA392
  6558. -#define	fec_rsd_bypass_pos 7
  6559. -#define	fec_rsd_bypass_len 1
  6560. -#define	fec_rsd_bypass_lsb 0
  6561. -#define xd_p_fec_sw_rst	0xA393
  6562. -#define	fec_sw_rst_pos 0
  6563. -#define	fec_sw_rst_len 1
  6564. -#define	fec_sw_rst_lsb 0
  6565. -#define xd_r_fec_vtb_pm_crc	0xA394
  6566. -#define	fec_vtb_pm_crc_pos 0
  6567. -#define	fec_vtb_pm_crc_len 8
  6568. -#define	fec_vtb_pm_crc_lsb 0
  6569. -#define xd_r_fec_vtb_tb_7_crc	0xA395
  6570. -#define	fec_vtb_tb_7_crc_pos 0
  6571. -#define	fec_vtb_tb_7_crc_len 8
  6572. -#define	fec_vtb_tb_7_crc_lsb 0
  6573. -#define xd_r_fec_vtb_tb_6_crc	0xA396
  6574. -#define	fec_vtb_tb_6_crc_pos 0
  6575. -#define	fec_vtb_tb_6_crc_len 8
  6576. -#define	fec_vtb_tb_6_crc_lsb 0
  6577. -#define xd_r_fec_vtb_tb_5_crc	0xA397
  6578. -#define	fec_vtb_tb_5_crc_pos 0
  6579. -#define	fec_vtb_tb_5_crc_len 8
  6580. -#define	fec_vtb_tb_5_crc_lsb 0
  6581. -#define xd_r_fec_vtb_tb_4_crc	0xA398
  6582. -#define	fec_vtb_tb_4_crc_pos 0
  6583. -#define	fec_vtb_tb_4_crc_len 8
  6584. -#define	fec_vtb_tb_4_crc_lsb 0
  6585. -#define xd_r_fec_vtb_tb_3_crc	0xA399
  6586. -#define	fec_vtb_tb_3_crc_pos 0
  6587. -#define	fec_vtb_tb_3_crc_len 8
  6588. -#define	fec_vtb_tb_3_crc_lsb 0
  6589. -#define xd_r_fec_vtb_tb_2_crc	0xA39A
  6590. -#define	fec_vtb_tb_2_crc_pos 0
  6591. -#define	fec_vtb_tb_2_crc_len 8
  6592. -#define	fec_vtb_tb_2_crc_lsb 0
  6593. -#define xd_r_fec_vtb_tb_1_crc	0xA39B
  6594. -#define	fec_vtb_tb_1_crc_pos 0
  6595. -#define	fec_vtb_tb_1_crc_len 8
  6596. -#define	fec_vtb_tb_1_crc_lsb 0
  6597. -#define xd_r_fec_vtb_tb_0_crc	0xA39C
  6598. -#define	fec_vtb_tb_0_crc_pos 0
  6599. -#define	fec_vtb_tb_0_crc_len 8
  6600. -#define	fec_vtb_tb_0_crc_lsb 0
  6601. -#define xd_r_fec_rsd_bank0_crc	0xA39D
  6602. -#define	fec_rsd_bank0_crc_pos 0
  6603. -#define	fec_rsd_bank0_crc_len 8
  6604. -#define	fec_rsd_bank0_crc_lsb 0
  6605. -#define xd_r_fec_rsd_bank1_crc	0xA39E
  6606. -#define	fec_rsd_bank1_crc_pos 0
  6607. -#define	fec_rsd_bank1_crc_len 8
  6608. -#define	fec_rsd_bank1_crc_lsb 0
  6609. -#define xd_r_fec_idi_vtb_crc	0xA39F
  6610. -#define	fec_idi_vtb_crc_pos 0
  6611. -#define	fec_idi_vtb_crc_len 8
  6612. -#define	fec_idi_vtb_crc_lsb 0
  6613. -#define xd_g_reg_tpsd_txmod	0xA3C0
  6614. -#define	reg_tpsd_txmod_pos 0
  6615. -#define	reg_tpsd_txmod_len 2
  6616. -#define	reg_tpsd_txmod_lsb 0
  6617. -#define xd_g_reg_tpsd_gi	0xA3C0
  6618. -#define	reg_tpsd_gi_pos 2
  6619. -#define	reg_tpsd_gi_len 2
  6620. -#define	reg_tpsd_gi_lsb 0
  6621. -#define xd_g_reg_tpsd_hier	0xA3C0
  6622. -#define	reg_tpsd_hier_pos 4
  6623. -#define	reg_tpsd_hier_len 3
  6624. -#define	reg_tpsd_hier_lsb 0
  6625. -#define xd_g_reg_bw	0xA3C1
  6626. -#define	reg_bw_pos 2
  6627. -#define	reg_bw_len 2
  6628. -#define	reg_bw_lsb 0
  6629. -#define xd_g_reg_dec_pri	0xA3C1
  6630. -#define	reg_dec_pri_pos 4
  6631. -#define	reg_dec_pri_len 1
  6632. -#define	reg_dec_pri_lsb 0
  6633. -#define xd_g_reg_tpsd_const	0xA3C1
  6634. -#define	reg_tpsd_const_pos 6
  6635. -#define	reg_tpsd_const_len 2
  6636. -#define	reg_tpsd_const_lsb 0
  6637. -#define xd_g_reg_tpsd_hpcr	0xA3C2
  6638. -#define	reg_tpsd_hpcr_pos 0
  6639. -#define	reg_tpsd_hpcr_len 3
  6640. -#define	reg_tpsd_hpcr_lsb 0
  6641. -#define xd_g_reg_tpsd_lpcr	0xA3C2
  6642. -#define	reg_tpsd_lpcr_pos 3
  6643. -#define	reg_tpsd_lpcr_len 3
  6644. -#define	reg_tpsd_lpcr_lsb 0
  6645. -#define xd_g_reg_ofsm_clk	0xA3D0
  6646. -#define	reg_ofsm_clk_pos 0
  6647. -#define	reg_ofsm_clk_len 3
  6648. -#define	reg_ofsm_clk_lsb 0
  6649. -#define xd_g_reg_fclk_cfg	0xA3D1
  6650. -#define	reg_fclk_cfg_pos 0
  6651. -#define	reg_fclk_cfg_len 1
  6652. -#define	reg_fclk_cfg_lsb 0
  6653. -#define xd_g_reg_fclk_idi	0xA3D1
  6654. -#define	reg_fclk_idi_pos 1
  6655. -#define	reg_fclk_idi_len 1
  6656. -#define	reg_fclk_idi_lsb 0
  6657. -#define xd_g_reg_fclk_odi	0xA3D1
  6658. -#define	reg_fclk_odi_pos 2
  6659. -#define	reg_fclk_odi_len 1
  6660. -#define	reg_fclk_odi_lsb 0
  6661. -#define xd_g_reg_fclk_rsd	0xA3D1
  6662. -#define	reg_fclk_rsd_pos 3
  6663. -#define	reg_fclk_rsd_len 1
  6664. -#define	reg_fclk_rsd_lsb 0
  6665. -#define xd_g_reg_fclk_vtb	0xA3D1
  6666. -#define	reg_fclk_vtb_pos 4
  6667. -#define	reg_fclk_vtb_len 1
  6668. -#define	reg_fclk_vtb_lsb 0
  6669. -#define xd_g_reg_fclk_cste	0xA3D1
  6670. -#define	reg_fclk_cste_pos 5
  6671. -#define	reg_fclk_cste_len 1
  6672. -#define	reg_fclk_cste_lsb 0
  6673. -#define xd_g_reg_fclk_mp2if	0xA3D1
  6674. -#define	reg_fclk_mp2if_pos 6
  6675. -#define	reg_fclk_mp2if_len 1
  6676. -#define	reg_fclk_mp2if_lsb 0
  6677. -#define xd_I2C_i2c_m_slave_addr	0xA400
  6678. -#define	i2c_m_slave_addr_pos 0
  6679. -#define	i2c_m_slave_addr_len 8
  6680. -#define	i2c_m_slave_addr_lsb 0
  6681. -#define xd_I2C_i2c_m_data1	0xA401
  6682. -#define	i2c_m_data1_pos 0
  6683. -#define	i2c_m_data1_len 8
  6684. -#define	i2c_m_data1_lsb 0
  6685. -#define xd_I2C_i2c_m_data2	0xA402
  6686. -#define	i2c_m_data2_pos 0
  6687. -#define	i2c_m_data2_len 8
  6688. -#define	i2c_m_data2_lsb 0
  6689. -#define xd_I2C_i2c_m_data3	0xA403
  6690. -#define	i2c_m_data3_pos 0
  6691. -#define	i2c_m_data3_len 8
  6692. -#define	i2c_m_data3_lsb 0
  6693. -#define xd_I2C_i2c_m_data4	0xA404
  6694. -#define	i2c_m_data4_pos 0
  6695. -#define	i2c_m_data4_len 8
  6696. -#define	i2c_m_data4_lsb 0
  6697. -#define xd_I2C_i2c_m_data5	0xA405
  6698. -#define	i2c_m_data5_pos 0
  6699. -#define	i2c_m_data5_len 8
  6700. -#define	i2c_m_data5_lsb 0
  6701. -#define xd_I2C_i2c_m_data6	0xA406
  6702. -#define	i2c_m_data6_pos 0
  6703. -#define	i2c_m_data6_len 8
  6704. -#define	i2c_m_data6_lsb 0
  6705. -#define xd_I2C_i2c_m_data7	0xA407
  6706. -#define	i2c_m_data7_pos 0
  6707. -#define	i2c_m_data7_len 8
  6708. -#define	i2c_m_data7_lsb 0
  6709. -#define xd_I2C_i2c_m_data8	0xA408
  6710. -#define	i2c_m_data8_pos 0
  6711. -#define	i2c_m_data8_len 8
  6712. -#define	i2c_m_data8_lsb 0
  6713. -#define xd_I2C_i2c_m_data9	0xA409
  6714. -#define	i2c_m_data9_pos 0
  6715. -#define	i2c_m_data9_len 8
  6716. -#define	i2c_m_data9_lsb 0
  6717. -#define xd_I2C_i2c_m_data10	0xA40A
  6718. -#define	i2c_m_data10_pos 0
  6719. -#define	i2c_m_data10_len 8
  6720. -#define	i2c_m_data10_lsb 0
  6721. -#define xd_I2C_i2c_m_data11	0xA40B
  6722. -#define	i2c_m_data11_pos 0
  6723. -#define	i2c_m_data11_len 8
  6724. -#define	i2c_m_data11_lsb 0
  6725. -#define xd_I2C_i2c_m_cmd_rw	0xA40C
  6726. -#define	i2c_m_cmd_rw_pos 0
  6727. -#define	i2c_m_cmd_rw_len 1
  6728. -#define	i2c_m_cmd_rw_lsb 0
  6729. -#define xd_I2C_i2c_m_cmd_rwlen	0xA40C
  6730. -#define	i2c_m_cmd_rwlen_pos 3
  6731. -#define	i2c_m_cmd_rwlen_len 4
  6732. -#define	i2c_m_cmd_rwlen_lsb 0
  6733. -#define xd_I2C_i2c_m_status_cmd_exe	0xA40D
  6734. -#define	i2c_m_status_cmd_exe_pos 0
  6735. -#define	i2c_m_status_cmd_exe_len 1
  6736. -#define	i2c_m_status_cmd_exe_lsb 0
  6737. -#define xd_I2C_i2c_m_status_wdat_done	0xA40D
  6738. -#define	i2c_m_status_wdat_done_pos 1
  6739. -#define	i2c_m_status_wdat_done_len 1
  6740. -#define	i2c_m_status_wdat_done_lsb 0
  6741. -#define xd_I2C_i2c_m_status_wdat_fail	0xA40D
  6742. -#define	i2c_m_status_wdat_fail_pos 2
  6743. -#define	i2c_m_status_wdat_fail_len 1
  6744. -#define	i2c_m_status_wdat_fail_lsb 0
  6745. -#define xd_I2C_i2c_m_period	0xA40E
  6746. -#define	i2c_m_period_pos 0
  6747. -#define	i2c_m_period_len 8
  6748. -#define	i2c_m_period_lsb 0
  6749. -#define xd_I2C_i2c_m_reg_msb_lsb	0xA40F
  6750. -#define	i2c_m_reg_msb_lsb_pos 0
  6751. -#define	i2c_m_reg_msb_lsb_len 1
  6752. -#define	i2c_m_reg_msb_lsb_lsb 0
  6753. -#define xd_I2C_reg_ofdm_rst	0xA40F
  6754. -#define	reg_ofdm_rst_pos 1
  6755. -#define	reg_ofdm_rst_len 1
  6756. -#define	reg_ofdm_rst_lsb 0
  6757. -#define xd_I2C_reg_sample_period_on_tuner	0xA40F
  6758. -#define	reg_sample_period_on_tuner_pos 2
  6759. -#define	reg_sample_period_on_tuner_len 1
  6760. -#define	reg_sample_period_on_tuner_lsb 0
  6761. -#define xd_I2C_reg_rst_i2c	0xA40F
  6762. -#define	reg_rst_i2c_pos 3
  6763. -#define	reg_rst_i2c_len 1
  6764. -#define	reg_rst_i2c_lsb 0
  6765. -#define xd_I2C_reg_ofdm_rst_en	0xA40F
  6766. -#define	reg_ofdm_rst_en_pos 4
  6767. -#define	reg_ofdm_rst_en_len 1
  6768. -#define	reg_ofdm_rst_en_lsb 0
  6769. -#define xd_I2C_reg_tuner_sda_sync_on	0xA40F
  6770. -#define	reg_tuner_sda_sync_on_pos 5
  6771. -#define	reg_tuner_sda_sync_on_len 1
  6772. -#define	reg_tuner_sda_sync_on_lsb 0
  6773. -#define xd_p_mp2if_data_access_disable_ofsm	0xA500
  6774. -#define	mp2if_data_access_disable_ofsm_pos 0
  6775. -#define	mp2if_data_access_disable_ofsm_len 1
  6776. -#define	mp2if_data_access_disable_ofsm_lsb 0
  6777. -#define xd_p_reg_mp2_sw_rst_ofsm	0xA500
  6778. -#define	reg_mp2_sw_rst_ofsm_pos 1
  6779. -#define	reg_mp2_sw_rst_ofsm_len 1
  6780. -#define	reg_mp2_sw_rst_ofsm_lsb 0
  6781. -#define xd_p_reg_mp2if_clk_en_ofsm	0xA500
  6782. -#define	reg_mp2if_clk_en_ofsm_pos 2
  6783. -#define	reg_mp2if_clk_en_ofsm_len 1
  6784. -#define	reg_mp2if_clk_en_ofsm_lsb 0
  6785. -#define xd_r_mp2if_sync_byte_locked	0xA500
  6786. -#define	mp2if_sync_byte_locked_pos 3
  6787. -#define	mp2if_sync_byte_locked_len 1
  6788. -#define	mp2if_sync_byte_locked_lsb 0
  6789. -#define xd_r_mp2if_ts_not_188	0xA500
  6790. -#define	mp2if_ts_not_188_pos 4
  6791. -#define	mp2if_ts_not_188_len 1
  6792. -#define	mp2if_ts_not_188_lsb 0
  6793. -#define xd_r_mp2if_psb_empty	0xA500
  6794. -#define	mp2if_psb_empty_pos 5
  6795. -#define	mp2if_psb_empty_len 1
  6796. -#define	mp2if_psb_empty_lsb 0
  6797. -#define xd_r_mp2if_psb_overflow	0xA500
  6798. -#define	mp2if_psb_overflow_pos 6
  6799. -#define	mp2if_psb_overflow_len 1
  6800. -#define	mp2if_psb_overflow_lsb 0
  6801. -#define xd_p_mp2if_keep_sf_sync_byte_ofsm	0xA500
  6802. -#define	mp2if_keep_sf_sync_byte_ofsm_pos 7
  6803. -#define	mp2if_keep_sf_sync_byte_ofsm_len 1
  6804. -#define	mp2if_keep_sf_sync_byte_ofsm_lsb 0
  6805. -#define xd_r_mp2if_psb_mp2if_num_pkt	0xA501
  6806. -#define	mp2if_psb_mp2if_num_pkt_pos 0
  6807. -#define	mp2if_psb_mp2if_num_pkt_len 6
  6808. -#define	mp2if_psb_mp2if_num_pkt_lsb 0
  6809. -#define xd_p_reg_mpeg_full_speed_ofsm	0xA501
  6810. -#define	reg_mpeg_full_speed_ofsm_pos 6
  6811. -#define	reg_mpeg_full_speed_ofsm_len 1
  6812. -#define	reg_mpeg_full_speed_ofsm_lsb 0
  6813. -#define xd_p_mp2if_mpeg_ser_mode_ofsm	0xA501
  6814. -#define	mp2if_mpeg_ser_mode_ofsm_pos 7
  6815. -#define	mp2if_mpeg_ser_mode_ofsm_len 1
  6816. -#define	mp2if_mpeg_ser_mode_ofsm_lsb 0
  6817. -#define xd_p_reg_sw_mon51	0xA600
  6818. -#define	reg_sw_mon51_pos 0
  6819. -#define	reg_sw_mon51_len 8
  6820. -#define	reg_sw_mon51_lsb 0
  6821. -#define xd_p_reg_top_pcsel	0xA601
  6822. -#define	reg_top_pcsel_pos 0
  6823. -#define	reg_top_pcsel_len 1
  6824. -#define	reg_top_pcsel_lsb 0
  6825. -#define xd_p_reg_top_rs232	0xA601
  6826. -#define	reg_top_rs232_pos 1
  6827. -#define	reg_top_rs232_len 1
  6828. -#define	reg_top_rs232_lsb 0
  6829. -#define xd_p_reg_top_pcout	0xA601
  6830. -#define	reg_top_pcout_pos 2
  6831. -#define	reg_top_pcout_len 1
  6832. -#define	reg_top_pcout_lsb 0
  6833. -#define xd_p_reg_top_debug	0xA601
  6834. -#define	reg_top_debug_pos 3
  6835. -#define	reg_top_debug_len 1
  6836. -#define	reg_top_debug_lsb 0
  6837. -#define xd_p_reg_top_adcdly	0xA601
  6838. -#define	reg_top_adcdly_pos 4
  6839. -#define	reg_top_adcdly_len 2
  6840. -#define	reg_top_adcdly_lsb 0
  6841. -#define xd_p_reg_top_pwrdw	0xA601
  6842. -#define	reg_top_pwrdw_pos 6
  6843. -#define	reg_top_pwrdw_len 1
  6844. -#define	reg_top_pwrdw_lsb 0
  6845. -#define xd_p_reg_top_pwrdw_inv	0xA601
  6846. -#define	reg_top_pwrdw_inv_pos 7
  6847. -#define	reg_top_pwrdw_inv_len 1
  6848. -#define	reg_top_pwrdw_inv_lsb 0
  6849. -#define xd_p_reg_top_int_inv	0xA602
  6850. -#define	reg_top_int_inv_pos 0
  6851. -#define	reg_top_int_inv_len 1
  6852. -#define	reg_top_int_inv_lsb 0
  6853. -#define xd_p_reg_top_dio_sel	0xA602
  6854. -#define	reg_top_dio_sel_pos 1
  6855. -#define	reg_top_dio_sel_len 1
  6856. -#define	reg_top_dio_sel_lsb 0
  6857. -#define xd_p_reg_top_gpioon0	0xA603
  6858. -#define	reg_top_gpioon0_pos 0
  6859. -#define	reg_top_gpioon0_len 1
  6860. -#define	reg_top_gpioon0_lsb 0
  6861. -#define xd_p_reg_top_gpioon1	0xA603
  6862. -#define	reg_top_gpioon1_pos 1
  6863. -#define	reg_top_gpioon1_len 1
  6864. -#define	reg_top_gpioon1_lsb 0
  6865. -#define xd_p_reg_top_gpioon2	0xA603
  6866. -#define	reg_top_gpioon2_pos 2
  6867. -#define	reg_top_gpioon2_len 1
  6868. -#define	reg_top_gpioon2_lsb 0
  6869. -#define xd_p_reg_top_gpioon3	0xA603
  6870. -#define	reg_top_gpioon3_pos 3
  6871. -#define	reg_top_gpioon3_len 1
  6872. -#define	reg_top_gpioon3_lsb 0
  6873. -#define xd_p_reg_top_lockon1	0xA603
  6874. -#define	reg_top_lockon1_pos 4
  6875. -#define	reg_top_lockon1_len 1
  6876. -#define	reg_top_lockon1_lsb 0
  6877. -#define xd_p_reg_top_lockon2	0xA603
  6878. -#define	reg_top_lockon2_pos 5
  6879. -#define	reg_top_lockon2_len 1
  6880. -#define	reg_top_lockon2_lsb 0
  6881. -#define xd_p_reg_top_gpioo0	0xA604
  6882. -#define	reg_top_gpioo0_pos 0
  6883. -#define	reg_top_gpioo0_len 1
  6884. -#define	reg_top_gpioo0_lsb 0
  6885. -#define xd_p_reg_top_gpioo1	0xA604
  6886. -#define	reg_top_gpioo1_pos 1
  6887. -#define	reg_top_gpioo1_len 1
  6888. -#define	reg_top_gpioo1_lsb 0
  6889. -#define xd_p_reg_top_gpioo2	0xA604
  6890. -#define	reg_top_gpioo2_pos 2
  6891. -#define	reg_top_gpioo2_len 1
  6892. -#define	reg_top_gpioo2_lsb 0
  6893. -#define xd_p_reg_top_gpioo3	0xA604
  6894. -#define	reg_top_gpioo3_pos 3
  6895. -#define	reg_top_gpioo3_len 1
  6896. -#define	reg_top_gpioo3_lsb 0
  6897. -#define xd_p_reg_top_lock1	0xA604
  6898. -#define	reg_top_lock1_pos 4
  6899. -#define	reg_top_lock1_len 1
  6900. -#define	reg_top_lock1_lsb 0
  6901. -#define xd_p_reg_top_lock2	0xA604
  6902. -#define	reg_top_lock2_pos 5
  6903. -#define	reg_top_lock2_len 1
  6904. -#define	reg_top_lock2_lsb 0
  6905. -#define xd_p_reg_top_gpioen0	0xA605
  6906. -#define	reg_top_gpioen0_pos 0
  6907. -#define	reg_top_gpioen0_len 1
  6908. -#define	reg_top_gpioen0_lsb 0
  6909. -#define xd_p_reg_top_gpioen1	0xA605
  6910. -#define	reg_top_gpioen1_pos 1
  6911. -#define	reg_top_gpioen1_len 1
  6912. -#define	reg_top_gpioen1_lsb 0
  6913. -#define xd_p_reg_top_gpioen2	0xA605
  6914. -#define	reg_top_gpioen2_pos 2
  6915. -#define	reg_top_gpioen2_len 1
  6916. -#define	reg_top_gpioen2_lsb 0
  6917. -#define xd_p_reg_top_gpioen3	0xA605
  6918. -#define	reg_top_gpioen3_pos 3
  6919. -#define	reg_top_gpioen3_len 1
  6920. -#define	reg_top_gpioen3_lsb 0
  6921. -#define xd_p_reg_top_locken1	0xA605
  6922. -#define	reg_top_locken1_pos 4
  6923. -#define	reg_top_locken1_len 1
  6924. -#define	reg_top_locken1_lsb 0
  6925. -#define xd_p_reg_top_locken2	0xA605
  6926. -#define	reg_top_locken2_pos 5
  6927. -#define	reg_top_locken2_len 1
  6928. -#define	reg_top_locken2_lsb 0
  6929. -#define xd_r_reg_top_gpioi0	0xA606
  6930. -#define	reg_top_gpioi0_pos 0
  6931. -#define	reg_top_gpioi0_len 1
  6932. -#define	reg_top_gpioi0_lsb 0
  6933. -#define xd_r_reg_top_gpioi1	0xA606
  6934. -#define	reg_top_gpioi1_pos 1
  6935. -#define	reg_top_gpioi1_len 1
  6936. -#define	reg_top_gpioi1_lsb 0
  6937. -#define xd_r_reg_top_gpioi2	0xA606
  6938. -#define	reg_top_gpioi2_pos 2
  6939. -#define	reg_top_gpioi2_len 1
  6940. -#define	reg_top_gpioi2_lsb 0
  6941. -#define xd_r_reg_top_gpioi3	0xA606
  6942. -#define	reg_top_gpioi3_pos 3
  6943. -#define	reg_top_gpioi3_len 1
  6944. -#define	reg_top_gpioi3_lsb 0
  6945. -#define xd_r_reg_top_locki1	0xA606
  6946. -#define	reg_top_locki1_pos 4
  6947. -#define	reg_top_locki1_len 1
  6948. -#define	reg_top_locki1_lsb 0
  6949. -#define xd_r_reg_top_locki2	0xA606
  6950. -#define	reg_top_locki2_pos 5
  6951. -#define	reg_top_locki2_len 1
  6952. -#define	reg_top_locki2_lsb 0
  6953. -#define xd_p_reg_dummy_7_0	0xA608
  6954. -#define	reg_dummy_7_0_pos 0
  6955. -#define	reg_dummy_7_0_len 8
  6956. -#define	reg_dummy_7_0_lsb 0
  6957. -#define xd_p_reg_dummy_15_8	0xA609
  6958. -#define	reg_dummy_15_8_pos 0
  6959. -#define	reg_dummy_15_8_len 8
  6960. -#define	reg_dummy_15_8_lsb 8
  6961. -#define xd_p_reg_dummy_23_16	0xA60A
  6962. -#define	reg_dummy_23_16_pos 0
  6963. -#define	reg_dummy_23_16_len 8
  6964. -#define	reg_dummy_23_16_lsb 16
  6965. -#define xd_p_reg_dummy_31_24	0xA60B
  6966. -#define	reg_dummy_31_24_pos 0
  6967. -#define	reg_dummy_31_24_len 8
  6968. -#define	reg_dummy_31_24_lsb 24
  6969. -#define xd_p_reg_dummy_39_32	0xA60C
  6970. -#define	reg_dummy_39_32_pos 0
  6971. -#define	reg_dummy_39_32_len 8
  6972. -#define	reg_dummy_39_32_lsb 32
  6973. -#define xd_p_reg_dummy_47_40	0xA60D
  6974. -#define	reg_dummy_47_40_pos 0
  6975. -#define	reg_dummy_47_40_len 8
  6976. -#define	reg_dummy_47_40_lsb 40
  6977. -#define xd_p_reg_dummy_55_48	0xA60E
  6978. -#define	reg_dummy_55_48_pos 0
  6979. -#define	reg_dummy_55_48_len 8
  6980. -#define	reg_dummy_55_48_lsb 48
  6981. -#define xd_p_reg_dummy_63_56	0xA60F
  6982. -#define	reg_dummy_63_56_pos 0
  6983. -#define	reg_dummy_63_56_len 8
  6984. -#define	reg_dummy_63_56_lsb 56
  6985. -#define xd_p_reg_dummy_71_64	0xA610
  6986. -#define	reg_dummy_71_64_pos 0
  6987. -#define	reg_dummy_71_64_len 8
  6988. -#define	reg_dummy_71_64_lsb 64
  6989. -#define xd_p_reg_dummy_79_72	0xA611
  6990. -#define	reg_dummy_79_72_pos 0
  6991. -#define	reg_dummy_79_72_len 8
  6992. -#define	reg_dummy_79_72_lsb 72
  6993. -#define xd_p_reg_dummy_87_80	0xA612
  6994. -#define	reg_dummy_87_80_pos 0
  6995. -#define	reg_dummy_87_80_len 8
  6996. -#define	reg_dummy_87_80_lsb 80
  6997. -#define xd_p_reg_dummy_95_88	0xA613
  6998. -#define	reg_dummy_95_88_pos 0
  6999. -#define	reg_dummy_95_88_len 8
  7000. -#define	reg_dummy_95_88_lsb 88
  7001. -#define xd_p_reg_dummy_103_96	0xA614
  7002. -#define	reg_dummy_103_96_pos 0
  7003. -#define	reg_dummy_103_96_len 8
  7004. -#define	reg_dummy_103_96_lsb 96
  7005. -
  7006. -#define xd_p_reg_unplug_flag	0xA615
  7007. -#define	reg_unplug_flag_pos 0
  7008. -#define	reg_unplug_flag_len 1
  7009. -#define	reg_unplug_flag_lsb 104
  7010. -
  7011. -#define xd_p_reg_api_dca_stes_request   0xA615
  7012. -#define reg_api_dca_stes_request_pos 1
  7013. -#define reg_api_dca_stes_request_len 1
  7014. -#define reg_api_dca_stes_request_lsb 0
  7015. -
  7016. -#define xd_p_reg_back_to_dca_flag	0xA615
  7017. -#define	reg_back_to_dca_flag_pos 2
  7018. -#define	reg_back_to_dca_flag_len 1
  7019. -#define	reg_back_to_dca_flag_lsb 106
  7020. -
  7021. -#define xd_p_reg_api_retrain_request    0xA615
  7022. -#define reg_api_retrain_request_pos 3
  7023. -#define reg_api_retrain_request_len 1
  7024. -#define reg_api_retrain_request_lsb 0
  7025. -
  7026. -#define xd_p_reg_Dyn_Top_Try_flag	0xA615
  7027. -#define	reg_Dyn_Top_Try_flag_pos 3
  7028. -#define	reg_Dyn_Top_Try_flag_len 1
  7029. -#define	reg_Dyn_Top_Try_flag_lsb 107
  7030. -
  7031. -#define xd_p_reg_API_retrain_freeze_flag	0xA615
  7032. -#define	reg_API_retrain_freeze_flag_pos 4
  7033. -#define	reg_API_retrain_freeze_flag_len 1
  7034. -#define	reg_API_retrain_freeze_flag_lsb 108
  7035. -
  7036. -#define xd_p_reg_dummy_111_104	0xA615
  7037. -#define	reg_dummy_111_104_pos 0
  7038. -#define	reg_dummy_111_104_len 8
  7039. -#define	reg_dummy_111_104_lsb 104
  7040. -#define xd_p_reg_dummy_119_112	0xA616
  7041. -#define	reg_dummy_119_112_pos 0
  7042. -#define	reg_dummy_119_112_len 8
  7043. -#define	reg_dummy_119_112_lsb 112
  7044. -#define xd_p_reg_dummy_127_120	0xA617
  7045. -#define	reg_dummy_127_120_pos 0
  7046. -#define	reg_dummy_127_120_len 8
  7047. -#define	reg_dummy_127_120_lsb 120
  7048. -#define xd_p_reg_dummy_135_128	0xA618
  7049. -#define	reg_dummy_135_128_pos 0
  7050. -#define	reg_dummy_135_128_len 8
  7051. -#define	reg_dummy_135_128_lsb 128
  7052. -
  7053. -#define xd_p_reg_dummy_143_136	0xA619
  7054. -#define	reg_dummy_143_136_pos 0
  7055. -#define	reg_dummy_143_136_len 8
  7056. -#define	reg_dummy_143_136_lsb 136
  7057. -
  7058. -#define xd_p_reg_CCIR_dis	0xA619
  7059. -#define	reg_CCIR_dis_pos 0
  7060. -#define	reg_CCIR_dis_len 1
  7061. -#define	reg_CCIR_dis_lsb 0
  7062. -
  7063. -#define xd_p_reg_dummy_151_144	0xA61A
  7064. -#define	reg_dummy_151_144_pos 0
  7065. -#define	reg_dummy_151_144_len 8
  7066. -#define	reg_dummy_151_144_lsb 144
  7067. -
  7068. -#define xd_p_reg_dummy_159_152	0xA61B
  7069. -#define	reg_dummy_159_152_pos 0
  7070. -#define	reg_dummy_159_152_len 8
  7071. -#define	reg_dummy_159_152_lsb 152
  7072. -
  7073. -#define xd_p_reg_dummy_167_160	0xA61C
  7074. -#define	reg_dummy_167_160_pos 0
  7075. -#define	reg_dummy_167_160_len 8
  7076. -#define	reg_dummy_167_160_lsb 160
  7077. -
  7078. -#define xd_p_reg_dummy_175_168	0xA61D
  7079. -#define	reg_dummy_175_168_pos 0
  7080. -#define	reg_dummy_175_168_len 8
  7081. -#define	reg_dummy_175_168_lsb 168
  7082. -
  7083. -#define xd_p_reg_dummy_183_176	0xA61E
  7084. -#define	reg_dummy_183_176_pos 0
  7085. -#define	reg_dummy_183_176_len 8
  7086. -#define	reg_dummy_183_176_lsb 176
  7087. -
  7088. -#define xd_p_reg_ofsm_read_rbc_en  0xA61E
  7089. -#define reg_ofsm_read_rbc_en_pos 2
  7090. -#define reg_ofsm_read_rbc_en_len 1
  7091. -#define reg_ofsm_read_rbc_en_lsb 0
  7092. -
  7093. -#define xd_p_reg_ce_filter_selection_dis  0xA61E
  7094. -#define reg_ce_filter_selection_dis_pos 1
  7095. -#define reg_ce_filter_selection_dis_len 1
  7096. -#define reg_ce_filter_selection_dis_lsb 0
  7097. -
  7098. -#define xd_p_reg_OFSM_version_control_7_0  0xA611
  7099. -#define reg_OFSM_version_control_7_0_pos 0
  7100. -#define reg_OFSM_version_control_7_0_len 8
  7101. -#define reg_OFSM_version_control_7_0_lsb 0
  7102. -
  7103. -#define xd_p_reg_OFSM_version_control_15_8  0xA61F
  7104. -#define reg_OFSM_version_control_15_8_pos 0
  7105. -#define reg_OFSM_version_control_15_8_len 8
  7106. -#define reg_OFSM_version_control_15_8_lsb 0
  7107. -
  7108. -#define xd_p_reg_OFSM_version_control_23_16  0xA620
  7109. -#define reg_OFSM_version_control_23_16_pos 0
  7110. -#define reg_OFSM_version_control_23_16_len 8
  7111. -#define reg_OFSM_version_control_23_16_lsb 0
  7112. -
  7113. -#define xd_p_reg_dummy_191_184	0xA61F
  7114. -#define	reg_dummy_191_184_pos 0
  7115. -#define	reg_dummy_191_184_len 8
  7116. -#define	reg_dummy_191_184_lsb 184
  7117. -
  7118. -#define xd_p_reg_dummy_199_192	0xA620
  7119. -#define	reg_dummy_199_192_pos 0
  7120. -#define	reg_dummy_199_192_len 8
  7121. -#define	reg_dummy_199_192_lsb 192
  7122. -
  7123. -#define xd_p_reg_ce_en	0xABC0
  7124. -#define	reg_ce_en_pos 0
  7125. -#define	reg_ce_en_len 1
  7126. -#define	reg_ce_en_lsb 0
  7127. -#define xd_p_reg_ce_fctrl_en	0xABC0
  7128. -#define	reg_ce_fctrl_en_pos 1
  7129. -#define	reg_ce_fctrl_en_len 1
  7130. -#define	reg_ce_fctrl_en_lsb 0
  7131. -#define xd_p_reg_ce_fste_tdi	0xABC0
  7132. -#define	reg_ce_fste_tdi_pos 2
  7133. -#define	reg_ce_fste_tdi_len 1
  7134. -#define	reg_ce_fste_tdi_lsb 0
  7135. -#define xd_p_reg_ce_dynamic	0xABC0
  7136. -#define	reg_ce_dynamic_pos 3
  7137. -#define	reg_ce_dynamic_len 1
  7138. -#define	reg_ce_dynamic_lsb 0
  7139. -#define xd_p_reg_ce_conf	0xABC0
  7140. -#define	reg_ce_conf_pos 4
  7141. -#define	reg_ce_conf_len 2
  7142. -#define	reg_ce_conf_lsb 0
  7143. -#define xd_p_reg_ce_dyn12	0xABC0
  7144. -#define	reg_ce_dyn12_pos 6
  7145. -#define	reg_ce_dyn12_len 1
  7146. -#define	reg_ce_dyn12_lsb 0
  7147. -#define xd_p_reg_ce_derot_en	0xABC0
  7148. -#define	reg_ce_derot_en_pos 7
  7149. -#define	reg_ce_derot_en_len 1
  7150. -#define	reg_ce_derot_en_lsb 0
  7151. -#define xd_p_reg_ce_dynamic_th_7_0	0xABC1
  7152. -#define	reg_ce_dynamic_th_7_0_pos 0
  7153. -#define	reg_ce_dynamic_th_7_0_len 8
  7154. -#define	reg_ce_dynamic_th_7_0_lsb 0
  7155. -#define xd_p_reg_ce_dynamic_th_15_8	0xABC2
  7156. -#define	reg_ce_dynamic_th_15_8_pos 0
  7157. -#define	reg_ce_dynamic_th_15_8_len 8
  7158. -#define	reg_ce_dynamic_th_15_8_lsb 8
  7159. -#define xd_p_reg_ce_s1	0xABC3
  7160. -#define	reg_ce_s1_pos 0
  7161. -#define	reg_ce_s1_len 5
  7162. -#define	reg_ce_s1_lsb 0
  7163. -#define xd_p_reg_ce_var_forced_value	0xABC3
  7164. -#define	reg_ce_var_forced_value_pos 5
  7165. -#define	reg_ce_var_forced_value_len 3
  7166. -#define	reg_ce_var_forced_value_lsb 0
  7167. -#define xd_p_reg_ce_data_im_7_0	0xABC4
  7168. -#define	reg_ce_data_im_7_0_pos 0
  7169. -#define	reg_ce_data_im_7_0_len 8
  7170. -#define	reg_ce_data_im_7_0_lsb 0
  7171. -#define xd_p_reg_ce_data_im_8	0xABC5
  7172. -#define	reg_ce_data_im_8_pos 0
  7173. -#define	reg_ce_data_im_8_len 1
  7174. -#define	reg_ce_data_im_8_lsb 0
  7175. -#define xd_p_reg_ce_data_re_6_0	0xABC5
  7176. -#define	reg_ce_data_re_6_0_pos 1
  7177. -#define	reg_ce_data_re_6_0_len 7
  7178. -#define	reg_ce_data_re_6_0_lsb 0
  7179. -#define xd_p_reg_ce_data_re_8_7	0xABC6
  7180. -#define	reg_ce_data_re_8_7_pos 0
  7181. -#define	reg_ce_data_re_8_7_len 2
  7182. -#define	reg_ce_data_re_8_7_lsb 7
  7183. -#define xd_p_reg_ce_tone_5_0	0xABC6
  7184. -#define	reg_ce_tone_5_0_pos 2
  7185. -#define	reg_ce_tone_5_0_len 6
  7186. -#define	reg_ce_tone_5_0_lsb 0
  7187. -#define xd_p_reg_ce_tone_12_6	0xABC7
  7188. -#define	reg_ce_tone_12_6_pos 0
  7189. -#define	reg_ce_tone_12_6_len 7
  7190. -#define	reg_ce_tone_12_6_lsb 6
  7191. -#define xd_p_reg_ce_centroid_drift_th	0xABC8
  7192. -#define	reg_ce_centroid_drift_th_pos 0
  7193. -#define	reg_ce_centroid_drift_th_len 8
  7194. -#define	reg_ce_centroid_drift_th_lsb 0
  7195. -#define xd_p_reg_ce_centroid_count_max	0xABC9
  7196. -#define	reg_ce_centroid_count_max_pos 0
  7197. -#define	reg_ce_centroid_count_max_len 4
  7198. -#define	reg_ce_centroid_count_max_lsb 0
  7199. -#define xd_p_reg_ce_centroid_bias_inc_7_0	0xABCA
  7200. -#define	reg_ce_centroid_bias_inc_7_0_pos 0
  7201. -#define	reg_ce_centroid_bias_inc_7_0_len 8
  7202. -#define	reg_ce_centroid_bias_inc_7_0_lsb 0
  7203. -#define xd_p_reg_ce_centroid_bias_inc_8	0xABCB
  7204. -#define	reg_ce_centroid_bias_inc_8_pos 0
  7205. -#define	reg_ce_centroid_bias_inc_8_len 1
  7206. -#define	reg_ce_centroid_bias_inc_8_lsb 0
  7207. -#define xd_p_reg_ce_var_th0_7_0	0xABCC
  7208. -#define	reg_ce_var_th0_7_0_pos 0
  7209. -#define	reg_ce_var_th0_7_0_len 8
  7210. -#define	reg_ce_var_th0_7_0_lsb 0
  7211. -#define xd_p_reg_ce_var_th0_15_8	0xABCD
  7212. -#define	reg_ce_var_th0_15_8_pos 0
  7213. -#define	reg_ce_var_th0_15_8_len 8
  7214. -#define	reg_ce_var_th0_15_8_lsb 8
  7215. -#define xd_p_reg_ce_var_th1_7_0	0xABCE
  7216. -#define	reg_ce_var_th1_7_0_pos 0
  7217. -#define	reg_ce_var_th1_7_0_len 8
  7218. -#define	reg_ce_var_th1_7_0_lsb 0
  7219. -#define xd_p_reg_ce_var_th1_15_8	0xABCF
  7220. -#define	reg_ce_var_th1_15_8_pos 0
  7221. -#define	reg_ce_var_th1_15_8_len 8
  7222. -#define	reg_ce_var_th1_15_8_lsb 8
  7223. -#define xd_p_reg_ce_var_th2_7_0	0xABD0
  7224. -#define	reg_ce_var_th2_7_0_pos 0
  7225. -#define	reg_ce_var_th2_7_0_len 8
  7226. -#define	reg_ce_var_th2_7_0_lsb 0
  7227. -#define xd_p_reg_ce_var_th2_15_8	0xABD1
  7228. -#define	reg_ce_var_th2_15_8_pos 0
  7229. -#define	reg_ce_var_th2_15_8_len 8
  7230. -#define	reg_ce_var_th2_15_8_lsb 8
  7231. -#define xd_p_reg_ce_var_th3_7_0	0xABD2
  7232. -#define	reg_ce_var_th3_7_0_pos 0
  7233. -#define	reg_ce_var_th3_7_0_len 8
  7234. -#define	reg_ce_var_th3_7_0_lsb 0
  7235. -#define xd_p_reg_ce_var_th3_15_8	0xABD3
  7236. -#define	reg_ce_var_th3_15_8_pos 0
  7237. -#define	reg_ce_var_th3_15_8_len 8
  7238. -#define	reg_ce_var_th3_15_8_lsb 8
  7239. -#define xd_p_reg_ce_var_th4_7_0	0xABD4
  7240. -#define	reg_ce_var_th4_7_0_pos 0
  7241. -#define	reg_ce_var_th4_7_0_len 8
  7242. -#define	reg_ce_var_th4_7_0_lsb 0
  7243. -#define xd_p_reg_ce_var_th4_15_8	0xABD5
  7244. -#define	reg_ce_var_th4_15_8_pos 0
  7245. -#define	reg_ce_var_th4_15_8_len 8
  7246. -#define	reg_ce_var_th4_15_8_lsb 8
  7247. -#define xd_p_reg_ce_var_th5_7_0	0xABD6
  7248. -#define	reg_ce_var_th5_7_0_pos 0
  7249. -#define	reg_ce_var_th5_7_0_len 8
  7250. -#define	reg_ce_var_th5_7_0_lsb 0
  7251. -#define xd_p_reg_ce_var_th5_15_8	0xABD7
  7252. -#define	reg_ce_var_th5_15_8_pos 0
  7253. -#define	reg_ce_var_th5_15_8_len 8
  7254. -#define	reg_ce_var_th5_15_8_lsb 8
  7255. -#define xd_p_reg_ce_var_th6_7_0	0xABD8
  7256. -#define	reg_ce_var_th6_7_0_pos 0
  7257. -#define	reg_ce_var_th6_7_0_len 8
  7258. -#define	reg_ce_var_th6_7_0_lsb 0
  7259. -#define xd_p_reg_ce_var_th6_15_8	0xABD9
  7260. -#define	reg_ce_var_th6_15_8_pos 0
  7261. -#define	reg_ce_var_th6_15_8_len 8
  7262. -#define	reg_ce_var_th6_15_8_lsb 8
  7263. -#define xd_p_reg_ce_fctrl_reset	0xABDA
  7264. -#define	reg_ce_fctrl_reset_pos 0
  7265. -#define	reg_ce_fctrl_reset_len 1
  7266. -#define	reg_ce_fctrl_reset_lsb 0
  7267. -#define xd_p_reg_ce_cent_auto_clr_en	0xABDA
  7268. -#define	reg_ce_cent_auto_clr_en_pos 1
  7269. -#define	reg_ce_cent_auto_clr_en_len 1
  7270. -#define	reg_ce_cent_auto_clr_en_lsb 0
  7271. -#define xd_p_reg_ce_fctrl_auto_reset_en	0xABDA
  7272. -#define	reg_ce_fctrl_auto_reset_en_pos 2
  7273. -#define	reg_ce_fctrl_auto_reset_en_len 1
  7274. -#define	reg_ce_fctrl_auto_reset_en_lsb 0
  7275. -#define xd_p_reg_ce_var_forced_en	0xABDA
  7276. -#define	reg_ce_var_forced_en_pos 3
  7277. -#define	reg_ce_var_forced_en_len 1
  7278. -#define	reg_ce_var_forced_en_lsb 0
  7279. -#define xd_p_reg_ce_cent_forced_en	0xABDA
  7280. -#define	reg_ce_cent_forced_en_pos 4
  7281. -#define	reg_ce_cent_forced_en_len 1
  7282. -#define	reg_ce_cent_forced_en_lsb 0
  7283. -#define xd_p_reg_ce_var_max	0xABDA
  7284. -#define	reg_ce_var_max_pos 5
  7285. -#define	reg_ce_var_max_len 3
  7286. -#define	reg_ce_var_max_lsb 0
  7287. -#define xd_p_reg_ce_cent_forced_value_7_0	0xABDB
  7288. -#define	reg_ce_cent_forced_value_7_0_pos 0
  7289. -#define	reg_ce_cent_forced_value_7_0_len 8
  7290. -#define	reg_ce_cent_forced_value_7_0_lsb 0
  7291. -#define xd_p_reg_ce_cent_forced_value_11_8	0xABDC
  7292. -#define	reg_ce_cent_forced_value_11_8_pos 0
  7293. -#define	reg_ce_cent_forced_value_11_8_len 4
  7294. -#define	reg_ce_cent_forced_value_11_8_lsb 8
  7295. -#define xd_p_reg_ce_fctrl_rd	0xABDD
  7296. -#define	reg_ce_fctrl_rd_pos 0
  7297. -#define	reg_ce_fctrl_rd_len 1
  7298. -#define	reg_ce_fctrl_rd_lsb 0
  7299. -#define xd_p_reg_ce_centroid_max_6_0	0xABDD
  7300. -#define	reg_ce_centroid_max_6_0_pos 1
  7301. -#define	reg_ce_centroid_max_6_0_len 7
  7302. -#define	reg_ce_centroid_max_6_0_lsb 0
  7303. -#define xd_p_reg_ce_centroid_max_11_7	0xABDE
  7304. -#define	reg_ce_centroid_max_11_7_pos 0
  7305. -#define	reg_ce_centroid_max_11_7_len 5
  7306. -#define	reg_ce_centroid_max_11_7_lsb 7
  7307. -#define xd_p_reg_ce_var	0xABDF
  7308. -#define	reg_ce_var_pos 0
  7309. -#define	reg_ce_var_len 3
  7310. -#define	reg_ce_var_lsb 0
  7311. -#define xd_p_reg_ce_fctrl_rdy	0xABDF
  7312. -#define	reg_ce_fctrl_rdy_pos 3
  7313. -#define	reg_ce_fctrl_rdy_len 1
  7314. -#define	reg_ce_fctrl_rdy_lsb 0
  7315. -#define xd_p_reg_ce_centroid_out_3_0	0xABDF
  7316. -#define	reg_ce_centroid_out_3_0_pos 4
  7317. -#define	reg_ce_centroid_out_3_0_len 4
  7318. -#define	reg_ce_centroid_out_3_0_lsb 0
  7319. -#define xd_p_reg_ce_centroid_out_11_4	0xABE0
  7320. -#define	reg_ce_centroid_out_11_4_pos 0
  7321. -#define	reg_ce_centroid_out_11_4_len 8
  7322. -#define	reg_ce_centroid_out_11_4_lsb 4
  7323. -#define xd_p_reg_ce_bias_7_0	0xABE1
  7324. -#define	reg_ce_bias_7_0_pos 0
  7325. -#define	reg_ce_bias_7_0_len 8
  7326. -#define	reg_ce_bias_7_0_lsb 0
  7327. -#define xd_p_reg_ce_bias_11_8	0xABE2
  7328. -#define	reg_ce_bias_11_8_pos 0
  7329. -#define	reg_ce_bias_11_8_len 4
  7330. -#define	reg_ce_bias_11_8_lsb 8
  7331. -#define xd_p_reg_ce_m1_3_0	0xABE2
  7332. -#define	reg_ce_m1_3_0_pos 4
  7333. -#define	reg_ce_m1_3_0_len 4
  7334. -#define	reg_ce_m1_3_0_lsb 0
  7335. -#define xd_p_reg_ce_m1_11_4	0xABE3
  7336. -#define	reg_ce_m1_11_4_pos 0
  7337. -#define	reg_ce_m1_11_4_len 8
  7338. -#define	reg_ce_m1_11_4_lsb 4
  7339. -#define xd_p_reg_ce_rh0_7_0	0xABE4
  7340. -#define	reg_ce_rh0_7_0_pos 0
  7341. -#define	reg_ce_rh0_7_0_len 8
  7342. -#define	reg_ce_rh0_7_0_lsb 0
  7343. -#define xd_p_reg_ce_rh0_15_8	0xABE5
  7344. -#define	reg_ce_rh0_15_8_pos 0
  7345. -#define	reg_ce_rh0_15_8_len 8
  7346. -#define	reg_ce_rh0_15_8_lsb 8
  7347. -#define xd_p_reg_ce_rh0_23_16	0xABE6
  7348. -#define	reg_ce_rh0_23_16_pos 0
  7349. -#define	reg_ce_rh0_23_16_len 8
  7350. -#define	reg_ce_rh0_23_16_lsb 16
  7351. -#define xd_p_reg_ce_rh0_31_24	0xABE7
  7352. -#define	reg_ce_rh0_31_24_pos 0
  7353. -#define	reg_ce_rh0_31_24_len 8
  7354. -#define	reg_ce_rh0_31_24_lsb 24
  7355. -#define xd_p_reg_ce_rh3_real_7_0	0xABE8
  7356. -#define	reg_ce_rh3_real_7_0_pos 0
  7357. -#define	reg_ce_rh3_real_7_0_len 8
  7358. -#define	reg_ce_rh3_real_7_0_lsb 0
  7359. -#define xd_p_reg_ce_rh3_real_15_8	0xABE9
  7360. -#define	reg_ce_rh3_real_15_8_pos 0
  7361. -#define	reg_ce_rh3_real_15_8_len 8
  7362. -#define	reg_ce_rh3_real_15_8_lsb 8
  7363. -#define xd_p_reg_ce_rh3_real_23_16	0xABEA
  7364. -#define	reg_ce_rh3_real_23_16_pos 0
  7365. -#define	reg_ce_rh3_real_23_16_len 8
  7366. -#define	reg_ce_rh3_real_23_16_lsb 16
  7367. -#define xd_p_reg_ce_rh3_real_31_24	0xABEB
  7368. -#define	reg_ce_rh3_real_31_24_pos 0
  7369. -#define	reg_ce_rh3_real_31_24_len 8
  7370. -#define	reg_ce_rh3_real_31_24_lsb 24
  7371. -#define xd_p_reg_ce_rh3_imag_7_0	0xABEC
  7372. -#define	reg_ce_rh3_imag_7_0_pos 0
  7373. -#define	reg_ce_rh3_imag_7_0_len 8
  7374. -#define	reg_ce_rh3_imag_7_0_lsb 0
  7375. -#define xd_p_reg_ce_rh3_imag_15_8	0xABED
  7376. -#define	reg_ce_rh3_imag_15_8_pos 0
  7377. -#define	reg_ce_rh3_imag_15_8_len 8
  7378. -#define	reg_ce_rh3_imag_15_8_lsb 8
  7379. -#define xd_p_reg_ce_rh3_imag_23_16	0xABEE
  7380. -#define	reg_ce_rh3_imag_23_16_pos 0
  7381. -#define	reg_ce_rh3_imag_23_16_len 8
  7382. -#define	reg_ce_rh3_imag_23_16_lsb 16
  7383. -#define xd_p_reg_ce_rh3_imag_31_24	0xABEF
  7384. -#define	reg_ce_rh3_imag_31_24_pos 0
  7385. -#define	reg_ce_rh3_imag_31_24_len 8
  7386. -#define	reg_ce_rh3_imag_31_24_lsb 24
  7387. -#define xd_p_reg_feq_fix_eh2_7_0	0xABF0
  7388. -#define	reg_feq_fix_eh2_7_0_pos 0
  7389. -#define	reg_feq_fix_eh2_7_0_len 8
  7390. -#define	reg_feq_fix_eh2_7_0_lsb 0
  7391. -#define xd_p_reg_feq_fix_eh2_15_8	0xABF1
  7392. -#define	reg_feq_fix_eh2_15_8_pos 0
  7393. -#define	reg_feq_fix_eh2_15_8_len 8
  7394. -#define	reg_feq_fix_eh2_15_8_lsb 8
  7395. -#define xd_p_reg_feq_fix_eh2_23_16	0xABF2
  7396. -#define	reg_feq_fix_eh2_23_16_pos 0
  7397. -#define	reg_feq_fix_eh2_23_16_len 8
  7398. -#define	reg_feq_fix_eh2_23_16_lsb 16
  7399. -#define xd_p_reg_feq_fix_eh2_31_24	0xABF3
  7400. -#define	reg_feq_fix_eh2_31_24_pos 0
  7401. -#define	reg_feq_fix_eh2_31_24_len 8
  7402. -#define	reg_feq_fix_eh2_31_24_lsb 24
  7403. -#define xd_p_reg_ce_m2_central_7_0	0xABF4
  7404. -#define	reg_ce_m2_central_7_0_pos 0
  7405. -#define	reg_ce_m2_central_7_0_len 8
  7406. -#define	reg_ce_m2_central_7_0_lsb 0
  7407. -#define xd_p_reg_ce_m2_central_15_8	0xABF5
  7408. -#define	reg_ce_m2_central_15_8_pos 0
  7409. -#define	reg_ce_m2_central_15_8_len 8
  7410. -#define	reg_ce_m2_central_15_8_lsb 8
  7411. -#define xd_p_reg_ce_fftshift	0xABF6
  7412. -#define	reg_ce_fftshift_pos 0
  7413. -#define	reg_ce_fftshift_len 4
  7414. -#define	reg_ce_fftshift_lsb 0
  7415. -#define xd_p_reg_ce_fftshift1	0xABF6
  7416. -#define	reg_ce_fftshift1_pos 4
  7417. -#define	reg_ce_fftshift1_len 4
  7418. -#define	reg_ce_fftshift1_lsb 0
  7419. -#define xd_p_reg_ce_fftshift2	0xABF7
  7420. -#define	reg_ce_fftshift2_pos 0
  7421. -#define	reg_ce_fftshift2_len 4
  7422. -#define	reg_ce_fftshift2_lsb 0
  7423. -#define xd_p_reg_ce_top_mobile	0xABF7
  7424. -#define	reg_ce_top_mobile_pos 4
  7425. -#define	reg_ce_top_mobile_len 1
  7426. -#define	reg_ce_top_mobile_lsb 0
  7427. -#define xd_p_reg_strong_sginal_detected 0xA2BC
  7428. -#define reg_strong_sginal_detected_pos 2
  7429. -#define reg_strong_sginal_detected_len 1
  7430. -#define reg_strong_sginal_detected_lsb 0
  7431. -
  7432. -#define XD_MP2IF_BASE                           0xB000
  7433. -#define XD_MP2IF_CSR                        (0x00 + XD_MP2IF_BASE)
  7434. -#define XD_MP2IF_DMX_CTRL                       (0x03 + XD_MP2IF_BASE)
  7435. -#define XD_MP2IF_PID_IDX                        (0x04 + XD_MP2IF_BASE)
  7436. -#define XD_MP2IF_PID_DATA_L                     (0x05 + XD_MP2IF_BASE)
  7437. -#define XD_MP2IF_PID_DATA_H                     (0x06 + XD_MP2IF_BASE)
  7438. -#define XD_MP2IF_MISC                       (0x07 + XD_MP2IF_BASE)
  7439. -
  7440. -extern struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d);
  7441. -extern int af9005_read_ofdm_register(struct dvb_usb_device *d, u16 reg,
  7442. -				     u8 * value);
  7443. -extern int af9005_read_ofdm_registers(struct dvb_usb_device *d, u16 reg,
  7444. -				      u8 * values, int len);
  7445. -extern int af9005_write_ofdm_register(struct dvb_usb_device *d, u16 reg,
  7446. -				      u8 value);
  7447. -extern int af9005_write_ofdm_registers(struct dvb_usb_device *d, u16 reg,
  7448. -				       u8 * values, int len);
  7449. -extern int af9005_read_tuner_registers(struct dvb_usb_device *d, u16 reg,
  7450. -				       u8 addr, u8 * values, int len);
  7451. -extern int af9005_write_tuner_registers(struct dvb_usb_device *d, u16 reg,
  7452. -					u8 * values, int len);
  7453. -extern int af9005_read_register_bits(struct dvb_usb_device *d, u16 reg,
  7454. -				     u8 pos, u8 len, u8 * value);
  7455. -extern int af9005_write_register_bits(struct dvb_usb_device *d, u16 reg,
  7456. -				      u8 pos, u8 len, u8 value);
  7457. -extern int af9005_send_command(struct dvb_usb_device *d, u8 command,
  7458. -			       u8 * wbuf, int wlen, u8 * rbuf, int rlen);
  7459. -extern int af9005_read_eeprom(struct dvb_usb_device *d, u8 address,
  7460. -			      u8 * values, int len);
  7461. -extern int af9005_tuner_attach(struct dvb_usb_adapter *adap);
  7462. -extern int af9005_led_control(struct dvb_usb_device *d, int onoff);
  7463. -
  7464. -extern u8 regmask[8];
  7465. -
  7466. -/* remote control decoder */
  7467. -extern int af9005_rc_decode(struct dvb_usb_device *d, u8 * data, int len,
  7468. -			    u32 * event, int *state);
  7469. -extern struct rc_map_table rc_map_af9005_table[];
  7470. -extern int rc_map_af9005_table_size;
  7471. -
  7472. -#endif
  7473. diff -ruN ../linux-4.14.336/drivers/net/Space.c ./drivers/net/Space.c
  7474. --- linux-4.14.336/../linux-4.14.336/drivers/net/Space.c	2024-01-10 14:45:41.000000000 +0100
  7475. +++ linux-4.14.336/./drivers/net/Space.c	2024-02-14 21:04:46.981594989 +0100
  7476. @@ -150,11 +150,6 @@
  7477.  	for (num = 0; num < 8; ++num)
  7478.  		ethif_probe2(num);
  7479.  
  7480. -#ifdef CONFIG_COPS
  7481. -	cops_probe(0);
  7482. -	cops_probe(1);
  7483. -	cops_probe(2);
  7484. -#endif
  7485.  #ifdef CONFIG_LTPC
  7486.  	ltpc_probe();
  7487.  #endif
  7488. diff -ruN ../linux-4.14.336/drivers/net/appletalk/Kconfig ./drivers/net/appletalk/Kconfig
  7489. --- linux-4.14.336/../linux-4.14.336/drivers/net/appletalk/Kconfig	2024-01-10 14:45:41.000000000 +0100
  7490. +++ linux-4.14.336/./drivers/net/appletalk/Kconfig	2024-02-14 21:04:25.861596249 +0100
  7491. @@ -49,32 +49,6 @@
  7492.  	  This driver is experimental, which means that it may not work.
  7493.  	  See the file <file:Documentation/networking/ltpc.txt>.
  7494.  
  7495. -config COPS
  7496. -	tristate "COPS LocalTalk PC support"
  7497. -	depends on DEV_APPLETALK && (ISA || EISA)
  7498. -	help
  7499. -	  This allows you to use COPS AppleTalk cards to connect to LocalTalk
  7500. -	  networks. You also need version 1.3.3 or later of the netatalk
  7501. -	  package. This driver is experimental, which means that it may not
  7502. -	  work. This driver will only work if you choose "AppleTalk DDP"
  7503. -	  networking support, above.
  7504. -	  Please read the file <file:Documentation/networking/cops.txt>.
  7505. -
  7506. -config COPS_DAYNA
  7507. -	bool "Dayna firmware support"
  7508. -	depends on COPS
  7509. -	help
  7510. -	  Support COPS compatible cards with Dayna style firmware (Dayna
  7511. -	  DL2000/ Daynatalk/PC (half length), COPS LT-95, Farallon PhoneNET PC
  7512. -	  III, Farallon PhoneNET PC II).
  7513. -
  7514. -config COPS_TANGENT
  7515. -	bool "Tangent firmware support"
  7516. -	depends on COPS
  7517. -	help
  7518. -	  Support COPS compatible cards with Tangent style firmware (Tangent
  7519. -	  ATB_II, Novell NL-1000, Daystar Digital LT-200.
  7520. -
  7521.  config IPDDP
  7522.  	tristate "Appletalk-IP driver support"
  7523.  	depends on DEV_APPLETALK && ATALK
  7524. diff -ruN ../linux-4.14.336/drivers/net/appletalk/Makefile ./drivers/net/appletalk/Makefile
  7525. --- linux-4.14.336/../linux-4.14.336/drivers/net/appletalk/Makefile	2024-01-10 14:45:41.000000000 +0100
  7526. +++ linux-4.14.336/./drivers/net/appletalk/Makefile	2024-02-14 21:04:05.191597490 +0100
  7527. @@ -3,5 +3,4 @@
  7528.  #
  7529.  
  7530.  obj-$(CONFIG_IPDDP) += ipddp.o
  7531. -obj-$(CONFIG_COPS) += cops.o
  7532.  obj-$(CONFIG_LTPC) += ltpc.o
  7533. diff -ruN ../linux-4.14.336/drivers/net/appletalk/cops.c ./drivers/net/appletalk/cops.c
  7534. --- linux-4.14.336/../linux-4.14.336/drivers/net/appletalk/cops.c	2024-01-10 14:45:41.000000000 +0100
  7535. +++ linux-4.14.336/./drivers/net/appletalk/cops.c	1970-01-01 01:00:00.000000000 +0100
  7536. @@ -1,1010 +0,0 @@
  7537. -/*      cops.c: LocalTalk driver for Linux.
  7538. - *
  7539. - *	Authors:
  7540. - *      - Jay Schulist <jschlst@samba.org>
  7541. - *
  7542. - *	With more than a little help from;
  7543. - *	- Alan Cox <alan@lxorguk.ukuu.org.uk>
  7544. - *
  7545. - *      Derived from:
  7546. - *      - skeleton.c: A network driver outline for linux.
  7547. - *        Written 1993-94 by Donald Becker.
  7548. - *	- ltpc.c: A driver for the LocalTalk PC card.
  7549. - *	  Written by Bradford W. Johnson.
  7550. - *
  7551. - *      Copyright 1993 United States Government as represented by the
  7552. - *      Director, National Security Agency.
  7553. - *
  7554. - *      This software may be used and distributed according to the terms
  7555. - *      of the GNU General Public License, incorporated herein by reference.
  7556. - *
  7557. - *	Changes:
  7558. - *	19970608	Alan Cox	Allowed dual card type support
  7559. - *					Can set board type in insmod
  7560. - *					Hooks for cops_setup routine
  7561. - *					(not yet implemented).
  7562. - *	19971101	Jay Schulist	Fixes for multiple lt* devices.
  7563. - *	19980607	Steven Hirsch	Fixed the badly broken support
  7564. - *					for Tangent type cards. Only
  7565. - *                                      tested on Daystar LT200. Some
  7566. - *                                      cleanup of formatting and program
  7567. - *                                      logic.  Added emacs 'local-vars'
  7568. - *                                      setup for Jay's brace style.
  7569. - *	20000211	Alan Cox	Cleaned up for softnet
  7570. - */
  7571. -
  7572. -static const char *version =
  7573. -"cops.c:v0.04 6/7/98 Jay Schulist <jschlst@samba.org>\n";
  7574. -/*
  7575. - *  Sources:
  7576. - *      COPS Localtalk SDK. This provides almost all of the information
  7577. - *      needed.
  7578. - */
  7579. -
  7580. -/*
  7581. - * insmod/modprobe configurable stuff.
  7582. - *	- IO Port, choose one your card supports or 0 if you dare.
  7583. - *	- IRQ, also choose one your card supports or nothing and let
  7584. - *	  the driver figure it out.
  7585. - */
  7586. -
  7587. -#include <linux/module.h>
  7588. -#include <linux/kernel.h>
  7589. -#include <linux/types.h>
  7590. -#include <linux/fcntl.h>
  7591. -#include <linux/interrupt.h>
  7592. -#include <linux/ptrace.h>
  7593. -#include <linux/ioport.h>
  7594. -#include <linux/in.h>
  7595. -#include <linux/string.h>
  7596. -#include <linux/errno.h>
  7597. -#include <linux/init.h>
  7598. -#include <linux/netdevice.h>
  7599. -#include <linux/etherdevice.h>
  7600. -#include <linux/skbuff.h>
  7601. -#include <linux/if_arp.h>
  7602. -#include <linux/if_ltalk.h>
  7603. -#include <linux/delay.h>	/* For udelay() */
  7604. -#include <linux/atalk.h>
  7605. -#include <linux/spinlock.h>
  7606. -#include <linux/bitops.h>
  7607. -#include <linux/jiffies.h>
  7608. -
  7609. -#include <asm/io.h>
  7610. -#include <asm/dma.h>
  7611. -
  7612. -#include "cops.h"		/* Our Stuff */
  7613. -#include "cops_ltdrv.h"		/* Firmware code for Tangent type cards. */
  7614. -#include "cops_ffdrv.h"		/* Firmware code for Dayna type cards. */
  7615. -
  7616. -/*
  7617. - *      The name of the card. Is used for messages and in the requests for
  7618. - *      io regions, irqs and dma channels
  7619. - */
  7620. -
  7621. -static const char *cardname = "cops";
  7622. -
  7623. -#ifdef CONFIG_COPS_DAYNA
  7624. -static int board_type = DAYNA;	/* Module exported */
  7625. -#else
  7626. -static int board_type = TANGENT;
  7627. -#endif
  7628. -
  7629. -static int io = 0x240;		/* Default IO for Dayna */
  7630. -static int irq = 5;		/* Default IRQ */
  7631. -
  7632. -/*
  7633. - *	COPS Autoprobe information.
  7634. - *	Right now if port address is right but IRQ is not 5 this will
  7635. - *      return a 5 no matter what since we will still get a status response.
  7636. - *      Need one more additional check to narrow down after we have gotten
  7637. - *      the ioaddr. But since only other possible IRQs is 3 and 4 so no real
  7638. - *	hurry on this. I *STRONGLY* recommend using IRQ 5 for your card with
  7639. - *	this driver.
  7640. - * 
  7641. - *	This driver has 2 modes and they are: Dayna mode and Tangent mode.
  7642. - *	Each mode corresponds with the type of card. It has been found
  7643. - *	that there are 2 main types of cards and all other cards are
  7644. - *	the same and just have different names or only have minor differences
  7645. - *	such as more IO ports. As this driver is tested it will
  7646. - *	become more clear on exactly what cards are supported. The driver
  7647. - *	defaults to using Dayna mode. To change the drivers mode, simply
  7648. - *	select Dayna or Tangent mode when configuring the kernel.
  7649. - *
  7650. - *      This driver should support:
  7651. - *      TANGENT driver mode:
  7652. - *              Tangent ATB-II, Novell NL-1000, Daystar Digital LT-200,
  7653. - *		COPS LT-1
  7654. - *      DAYNA driver mode:
  7655. - *              Dayna DL2000/DaynaTalk PC (Half Length), COPS LT-95, 
  7656. - *		Farallon PhoneNET PC III, Farallon PhoneNET PC II
  7657. - *	Other cards possibly supported mode unknown though:
  7658. - *		Dayna DL2000 (Full length), COPS LT/M (Micro-Channel)
  7659. - *
  7660. - *	Cards NOT supported by this driver but supported by the ltpc.c
  7661. - *	driver written by Bradford W. Johnson <johns393@maroon.tc.umn.edu>
  7662. - *		Farallon PhoneNET PC
  7663. - *		Original Apple LocalTalk PC card
  7664. - * 
  7665. - *      N.B.
  7666. - *
  7667. - *      The Daystar Digital LT200 boards do not support interrupt-driven
  7668. - *      IO.  You must specify 'irq=0xff' as a module parameter to invoke
  7669. - *      polled mode.  I also believe that the port probing logic is quite
  7670. - *      dangerous at best and certainly hopeless for a polled card.  Best to 
  7671. - *      specify both. - Steve H.
  7672. - *
  7673. - */
  7674. -
  7675. -/*
  7676. - * Zero terminated list of IO ports to probe.
  7677. - */
  7678. -
  7679. -static unsigned int ports[] = { 
  7680. -	0x240, 0x340, 0x200, 0x210, 0x220, 0x230, 0x260, 
  7681. -	0x2A0, 0x300, 0x310, 0x320, 0x330, 0x350, 0x360,
  7682. -	0
  7683. -};
  7684. -
  7685. -/*
  7686. - * Zero terminated list of IRQ ports to probe.
  7687. - */
  7688. -
  7689. -static int cops_irqlist[] = {
  7690. -	5, 4, 3, 0 
  7691. -};
  7692. -
  7693. -static struct timer_list cops_timer;
  7694. -
  7695. -/* use 0 for production, 1 for verification, 2 for debug, 3 for verbose debug */
  7696. -#ifndef COPS_DEBUG
  7697. -#define COPS_DEBUG 1 
  7698. -#endif
  7699. -static unsigned int cops_debug = COPS_DEBUG;
  7700. -
  7701. -/* The number of low I/O ports used by the card. */
  7702. -#define COPS_IO_EXTENT       8
  7703. -
  7704. -/* Information that needs to be kept for each board. */
  7705. -
  7706. -struct cops_local
  7707. -{
  7708. -        int board;			/* Holds what board type is. */
  7709. -	int nodeid;			/* Set to 1 once have nodeid. */
  7710. -        unsigned char node_acquire;	/* Node ID when acquired. */
  7711. -        struct atalk_addr node_addr;	/* Full node address */
  7712. -	spinlock_t lock;		/* RX/TX lock */
  7713. -};
  7714. -
  7715. -/* Index to functions, as function prototypes. */
  7716. -static int  cops_probe1 (struct net_device *dev, int ioaddr);
  7717. -static int  cops_irq (int ioaddr, int board);
  7718. -
  7719. -static int  cops_open (struct net_device *dev);
  7720. -static int  cops_jumpstart (struct net_device *dev);
  7721. -static void cops_reset (struct net_device *dev, int sleep);
  7722. -static void cops_load (struct net_device *dev);
  7723. -static int  cops_nodeid (struct net_device *dev, int nodeid);
  7724. -
  7725. -static irqreturn_t cops_interrupt (int irq, void *dev_id);
  7726. -static void cops_poll (unsigned long ltdev);
  7727. -static void cops_timeout(struct net_device *dev);
  7728. -static void cops_rx (struct net_device *dev);
  7729. -static netdev_tx_t  cops_send_packet (struct sk_buff *skb,
  7730. -					    struct net_device *dev);
  7731. -static void set_multicast_list (struct net_device *dev);
  7732. -static int  cops_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
  7733. -static int  cops_close (struct net_device *dev);
  7734. -
  7735. -static void cleanup_card(struct net_device *dev)
  7736. -{
  7737. -	if (dev->irq)
  7738. -		free_irq(dev->irq, dev);
  7739. -	release_region(dev->base_addr, COPS_IO_EXTENT);
  7740. -}
  7741. -
  7742. -/*
  7743. - *      Check for a network adaptor of this type, and return '0' iff one exists.
  7744. - *      If dev->base_addr == 0, probe all likely locations.
  7745. - *      If dev->base_addr in [1..0x1ff], always return failure.
  7746. - *        otherwise go with what we pass in.
  7747. - */
  7748. -struct net_device * __init cops_probe(int unit)
  7749. -{
  7750. -	struct net_device *dev;
  7751. -	unsigned *port;
  7752. -	int base_addr;
  7753. -	int err = 0;
  7754. -
  7755. -	dev = alloc_ltalkdev(sizeof(struct cops_local));
  7756. -	if (!dev)
  7757. -		return ERR_PTR(-ENOMEM);
  7758. -
  7759. -	if (unit >= 0) {
  7760. -		sprintf(dev->name, "lt%d", unit);
  7761. -		netdev_boot_setup_check(dev);
  7762. -		irq = dev->irq;
  7763. -		base_addr = dev->base_addr;
  7764. -	} else {
  7765. -		base_addr = dev->base_addr = io;
  7766. -	}
  7767. -
  7768. -	if (base_addr > 0x1ff) {    /* Check a single specified location. */
  7769. -		err = cops_probe1(dev, base_addr);
  7770. -	} else if (base_addr != 0) { /* Don't probe at all. */
  7771. -		err = -ENXIO;
  7772. -	} else {
  7773. -		/* FIXME  Does this really work for cards which generate irq?
  7774. -		 * It's definitely N.G. for polled Tangent. sh
  7775. -		 * Dayna cards don't autoprobe well at all, but if your card is
  7776. -		 * at IRQ 5 & IO 0x240 we find it every time. ;) JS
  7777. -		 */
  7778. -		for (port = ports; *port && cops_probe1(dev, *port) < 0; port++)
  7779. -			;
  7780. -		if (!*port)
  7781. -			err = -ENODEV;
  7782. -	}
  7783. -	if (err)
  7784. -		goto out;
  7785. -	err = register_netdev(dev);
  7786. -	if (err)
  7787. -		goto out1;
  7788. -	return dev;
  7789. -out1:
  7790. -	cleanup_card(dev);
  7791. -out:
  7792. -	free_netdev(dev);
  7793. -	return ERR_PTR(err);
  7794. -}
  7795. -
  7796. -static const struct net_device_ops cops_netdev_ops = {
  7797. -	.ndo_open               = cops_open,
  7798. -        .ndo_stop               = cops_close,
  7799. -	.ndo_start_xmit   	= cops_send_packet,
  7800. -	.ndo_tx_timeout		= cops_timeout,
  7801. -        .ndo_do_ioctl           = cops_ioctl,
  7802. -	.ndo_set_rx_mode	= set_multicast_list,
  7803. -};
  7804. -
  7805. -/*
  7806. - *      This is the real probe routine. Linux has a history of friendly device
  7807. - *      probes on the ISA bus. A good device probes avoids doing writes, and
  7808. - *      verifies that the correct device exists and functions.
  7809. - */
  7810. -static int __init cops_probe1(struct net_device *dev, int ioaddr)
  7811. -{
  7812. -        struct cops_local *lp;
  7813. -	static unsigned version_printed;
  7814. -	int board = board_type;
  7815. -	int retval;
  7816. -	
  7817. -        if(cops_debug && version_printed++ == 0)
  7818. -		printk("%s", version);
  7819. -
  7820. -	/* Grab the region so no one else tries to probe our ioports. */
  7821. -	if (!request_region(ioaddr, COPS_IO_EXTENT, dev->name))
  7822. -		return -EBUSY;
  7823. -
  7824. -        /*
  7825. -         * Since this board has jumpered interrupts, allocate the interrupt
  7826. -         * vector now. There is no point in waiting since no other device
  7827. -         * can use the interrupt, and this marks the irq as busy. Jumpered
  7828. -         * interrupts are typically not reported by the boards, and we must
  7829. -         * used AutoIRQ to find them.
  7830. -	 */
  7831. -	dev->irq = irq;
  7832. -	switch (dev->irq)
  7833. -	{
  7834. -		case 0:
  7835. -			/* COPS AutoIRQ routine */
  7836. -			dev->irq = cops_irq(ioaddr, board);
  7837. -			if (dev->irq)
  7838. -				break;
  7839. -			/* No IRQ found on this port, fallthrough */
  7840. -		case 1:
  7841. -			retval = -EINVAL;
  7842. -			goto err_out;
  7843. -
  7844. -		/* Fixup for users that don't know that IRQ 2 is really
  7845. -		 * IRQ 9, or don't know which one to set.
  7846. -		 */
  7847. -		case 2:
  7848. -			dev->irq = 9;
  7849. -			break;
  7850. -
  7851. -		/* Polled operation requested. Although irq of zero passed as
  7852. -		 * a parameter tells the init routines to probe, we'll
  7853. -		 * overload it to denote polled operation at runtime.
  7854. -		 */
  7855. -		case 0xff:
  7856. -			dev->irq = 0;
  7857. -			break;
  7858. -
  7859. -		default:
  7860. -			break;
  7861. -	}
  7862. -
  7863. -	dev->base_addr = ioaddr;
  7864. -
  7865. -	/* Reserve any actual interrupt. */
  7866. -	if (dev->irq) {
  7867. -		retval = request_irq(dev->irq, cops_interrupt, 0, dev->name, dev);
  7868. -		if (retval)
  7869. -			goto err_out;
  7870. -	}
  7871. -
  7872. -        lp = netdev_priv(dev);
  7873. -        spin_lock_init(&lp->lock);
  7874. -
  7875. -	/* Copy local board variable to lp struct. */
  7876. -	lp->board               = board;
  7877. -
  7878. -	dev->netdev_ops 	= &cops_netdev_ops;
  7879. -	dev->watchdog_timeo	= HZ * 2;
  7880. -
  7881. -
  7882. -	/* Tell the user where the card is and what mode we're in. */
  7883. -	if(board==DAYNA)
  7884. -		printk("%s: %s at %#3x, using IRQ %d, in Dayna mode.\n", 
  7885. -			dev->name, cardname, ioaddr, dev->irq);
  7886. -	if(board==TANGENT) {
  7887. -		if(dev->irq)
  7888. -			printk("%s: %s at %#3x, IRQ %d, in Tangent mode\n", 
  7889. -				dev->name, cardname, ioaddr, dev->irq);
  7890. -		else
  7891. -			printk("%s: %s at %#3x, using polled IO, in Tangent mode.\n", 
  7892. -				dev->name, cardname, ioaddr);
  7893. -
  7894. -	}
  7895. -        return 0;
  7896. -
  7897. -err_out:
  7898. -	release_region(ioaddr, COPS_IO_EXTENT);
  7899. -	return retval;
  7900. -}
  7901. -
  7902. -static int __init cops_irq (int ioaddr, int board)
  7903. -{       /*
  7904. -         * This does not use the IRQ to determine where the IRQ is. We just
  7905. -         * assume that when we get a correct status response that it's the IRQ.
  7906. -         * This really just verifies the IO port but since we only have access
  7907. -         * to such a small number of IRQs (5, 4, 3) this is not bad.
  7908. -         * This will probably not work for more than one card.
  7909. -         */
  7910. -        int irqaddr=0;
  7911. -        int i, x, status;
  7912. -
  7913. -        if(board==DAYNA)
  7914. -        {
  7915. -                outb(0, ioaddr+DAYNA_RESET);
  7916. -                inb(ioaddr+DAYNA_RESET);
  7917. -                mdelay(333);
  7918. -        }
  7919. -        if(board==TANGENT)
  7920. -        {
  7921. -                inb(ioaddr);
  7922. -                outb(0, ioaddr);
  7923. -                outb(0, ioaddr+TANG_RESET);
  7924. -        }
  7925. -
  7926. -        for(i=0; cops_irqlist[i] !=0; i++)
  7927. -        {
  7928. -                irqaddr = cops_irqlist[i];
  7929. -                for(x = 0xFFFF; x>0; x --)    /* wait for response */
  7930. -                {
  7931. -                        if(board==DAYNA)
  7932. -                        {
  7933. -                                status = (inb(ioaddr+DAYNA_CARD_STATUS)&3);
  7934. -                                if(status == 1)
  7935. -                                        return irqaddr;
  7936. -                        }
  7937. -                        if(board==TANGENT)
  7938. -                        {
  7939. -                                if((inb(ioaddr+TANG_CARD_STATUS)& TANG_TX_READY) !=0)
  7940. -                                        return irqaddr;
  7941. -                        }
  7942. -                }
  7943. -        }
  7944. -        return 0;       /* no IRQ found */
  7945. -}
  7946. -
  7947. -/*
  7948. - * Open/initialize the board. This is called (in the current kernel)
  7949. - * sometime after booting when the 'ifconfig' program is run.
  7950. - */
  7951. -static int cops_open(struct net_device *dev)
  7952. -{
  7953. -    struct cops_local *lp = netdev_priv(dev);
  7954. -
  7955. -	if(dev->irq==0)
  7956. -	{
  7957. -		/*
  7958. -		 * I don't know if the Dayna-style boards support polled 
  7959. -		 * operation.  For now, only allow it for Tangent.
  7960. -		 */
  7961. -		if(lp->board==TANGENT)	/* Poll 20 times per second */
  7962. -		{
  7963. -		    init_timer(&cops_timer);
  7964. -		    cops_timer.function = cops_poll;
  7965. -		    cops_timer.data 	= (unsigned long)dev;
  7966. -		    cops_timer.expires 	= jiffies + HZ/20;
  7967. -		    add_timer(&cops_timer);
  7968. -		} 
  7969. -		else 
  7970. -		{
  7971. -			printk(KERN_WARNING "%s: No irq line set\n", dev->name);
  7972. -			return -EAGAIN;
  7973. -		}
  7974. -	}
  7975. -
  7976. -	cops_jumpstart(dev);	/* Start the card up. */
  7977. -
  7978. -	netif_start_queue(dev);
  7979. -        return 0;
  7980. -}
  7981. -
  7982. -/*
  7983. - *	This allows for a dynamic start/restart of the entire card.
  7984. - */
  7985. -static int cops_jumpstart(struct net_device *dev)
  7986. -{
  7987. -	struct cops_local *lp = netdev_priv(dev);
  7988. -
  7989. -	/*
  7990. -         *      Once the card has the firmware loaded and has acquired
  7991. -         *      the nodeid, if it is reset it will lose it all.
  7992. -         */
  7993. -        cops_reset(dev,1);	/* Need to reset card before load firmware. */
  7994. -        cops_load(dev);		/* Load the firmware. */
  7995. -
  7996. -	/*
  7997. -	 *	If atalkd already gave us a nodeid we will use that
  7998. -	 *	one again, else we wait for atalkd to give us a nodeid
  7999. -	 *	in cops_ioctl. This may cause a problem if someone steals
  8000. -	 *	our nodeid while we are resetting.
  8001. -	 */	
  8002. -	if(lp->nodeid == 1)
  8003. -		cops_nodeid(dev,lp->node_acquire);
  8004. -
  8005. -	return 0;
  8006. -}
  8007. -
  8008. -static void tangent_wait_reset(int ioaddr)
  8009. -{
  8010. -	int timeout=0;
  8011. -
  8012. -	while(timeout++ < 5 && (inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0)
  8013. -		mdelay(1);   /* Wait 1 second */
  8014. -}
  8015. -
  8016. -/*
  8017. - *      Reset the LocalTalk board.
  8018. - */
  8019. -static void cops_reset(struct net_device *dev, int sleep)
  8020. -{
  8021. -        struct cops_local *lp = netdev_priv(dev);
  8022. -        int ioaddr=dev->base_addr;
  8023. -
  8024. -        if(lp->board==TANGENT)
  8025. -        {
  8026. -                inb(ioaddr);		/* Clear request latch. */
  8027. -                outb(0,ioaddr);		/* Clear the TANG_TX_READY flop. */
  8028. -                outb(0, ioaddr+TANG_RESET);	/* Reset the adapter. */
  8029. -
  8030. -		tangent_wait_reset(ioaddr);
  8031. -                outb(0, ioaddr+TANG_CLEAR_INT);
  8032. -        }
  8033. -        if(lp->board==DAYNA)
  8034. -        {
  8035. -                outb(0, ioaddr+DAYNA_RESET);	/* Assert the reset port */
  8036. -                inb(ioaddr+DAYNA_RESET);	/* Clear the reset */
  8037. -		if (sleep)
  8038. -			msleep(333);
  8039. -		else
  8040. -			mdelay(333);
  8041. -        }
  8042. -
  8043. -	netif_wake_queue(dev);
  8044. -}
  8045. -
  8046. -static void cops_load (struct net_device *dev)
  8047. -{
  8048. -        struct ifreq ifr;
  8049. -        struct ltfirmware *ltf= (struct ltfirmware *)&ifr.ifr_ifru;
  8050. -        struct cops_local *lp = netdev_priv(dev);
  8051. -        int ioaddr=dev->base_addr;
  8052. -	int length, i = 0;
  8053. -
  8054. -        strcpy(ifr.ifr_name,"lt0");
  8055. -
  8056. -        /* Get card's firmware code and do some checks on it. */
  8057. -#ifdef CONFIG_COPS_DAYNA        
  8058. -        if(lp->board==DAYNA)
  8059. -        {
  8060. -                ltf->length=sizeof(ffdrv_code);
  8061. -                ltf->data=ffdrv_code;
  8062. -        }
  8063. -        else
  8064. -#endif        
  8065. -#ifdef CONFIG_COPS_TANGENT
  8066. -        if(lp->board==TANGENT)
  8067. -        {
  8068. -                ltf->length=sizeof(ltdrv_code);
  8069. -                ltf->data=ltdrv_code;
  8070. -        }
  8071. -        else
  8072. -#endif
  8073. -	{
  8074. -		printk(KERN_INFO "%s; unsupported board type.\n", dev->name);
  8075. -		return;
  8076. -	}
  8077. -	
  8078. -        /* Check to make sure firmware is correct length. */
  8079. -        if(lp->board==DAYNA && ltf->length!=5983)
  8080. -        {
  8081. -                printk(KERN_WARNING "%s: Firmware is not length of FFDRV.BIN.\n", dev->name);
  8082. -                return;
  8083. -        }
  8084. -        if(lp->board==TANGENT && ltf->length!=2501)
  8085. -        {
  8086. -                printk(KERN_WARNING "%s: Firmware is not length of DRVCODE.BIN.\n", dev->name);
  8087. -                return;
  8088. -        }
  8089. -
  8090. -        if(lp->board==DAYNA)
  8091. -        {
  8092. -                /*
  8093. -                 *      We must wait for a status response
  8094. -                 *      with the DAYNA board.
  8095. -                 */
  8096. -                while(++i<65536)
  8097. -                {
  8098. -                       if((inb(ioaddr+DAYNA_CARD_STATUS)&3)==1)
  8099. -                                break;
  8100. -                }
  8101. -
  8102. -                if(i==65536)
  8103. -                        return;
  8104. -        }
  8105. -
  8106. -        /*
  8107. -         *      Upload the firmware and kick. Byte-by-byte works nicely here.
  8108. -         */
  8109. -	i=0;
  8110. -        length = ltf->length;
  8111. -        while(length--)
  8112. -        {
  8113. -                outb(ltf->data[i], ioaddr);
  8114. -                i++;
  8115. -        }
  8116. -
  8117. -	if(cops_debug > 1)
  8118. -		printk("%s: Uploaded firmware - %d bytes of %d bytes.\n", 
  8119. -			dev->name, i, ltf->length);
  8120. -
  8121. -        if(lp->board==DAYNA) 	/* Tell Dayna to run the firmware code. */
  8122. -                outb(1, ioaddr+DAYNA_INT_CARD);
  8123. -	else			/* Tell Tang to run the firmware code. */
  8124. -		inb(ioaddr);
  8125. -
  8126. -        if(lp->board==TANGENT)
  8127. -        {
  8128. -                tangent_wait_reset(ioaddr);
  8129. -                inb(ioaddr);	/* Clear initial ready signal. */
  8130. -        }
  8131. -}
  8132. -
  8133. -/*
  8134. - * 	Get the LocalTalk Nodeid from the card. We can suggest
  8135. - *	any nodeid 1-254. The card will try and get that exact
  8136. - *	address else we can specify 0 as the nodeid and the card
  8137. - *	will autoprobe for a nodeid.
  8138. - */
  8139. -static int cops_nodeid (struct net_device *dev, int nodeid)
  8140. -{
  8141. -	struct cops_local *lp = netdev_priv(dev);
  8142. -	int ioaddr = dev->base_addr;
  8143. -
  8144. -	if(lp->board == DAYNA)
  8145. -        {
  8146. -        	/* Empty any pending adapter responses. */
  8147. -                while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0)
  8148. -                {
  8149. -			outb(0, ioaddr+COPS_CLEAR_INT);	/* Clear interrupts. */
  8150. -        		if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_REQUEST)
  8151. -                		cops_rx(dev);	/* Kick any packets waiting. */
  8152. -			schedule();
  8153. -                }
  8154. -
  8155. -                outb(2, ioaddr);       	/* Output command packet length as 2. */
  8156. -                outb(0, ioaddr);
  8157. -                outb(LAP_INIT, ioaddr);	/* Send LAP_INIT command byte. */
  8158. -                outb(nodeid, ioaddr);  	/* Suggest node address. */
  8159. -        }
  8160. -
  8161. -	if(lp->board == TANGENT)
  8162. -        {
  8163. -                /* Empty any pending adapter responses. */
  8164. -                while(inb(ioaddr+TANG_CARD_STATUS)&TANG_RX_READY)
  8165. -                {
  8166. -			outb(0, ioaddr+COPS_CLEAR_INT);	/* Clear interrupt. */
  8167. -                	cops_rx(dev);          	/* Kick out packets waiting. */
  8168. -			schedule();
  8169. -                }
  8170. -
  8171. -		/* Not sure what Tangent does if nodeid picked is used. */
  8172. -                if(nodeid == 0)	         		/* Seed. */
  8173. -                	nodeid = jiffies&0xFF;		/* Get a random try */
  8174. -                outb(2, ioaddr);        		/* Command length LSB */
  8175. -                outb(0, ioaddr);       			/* Command length MSB */
  8176. -                outb(LAP_INIT, ioaddr); 		/* Send LAP_INIT byte */
  8177. -                outb(nodeid, ioaddr); 		  	/* LAP address hint. */
  8178. -                outb(0xFF, ioaddr);     		/* Int. level to use */
  8179. -        }
  8180. -
  8181. -	lp->node_acquire=0;		/* Set nodeid holder to 0. */
  8182. -        while(lp->node_acquire==0)	/* Get *True* nodeid finally. */
  8183. -	{
  8184. -		outb(0, ioaddr+COPS_CLEAR_INT);	/* Clear any interrupt. */
  8185. -
  8186. -		if(lp->board == DAYNA)
  8187. -		{
  8188. -                	if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_REQUEST)
  8189. -                		cops_rx(dev);	/* Grab the nodeid put in lp->node_acquire. */
  8190. -		}
  8191. -		if(lp->board == TANGENT)
  8192. -		{	
  8193. -			if(inb(ioaddr+TANG_CARD_STATUS)&TANG_RX_READY)
  8194. -                                cops_rx(dev);   /* Grab the nodeid put in lp->node_acquire. */
  8195. -		}
  8196. -		schedule();
  8197. -	}
  8198. -
  8199. -	if(cops_debug > 1)
  8200. -		printk(KERN_DEBUG "%s: Node ID %d has been acquired.\n", 
  8201. -			dev->name, lp->node_acquire);
  8202. -
  8203. -	lp->nodeid=1;	/* Set got nodeid to 1. */
  8204. -
  8205. -        return 0;
  8206. -}
  8207. -
  8208. -/*
  8209. - *	Poll the Tangent type cards to see if we have work.
  8210. - */
  8211. - 
  8212. -static void cops_poll(unsigned long ltdev)
  8213. -{
  8214. -	int ioaddr, status;
  8215. -	int boguscount = 0;
  8216. -
  8217. -	struct net_device *dev = (struct net_device *)ltdev;
  8218. -
  8219. -	del_timer(&cops_timer);
  8220. -
  8221. -	if(dev == NULL)
  8222. -		return;	/* We've been downed */
  8223. -
  8224. -	ioaddr = dev->base_addr;
  8225. -	do {
  8226. -		status=inb(ioaddr+TANG_CARD_STATUS);
  8227. -		if(status & TANG_RX_READY)
  8228. -			cops_rx(dev);
  8229. -		if(status & TANG_TX_READY)
  8230. -			netif_wake_queue(dev);
  8231. -		status = inb(ioaddr+TANG_CARD_STATUS);
  8232. -	} while((++boguscount < 20) && (status&(TANG_RX_READY|TANG_TX_READY)));
  8233. -
  8234. -	/* poll 20 times per second */
  8235. -	cops_timer.expires = jiffies + HZ/20;
  8236. -	add_timer(&cops_timer);
  8237. -}
  8238. -
  8239. -/*
  8240. - *      The typical workload of the driver:
  8241. - *      Handle the network interface interrupts.
  8242. - */
  8243. -static irqreturn_t cops_interrupt(int irq, void *dev_id)
  8244. -{
  8245. -        struct net_device *dev = dev_id;
  8246. -        struct cops_local *lp;
  8247. -        int ioaddr, status;
  8248. -        int boguscount = 0;
  8249. -
  8250. -        ioaddr = dev->base_addr;
  8251. -        lp = netdev_priv(dev);
  8252. -
  8253. -	if(lp->board==DAYNA)
  8254. -	{
  8255. -		do {
  8256. -			outb(0, ioaddr + COPS_CLEAR_INT);
  8257. -                       	status=inb(ioaddr+DAYNA_CARD_STATUS);
  8258. -                       	if((status&0x03)==DAYNA_RX_REQUEST)
  8259. -                       	        cops_rx(dev);
  8260. -                	netif_wake_queue(dev);
  8261. -		} while(++boguscount < 20);
  8262. -	}
  8263. -	else
  8264. -	{
  8265. -		do {
  8266. -                       	status=inb(ioaddr+TANG_CARD_STATUS);
  8267. -			if(status & TANG_RX_READY)
  8268. -				cops_rx(dev);
  8269. -			if(status & TANG_TX_READY)
  8270. -				netif_wake_queue(dev);
  8271. -			status=inb(ioaddr+TANG_CARD_STATUS);
  8272. -		} while((++boguscount < 20) && (status&(TANG_RX_READY|TANG_TX_READY)));
  8273. -	}
  8274. -
  8275. -        return IRQ_HANDLED;
  8276. -}
  8277. -
  8278. -/*
  8279. - *      We have a good packet(s), get it/them out of the buffers.
  8280. - */
  8281. -static void cops_rx(struct net_device *dev)
  8282. -{
  8283. -        int pkt_len = 0;
  8284. -        int rsp_type = 0;
  8285. -        struct sk_buff *skb = NULL;
  8286. -        struct cops_local *lp = netdev_priv(dev);
  8287. -        int ioaddr = dev->base_addr;
  8288. -        int boguscount = 0;
  8289. -        unsigned long flags;
  8290. -
  8291. -
  8292. -	spin_lock_irqsave(&lp->lock, flags);
  8293. -	
  8294. -        if(lp->board==DAYNA)
  8295. -        {
  8296. -                outb(0, ioaddr);                /* Send out Zero length. */
  8297. -                outb(0, ioaddr);
  8298. -                outb(DATA_READ, ioaddr);        /* Send read command out. */
  8299. -
  8300. -                /* Wait for DMA to turn around. */
  8301. -                while(++boguscount<1000000)
  8302. -                {
  8303. -			barrier();
  8304. -                        if((inb(ioaddr+DAYNA_CARD_STATUS)&0x03)==DAYNA_RX_READY)
  8305. -                                break;
  8306. -                }
  8307. -
  8308. -                if(boguscount==1000000)
  8309. -                {
  8310. -                        printk(KERN_WARNING "%s: DMA timed out.\n",dev->name);
  8311. -			spin_unlock_irqrestore(&lp->lock, flags);
  8312. -                        return;
  8313. -                }
  8314. -        }
  8315. -
  8316. -        /* Get response length. */
  8317. -	if(lp->board==DAYNA)
  8318. -        	pkt_len = inb(ioaddr) & 0xFF;
  8319. -	else
  8320. -		pkt_len = inb(ioaddr) & 0x00FF;
  8321. -        pkt_len |= (inb(ioaddr) << 8);
  8322. -        /* Input IO code. */
  8323. -        rsp_type=inb(ioaddr);
  8324. -
  8325. -        /* Malloc up new buffer. */
  8326. -        skb = dev_alloc_skb(pkt_len);
  8327. -        if(skb == NULL)
  8328. -        {
  8329. -                printk(KERN_WARNING "%s: Memory squeeze, dropping packet.\n",
  8330. -			dev->name);
  8331. -                dev->stats.rx_dropped++;
  8332. -                while(pkt_len--)        /* Discard packet */
  8333. -                        inb(ioaddr);
  8334. -                spin_unlock_irqrestore(&lp->lock, flags);
  8335. -                return;
  8336. -        }
  8337. -        skb->dev = dev;
  8338. -        skb_put(skb, pkt_len);
  8339. -        skb->protocol = htons(ETH_P_LOCALTALK);
  8340. -
  8341. -        insb(ioaddr, skb->data, pkt_len);               /* Eat the Data */
  8342. -
  8343. -        if(lp->board==DAYNA)
  8344. -                outb(1, ioaddr+DAYNA_INT_CARD);         /* Interrupt the card */
  8345. -
  8346. -        spin_unlock_irqrestore(&lp->lock, flags);  /* Restore interrupts. */
  8347. -
  8348. -        /* Check for bad response length */
  8349. -        if(pkt_len < 0 || pkt_len > MAX_LLAP_SIZE)
  8350. -        {
  8351. -		printk(KERN_WARNING "%s: Bad packet length of %d bytes.\n", 
  8352. -			dev->name, pkt_len);
  8353. -                dev->stats.tx_errors++;
  8354. -                dev_kfree_skb_any(skb);
  8355. -                return;
  8356. -        }
  8357. -
  8358. -        /* Set nodeid and then get out. */
  8359. -        if(rsp_type == LAP_INIT_RSP)
  8360. -        {	/* Nodeid taken from received packet. */
  8361. -                lp->node_acquire = skb->data[0];
  8362. -                dev_kfree_skb_any(skb);
  8363. -                return;
  8364. -        }
  8365. -
  8366. -        /* One last check to make sure we have a good packet. */
  8367. -        if(rsp_type != LAP_RESPONSE)
  8368. -        {
  8369. -                printk(KERN_WARNING "%s: Bad packet type %d.\n", dev->name, rsp_type);
  8370. -                dev->stats.tx_errors++;
  8371. -                dev_kfree_skb_any(skb);
  8372. -                return;
  8373. -        }
  8374. -
  8375. -        skb_reset_mac_header(skb);    /* Point to entire packet. */
  8376. -        skb_pull(skb,3);
  8377. -        skb_reset_transport_header(skb);    /* Point to data (Skip header). */
  8378. -
  8379. -        /* Update the counters. */
  8380. -        dev->stats.rx_packets++;
  8381. -        dev->stats.rx_bytes += skb->len;
  8382. -
  8383. -        /* Send packet to a higher place. */
  8384. -        netif_rx(skb);
  8385. -}
  8386. -
  8387. -static void cops_timeout(struct net_device *dev)
  8388. -{
  8389. -        struct cops_local *lp = netdev_priv(dev);
  8390. -        int ioaddr = dev->base_addr;
  8391. -
  8392. -	dev->stats.tx_errors++;
  8393. -        if(lp->board==TANGENT)
  8394. -        {
  8395. -		if((inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0)
  8396. -               		printk(KERN_WARNING "%s: No TX complete interrupt.\n", dev->name);
  8397. -	}
  8398. -	printk(KERN_WARNING "%s: Transmit timed out.\n", dev->name);
  8399. -	cops_jumpstart(dev);	/* Restart the card. */
  8400. -	netif_trans_update(dev); /* prevent tx timeout */
  8401. -	netif_wake_queue(dev);
  8402. -}
  8403. -
  8404. -
  8405. -/*
  8406. - *	Make the card transmit a LocalTalk packet.
  8407. - */
  8408. -
  8409. -static netdev_tx_t cops_send_packet(struct sk_buff *skb,
  8410. -					  struct net_device *dev)
  8411. -{
  8412. -        struct cops_local *lp = netdev_priv(dev);
  8413. -        int ioaddr = dev->base_addr;
  8414. -        unsigned long flags;
  8415. -
  8416. -        /*
  8417. -         * Block a timer-based transmit from overlapping. 
  8418. -	 */
  8419. -	 
  8420. -	netif_stop_queue(dev);
  8421. -
  8422. -	spin_lock_irqsave(&lp->lock, flags);
  8423. -	if(lp->board == DAYNA)	 /* Wait for adapter transmit buffer. */
  8424. -		while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0)
  8425. -			cpu_relax();
  8426. -	if(lp->board == TANGENT) /* Wait for adapter transmit buffer. */
  8427. -		while((inb(ioaddr+TANG_CARD_STATUS)&TANG_TX_READY)==0)
  8428. -			cpu_relax();
  8429. -
  8430. -	/* Output IO length. */
  8431. -	outb(skb->len, ioaddr);
  8432. -	if(lp->board == DAYNA)
  8433. -               	outb(skb->len >> 8, ioaddr);
  8434. -	else
  8435. -		outb((skb->len >> 8)&0x0FF, ioaddr);
  8436. -
  8437. -	/* Output IO code. */
  8438. -	outb(LAP_WRITE, ioaddr);
  8439. -
  8440. -	if(lp->board == DAYNA)	/* Check the transmit buffer again. */
  8441. -        	while((inb(ioaddr+DAYNA_CARD_STATUS)&DAYNA_TX_READY)==0);
  8442. -
  8443. -	outsb(ioaddr, skb->data, skb->len);	/* Send out the data. */
  8444. -
  8445. -	if(lp->board==DAYNA)	/* Dayna requires you kick the card */
  8446. -		outb(1, ioaddr+DAYNA_INT_CARD);
  8447. -
  8448. -	spin_unlock_irqrestore(&lp->lock, flags);	/* Restore interrupts. */
  8449. -
  8450. -	/* Done sending packet, update counters and cleanup. */
  8451. -	dev->stats.tx_packets++;
  8452. -	dev->stats.tx_bytes += skb->len;
  8453. -	dev_kfree_skb (skb);
  8454. -	return NETDEV_TX_OK;
  8455. -}
  8456. -
  8457. -/*
  8458. - *	Dummy function to keep the Appletalk layer happy.
  8459. - */
  8460. - 
  8461. -static void set_multicast_list(struct net_device *dev)
  8462. -{
  8463. -        if(cops_debug >= 3)
  8464. -		printk("%s: set_multicast_list executed\n", dev->name);
  8465. -}
  8466. -
  8467. -/*
  8468. - *      System ioctls for the COPS LocalTalk card.
  8469. - */
  8470. - 
  8471. -static int cops_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
  8472. -{
  8473. -        struct cops_local *lp = netdev_priv(dev);
  8474. -        struct sockaddr_at *sa = (struct sockaddr_at *)&ifr->ifr_addr;
  8475. -        struct atalk_addr *aa = &lp->node_addr;
  8476. -
  8477. -        switch(cmd)
  8478. -        {
  8479. -                case SIOCSIFADDR:
  8480. -			/* Get and set the nodeid and network # atalkd wants. */
  8481. -			cops_nodeid(dev, sa->sat_addr.s_node);
  8482. -			aa->s_net               = sa->sat_addr.s_net;
  8483. -                        aa->s_node              = lp->node_acquire;
  8484. -
  8485. -			/* Set broardcast address. */
  8486. -                        dev->broadcast[0]       = 0xFF;
  8487. -			
  8488. -			/* Set hardware address. */
  8489. -                        dev->dev_addr[0]        = aa->s_node;
  8490. -                        dev->addr_len           = 1;
  8491. -                        return 0;
  8492. -
  8493. -                case SIOCGIFADDR:
  8494. -                        sa->sat_addr.s_net      = aa->s_net;
  8495. -                        sa->sat_addr.s_node     = aa->s_node;
  8496. -                        return 0;
  8497. -
  8498. -                default:
  8499. -                        return -EOPNOTSUPP;
  8500. -        }
  8501. -}
  8502. -
  8503. -/*
  8504. - *	The inverse routine to cops_open().
  8505. - */
  8506. - 
  8507. -static int cops_close(struct net_device *dev)
  8508. -{
  8509. -	struct cops_local *lp = netdev_priv(dev);
  8510. -
  8511. -	/* If we were running polled, yank the timer.
  8512. -	 */
  8513. -	if(lp->board==TANGENT && dev->irq==0)
  8514. -		del_timer(&cops_timer);
  8515. -
  8516. -	netif_stop_queue(dev);
  8517. -        return 0;
  8518. -}
  8519. -
  8520. -
  8521. -#ifdef MODULE
  8522. -static struct net_device *cops_dev;
  8523. -
  8524. -MODULE_LICENSE("GPL");
  8525. -module_param_hw(io, int, ioport, 0);
  8526. -module_param_hw(irq, int, irq, 0);
  8527. -module_param_hw(board_type, int, other, 0);
  8528. -
  8529. -static int __init cops_module_init(void)
  8530. -{
  8531. -	if (io == 0)
  8532. -		printk(KERN_WARNING "%s: You shouldn't autoprobe with insmod\n",
  8533. -			cardname);
  8534. -	cops_dev = cops_probe(-1);
  8535. -	return PTR_ERR_OR_ZERO(cops_dev);
  8536. -}
  8537. -
  8538. -static void __exit cops_module_exit(void)
  8539. -{
  8540. -	unregister_netdev(cops_dev);
  8541. -	cleanup_card(cops_dev);
  8542. -	free_netdev(cops_dev);
  8543. -}
  8544. -module_init(cops_module_init);
  8545. -module_exit(cops_module_exit);
  8546. -#endif /* MODULE */
  8547. diff -ruN ../linux-4.14.336/drivers/net/appletalk/cops.h ./drivers/net/appletalk/cops.h
  8548. --- linux-4.14.336/../linux-4.14.336/drivers/net/appletalk/cops.h	2024-01-10 14:45:41.000000000 +0100
  8549. +++ linux-4.14.336/./drivers/net/appletalk/cops.h	1970-01-01 01:00:00.000000000 +0100
  8550. @@ -1,61 +0,0 @@
  8551. -/* SPDX-License-Identifier: GPL-2.0 */
  8552. -/*      cops.h: LocalTalk driver for Linux.
  8553. - *
  8554. - *      Authors:
  8555. - *      - Jay Schulist <jschlst@samba.org>
  8556. - */
  8557. -
  8558. -#ifndef __LINUX_COPSLTALK_H
  8559. -#define __LINUX_COPSLTALK_H
  8560. -
  8561. -#ifdef __KERNEL__
  8562. -
  8563. -/* Max LLAP size we will accept. */
  8564. -#define MAX_LLAP_SIZE		603
  8565. -
  8566. -/* Tangent */
  8567. -#define TANG_CARD_STATUS        1
  8568. -#define TANG_CLEAR_INT          1
  8569. -#define TANG_RESET              3
  8570. -
  8571. -#define TANG_TX_READY           1
  8572. -#define TANG_RX_READY           2
  8573. -
  8574. -/* Dayna */
  8575. -#define DAYNA_CMD_DATA          0
  8576. -#define DAYNA_CLEAR_INT         1
  8577. -#define DAYNA_CARD_STATUS       2
  8578. -#define DAYNA_INT_CARD          3
  8579. -#define DAYNA_RESET             4
  8580. -
  8581. -#define DAYNA_RX_READY          0
  8582. -#define DAYNA_TX_READY          1
  8583. -#define DAYNA_RX_REQUEST        3
  8584. -
  8585. -/* Same on both card types */
  8586. -#define COPS_CLEAR_INT  1
  8587. -
  8588. -/* LAP response codes received from the cards. */
  8589. -#define LAP_INIT        1       /* Init cmd */
  8590. -#define LAP_INIT_RSP    2       /* Init response */
  8591. -#define LAP_WRITE       3       /* Write cmd */
  8592. -#define DATA_READ       4       /* Data read */
  8593. -#define LAP_RESPONSE    4       /* Received ALAP frame response */
  8594. -#define LAP_GETSTAT     5       /* Get LAP and HW status */
  8595. -#define LAP_RSPSTAT     6       /* Status response */
  8596. -
  8597. -#endif
  8598. -
  8599. -/*
  8600. - *	Structure to hold the firmware information.
  8601. - */
  8602. -struct ltfirmware
  8603. -{
  8604. -        unsigned int length;
  8605. -        const unsigned char *data;
  8606. -};
  8607. -
  8608. -#define DAYNA 1
  8609. -#define TANGENT 2
  8610. -
  8611. -#endif
  8612. diff -ruN ../linux-4.14.336/drivers/net/appletalk/cops_ffdrv.h ./drivers/net/appletalk/cops_ffdrv.h
  8613. --- linux-4.14.336/../linux-4.14.336/drivers/net/appletalk/cops_ffdrv.h	2024-01-10 14:45:41.000000000 +0100
  8614. +++ linux-4.14.336/./drivers/net/appletalk/cops_ffdrv.h	1970-01-01 01:00:00.000000000 +0100
  8615. @@ -1,532 +0,0 @@
  8616. -
  8617. -/*
  8618. - *	The firmware this driver downloads into the Localtalk card is a
  8619. - *	separate program and is not GPL'd source code, even though the Linux
  8620. - *	side driver and the routine that loads this data into the card are.
  8621. - *	
  8622. - *	It is taken from the COPS SDK and is under the following license
  8623. - *
  8624. - *	This material is licensed to you strictly for use in conjunction with
  8625. - *	the use of COPS LocalTalk adapters.
  8626. - *	There is no charge for this SDK. And no waranty express or implied
  8627. - *	about its fitness for any purpose. However, we will cheerefully
  8628. - *	refund every penny you paid for this SDK...
  8629. - *	Regards,
  8630. - *
  8631. - *	Thomas F. Divine
  8632. - *	Chief Scientist
  8633. - */
  8634. -
  8635. -
  8636. -/*      cops_ffdrv.h: LocalTalk driver firmware dump for Linux.
  8637. - *
  8638. - *      Authors:
  8639. - *      - Jay Schulist <jschlst@samba.org>
  8640. - */
  8641. -
  8642. -
  8643. -#ifdef CONFIG_COPS_DAYNA
  8644. -
  8645. -static const unsigned char ffdrv_code[] = {
  8646. -	58,3,0,50,228,149,33,255,255,34,226,149,
  8647. -	249,17,40,152,33,202,154,183,237,82,77,68,
  8648. -	11,107,98,19,54,0,237,176,175,50,80,0,
  8649. -	62,128,237,71,62,32,237,57,51,62,12,237,
  8650. -	57,50,237,57,54,62,6,237,57,52,62,12,
  8651. -	237,57,49,33,107,137,34,32,128,33,83,130,
  8652. -	34,40,128,33,86,130,34,42,128,33,112,130,
  8653. -	34,36,128,33,211,130,34,38,128,62,0,237,
  8654. -	57,16,33,63,148,34,34,128,237,94,205,15,
  8655. -	130,251,205,168,145,24,141,67,111,112,121,114,
  8656. -	105,103,104,116,32,40,67,41,32,49,57,56,
  8657. -	56,32,45,32,68,97,121,110,97,32,67,111,
  8658. -	109,109,117,110,105,99,97,116,105,111,110,115,
  8659. -	32,32,32,65,108,108,32,114,105,103,104,116,
  8660. -	115,32,114,101,115,101,114,118,101,100,46,32,
  8661. -	32,40,68,40,68,7,16,8,34,7,22,6,
  8662. -	16,5,12,4,8,3,6,140,0,16,39,128,
  8663. -	0,4,96,10,224,6,0,7,126,2,64,11,
  8664. -	118,12,6,13,0,14,193,15,0,5,96,3,
  8665. -	192,1,64,9,8,62,9,211,66,62,192,211,
  8666. -	66,62,100,61,32,253,6,28,33,205,129,14,
  8667. -	66,237,163,194,253,129,6,28,33,205,129,14,
  8668. -	64,237,163,194,9,130,201,62,47,50,71,152,
  8669. -	62,47,211,68,58,203,129,237,57,20,58,204,
  8670. -	129,237,57,21,33,77,152,54,132,205,233,129,
  8671. -	58,228,149,254,209,40,6,56,4,62,0,24,
  8672. -	2,219,96,33,233,149,119,230,62,33,232,149,
  8673. -	119,213,33,8,152,17,7,0,25,119,19,25,
  8674. -	119,209,201,251,237,77,245,197,213,229,221,229,
  8675. -	205,233,129,62,1,50,106,137,205,158,139,221,
  8676. -	225,225,209,193,241,251,237,77,245,197,213,219,
  8677. -	72,237,56,16,230,46,237,57,16,237,56,12,
  8678. -	58,72,152,183,32,26,6,20,17,128,2,237,
  8679. -	56,46,187,32,35,237,56,47,186,32,29,219,
  8680. -	72,230,1,32,3,5,32,232,175,50,72,152,
  8681. -	229,221,229,62,1,50,106,137,205,158,139,221,
  8682. -	225,225,24,25,62,1,50,72,152,58,201,129,
  8683. -	237,57,12,58,202,129,237,57,13,237,56,16,
  8684. -	246,17,237,57,16,209,193,241,251,237,77,245,
  8685. -	197,229,213,221,229,237,56,16,230,17,237,57,
  8686. -	16,237,56,20,58,34,152,246,16,246,8,211,
  8687. -	68,62,6,61,32,253,58,34,152,246,8,211,
  8688. -	68,58,203,129,237,57,20,58,204,129,237,57,
  8689. -	21,237,56,16,246,34,237,57,16,221,225,209,
  8690. -	225,193,241,251,237,77,33,2,0,57,126,230,
  8691. -	3,237,100,1,40,2,246,128,230,130,245,62,
  8692. -	5,211,64,241,211,64,201,229,213,243,237,56,
  8693. -	16,230,46,237,57,16,237,56,12,251,70,35,
  8694. -	35,126,254,175,202,77,133,254,129,202,15,133,
  8695. -	230,128,194,191,132,43,58,44,152,119,33,76,
  8696. -	152,119,35,62,132,119,120,254,255,40,4,58,
  8697. -	49,152,119,219,72,43,43,112,17,3,0,237,
  8698. -	56,52,230,248,237,57,52,219,72,230,1,194,
  8699. -	141,131,209,225,237,56,52,246,6,237,57,52,
  8700. -	62,1,55,251,201,62,3,211,66,62,192,211,
  8701. -	66,62,48,211,66,0,0,219,66,230,1,40,
  8702. -	4,219,67,24,240,205,203,135,58,75,152,254,
  8703. -	255,202,128,132,58,49,152,254,161,250,207,131,
  8704. -	58,34,152,211,68,62,10,211,66,62,128,211,
  8705. -	66,62,11,211,66,62,6,211,66,24,0,62,
  8706. -	14,211,66,62,33,211,66,62,1,211,66,62,
  8707. -	64,211,66,62,3,211,66,62,209,211,66,62,
  8708. -	100,71,219,66,230,1,32,6,5,32,247,195,
  8709. -	248,132,219,67,71,58,44,152,184,194,248,132,
  8710. -	62,100,71,219,66,230,1,32,6,5,32,247,
  8711. -	195,248,132,219,67,62,100,71,219,66,230,1,
  8712. -	32,6,5,32,247,195,248,132,219,67,254,133,
  8713. -	32,7,62,0,50,74,152,24,17,254,173,32,
  8714. -	7,62,1,50,74,152,24,6,254,141,194,248,
  8715. -	132,71,209,225,58,49,152,254,132,32,10,62,
  8716. -	50,205,2,134,205,144,135,24,27,254,140,32,
  8717. -	15,62,110,205,2,134,62,141,184,32,5,205,
  8718. -	144,135,24,8,62,10,205,2,134,205,8,134,
  8719. -	62,1,50,106,137,205,158,139,237,56,52,246,
  8720. -	6,237,57,52,175,183,251,201,62,20,135,237,
  8721. -	57,20,175,237,57,21,237,56,16,246,2,237,
  8722. -	57,16,237,56,20,95,237,56,21,123,254,10,
  8723. -	48,244,237,56,16,230,17,237,57,16,209,225,
  8724. -	205,144,135,62,1,50,106,137,205,158,139,237,
  8725. -	56,52,246,6,237,57,52,175,183,251,201,209,
  8726. -	225,243,219,72,230,1,40,13,62,10,211,66,
  8727. -	0,0,219,66,230,192,202,226,132,237,56,52,
  8728. -	246,6,237,57,52,62,1,55,251,201,205,203,
  8729. -	135,62,1,50,106,137,205,158,139,237,56,52,
  8730. -	246,6,237,57,52,183,251,201,209,225,62,1,
  8731. -	50,106,137,205,158,139,237,56,52,246,6,237,
  8732. -	57,52,62,2,55,251,201,209,225,243,219,72,
  8733. -	230,1,202,213,132,62,10,211,66,0,0,219,
  8734. -	66,230,192,194,213,132,229,62,1,50,106,137,
  8735. -	42,40,152,205,65,143,225,17,3,0,205,111,
  8736. -	136,62,6,211,66,58,44,152,211,66,237,56,
  8737. -	52,246,6,237,57,52,183,251,201,209,197,237,
  8738. -	56,52,230,248,237,57,52,219,72,230,1,32,
  8739. -	15,193,225,237,56,52,246,6,237,57,52,62,
  8740. -	1,55,251,201,14,23,58,37,152,254,0,40,
  8741. -	14,14,2,254,1,32,5,62,140,119,24,3,
  8742. -	62,132,119,43,43,197,205,203,135,193,62,1,
  8743. -	211,66,62,64,211,66,62,3,211,66,62,193,
  8744. -	211,66,62,100,203,39,71,219,66,230,1,32,
  8745. -	6,5,32,247,195,229,133,33,238,151,219,67,
  8746. -	71,58,44,152,184,194,229,133,119,62,100,71,
  8747. -	219,66,230,1,32,6,5,32,247,195,229,133,
  8748. -	219,67,35,119,13,32,234,193,225,62,1,50,
  8749. -	106,137,205,158,139,237,56,52,246,6,237,57,
  8750. -	52,175,183,251,201,33,234,151,35,35,62,255,
  8751. -	119,193,225,62,1,50,106,137,205,158,139,237,
  8752. -	56,52,246,6,237,57,52,175,251,201,243,61,
  8753. -	32,253,251,201,62,3,211,66,62,192,211,66,
  8754. -	58,49,152,254,140,32,19,197,229,213,17,181,
  8755. -	129,33,185,129,1,2,0,237,176,209,225,193,
  8756. -	24,27,229,213,33,187,129,58,49,152,230,15,
  8757. -	87,30,2,237,92,25,17,181,129,126,18,19,
  8758. -	35,126,18,209,225,58,34,152,246,8,211,68,
  8759. -	58,49,152,254,165,40,14,254,164,40,10,62,
  8760. -	10,211,66,62,224,211,66,24,25,58,74,152,
  8761. -	254,0,40,10,62,10,211,66,62,160,211,66,
  8762. -	24,8,62,10,211,66,62,128,211,66,62,11,
  8763. -	211,66,62,6,211,66,205,147,143,62,5,211,
  8764. -	66,62,224,211,66,62,5,211,66,62,96,211,
  8765. -	66,62,5,61,32,253,62,5,211,66,62,224,
  8766. -	211,66,62,14,61,32,253,62,5,211,66,62,
  8767. -	233,211,66,62,128,211,66,58,181,129,61,32,
  8768. -	253,62,1,211,66,62,192,211,66,1,254,19,
  8769. -	237,56,46,187,32,6,13,32,247,195,226,134,
  8770. -	62,192,211,66,0,0,219,66,203,119,40,250,
  8771. -	219,66,203,87,40,250,243,237,56,16,230,17,
  8772. -	237,57,16,237,56,20,251,62,5,211,66,62,
  8773. -	224,211,66,58,182,129,61,32,253,229,33,181,
  8774. -	129,58,183,129,203,63,119,35,58,184,129,119,
  8775. -	225,62,10,211,66,62,224,211,66,62,11,211,
  8776. -	66,62,118,211,66,62,47,211,68,62,5,211,
  8777. -	66,62,233,211,66,58,181,129,61,32,253,62,
  8778. -	5,211,66,62,224,211,66,58,182,129,61,32,
  8779. -	253,62,5,211,66,62,96,211,66,201,229,213,
  8780. -	58,50,152,230,15,87,30,2,237,92,33,187,
  8781. -	129,25,17,181,129,126,18,35,19,126,18,209,
  8782. -	225,58,71,152,246,8,211,68,58,50,152,254,
  8783. -	165,40,14,254,164,40,10,62,10,211,66,62,
  8784. -	224,211,66,24,8,62,10,211,66,62,128,211,
  8785. -	66,62,11,211,66,62,6,211,66,195,248,135,
  8786. -	62,3,211,66,62,192,211,66,197,229,213,17,
  8787. -	181,129,33,183,129,1,2,0,237,176,209,225,
  8788. -	193,62,47,211,68,62,10,211,66,62,224,211,
  8789. -	66,62,11,211,66,62,118,211,66,62,1,211,
  8790. -	66,62,0,211,66,205,147,143,195,16,136,62,
  8791. -	3,211,66,62,192,211,66,197,229,213,17,181,
  8792. -	129,33,183,129,1,2,0,237,176,209,225,193,
  8793. -	62,47,211,68,62,10,211,66,62,224,211,66,
  8794. -	62,11,211,66,62,118,211,66,205,147,143,62,
  8795. -	5,211,66,62,224,211,66,62,5,211,66,62,
  8796. -	96,211,66,62,5,61,32,253,62,5,211,66,
  8797. -	62,224,211,66,62,14,61,32,253,62,5,211,
  8798. -	66,62,233,211,66,62,128,211,66,58,181,129,
  8799. -	61,32,253,62,1,211,66,62,192,211,66,1,
  8800. -	254,19,237,56,46,187,32,6,13,32,247,195,
  8801. -	88,136,62,192,211,66,0,0,219,66,203,119,
  8802. -	40,250,219,66,203,87,40,250,62,5,211,66,
  8803. -	62,224,211,66,58,182,129,61,32,253,62,5,
  8804. -	211,66,62,96,211,66,201,197,14,67,6,0,
  8805. -	62,3,211,66,62,192,211,66,62,48,211,66,
  8806. -	0,0,219,66,230,1,40,4,219,67,24,240,
  8807. -	62,5,211,66,62,233,211,66,62,128,211,66,
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  8811. -	4,40,3,5,32,247,219,66,230,4,40,250,
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  8832. -	194,210,138,35,35,62,130,190,194,200,137,62,
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  8835. -	175,50,106,137,42,40,152,205,65,143,225,54,
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  8843. -	152,230,15,87,126,31,21,242,65,138,56,2,
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  8845. -	62,31,21,242,85,138,218,98,138,209,225,195,
  8846. -	20,139,58,50,152,33,100,137,230,15,95,22,
  8847. -	0,25,126,50,71,152,209,225,58,50,152,254,
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  8849. -	173,24,2,54,133,43,70,58,44,152,119,43,
  8850. -	112,17,3,0,205,70,135,175,50,106,137,205,
  8851. -	208,139,58,199,129,237,57,12,58,200,129,237,
  8852. -	57,13,237,56,16,246,17,237,57,16,225,209,
  8853. -	193,241,251,237,77,62,129,190,194,227,138,54,
  8854. -	130,43,70,58,44,152,119,43,112,17,3,0,
  8855. -	205,144,135,195,20,139,35,35,126,254,132,194,
  8856. -	227,138,175,50,106,137,205,158,139,24,42,58,
  8857. -	201,154,254,1,40,7,62,1,50,106,137,24,
  8858. -	237,58,106,137,254,1,202,222,138,62,128,166,
  8859. -	194,222,138,221,229,221,33,67,152,205,127,142,
  8860. -	205,109,144,221,225,225,209,193,241,251,237,77,
  8861. -	58,106,137,254,1,202,44,139,58,50,152,254,
  8862. -	164,250,44,139,58,73,152,238,1,50,73,152,
  8863. -	221,229,221,33,51,152,205,127,142,221,225,62,
  8864. -	1,50,106,137,205,158,139,195,13,139,24,208,
  8865. -	24,206,24,204,230,64,40,3,195,20,139,195,
  8866. -	20,139,43,126,33,8,152,119,35,58,44,152,
  8867. -	119,43,237,91,35,152,205,203,135,205,158,139,
  8868. -	195,13,139,175,50,78,152,62,3,211,66,62,
  8869. -	192,211,66,201,197,33,4,0,57,126,35,102,
  8870. -	111,62,1,50,106,137,219,72,205,141,139,193,
  8871. -	201,62,1,50,78,152,34,40,152,54,0,35,
  8872. -	35,54,0,195,163,139,58,78,152,183,200,229,
  8873. -	33,181,129,58,183,129,119,35,58,184,129,119,
  8874. -	225,62,47,211,68,62,14,211,66,62,193,211,
  8875. -	66,62,10,211,66,62,224,211,66,62,11,211,
  8876. -	66,62,118,211,66,195,3,140,58,78,152,183,
  8877. -	200,58,71,152,211,68,254,69,40,4,254,70,
  8878. -	32,17,58,73,152,254,0,40,10,62,10,211,
  8879. -	66,62,160,211,66,24,8,62,10,211,66,62,
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  8881. -	6,211,66,58,44,152,211,66,62,16,211,66,
  8882. -	62,56,211,66,62,48,211,66,0,0,219,66,
  8883. -	230,1,40,4,219,67,24,240,62,14,211,66,
  8884. -	62,33,211,66,42,40,152,205,65,143,62,1,
  8885. -	211,66,62,248,211,66,237,56,48,246,145,246,
  8886. -	8,230,207,237,57,48,62,3,211,66,62,221,
  8887. -	211,66,201,62,16,211,66,62,56,211,66,62,
  8888. -	48,211,66,0,0,219,66,230,1,40,4,219,
  8889. -	67,24,240,62,14,211,66,62,33,211,66,62,
  8890. -	1,211,66,62,248,211,66,237,56,48,246,153,
  8891. -	230,207,237,57,48,62,3,211,66,62,221,211,
  8892. -	66,201,229,213,33,234,149,95,22,0,25,126,
  8893. -	254,132,40,4,254,140,32,2,175,119,123,209,
  8894. -	225,201,6,8,14,0,31,48,1,12,16,250,
  8895. -	121,201,33,4,0,57,94,35,86,33,2,0,
  8896. -	57,126,35,102,111,221,229,34,89,152,237,83,
  8897. -	91,152,221,33,63,152,205,127,142,58,81,152,
  8898. -	50,82,152,58,80,152,135,50,80,152,205,162,
  8899. -	140,254,3,56,16,58,81,152,135,60,230,15,
  8900. -	50,81,152,175,50,80,152,24,23,58,79,152,
  8901. -	205,162,140,254,3,48,13,58,81,152,203,63,
  8902. -	50,81,152,62,255,50,79,152,58,81,152,50,
  8903. -	82,152,58,79,152,135,50,79,152,62,32,50,
  8904. -	83,152,50,84,152,237,56,16,230,17,237,57,
  8905. -	16,219,72,62,192,50,93,152,62,93,50,94,
  8906. -	152,58,93,152,61,50,93,152,32,9,58,94,
  8907. -	152,61,50,94,152,40,44,62,170,237,57,20,
  8908. -	175,237,57,21,237,56,16,246,2,237,57,16,
  8909. -	219,72,230,1,202,29,141,237,56,20,71,237,
  8910. -	56,21,120,254,10,48,237,237,56,16,230,17,
  8911. -	237,57,16,243,62,14,211,66,62,65,211,66,
  8912. -	251,58,39,152,23,23,60,50,39,152,71,58,
  8913. -	82,152,160,230,15,40,22,71,14,10,219,66,
  8914. -	230,16,202,186,141,219,72,230,1,202,186,141,
  8915. -	13,32,239,16,235,42,89,152,237,91,91,152,
  8916. -	205,47,131,48,7,61,202,186,141,195,227,141,
  8917. -	221,225,33,0,0,201,221,33,55,152,205,127,
  8918. -	142,58,84,152,61,50,84,152,40,19,58,82,
  8919. -	152,246,1,50,82,152,58,79,152,246,1,50,
  8920. -	79,152,195,29,141,221,225,33,1,0,201,221,
  8921. -	33,59,152,205,127,142,58,80,152,246,1,50,
  8922. -	80,152,58,82,152,135,246,1,50,82,152,58,
  8923. -	83,152,61,50,83,152,194,29,141,221,225,33,
  8924. -	2,0,201,221,229,33,0,0,57,17,4,0,
  8925. -	25,126,50,44,152,230,128,50,85,152,58,85,
  8926. -	152,183,40,6,221,33,88,2,24,4,221,33,
  8927. -	150,0,58,44,152,183,40,53,60,40,50,60,
  8928. -	40,47,61,61,33,86,152,119,35,119,35,54,
  8929. -	129,175,50,48,152,221,43,221,229,225,124,181,
  8930. -	40,42,33,86,152,17,3,0,205,189,140,17,
  8931. -	232,3,27,123,178,32,251,58,48,152,183,40,
  8932. -	224,58,44,152,71,62,7,128,230,127,71,58,
  8933. -	85,152,176,50,44,152,24,162,221,225,201,183,
  8934. -	221,52,0,192,221,52,1,192,221,52,2,192,
  8935. -	221,52,3,192,55,201,245,62,1,211,100,241,
  8936. -	201,245,62,1,211,96,241,201,33,2,0,57,
  8937. -	126,35,102,111,237,56,48,230,175,237,57,48,
  8938. -	62,48,237,57,49,125,237,57,32,124,237,57,
  8939. -	33,62,0,237,57,34,62,88,237,57,35,62,
  8940. -	0,237,57,36,237,57,37,33,128,2,125,237,
  8941. -	57,38,124,237,57,39,237,56,48,246,97,230,
  8942. -	207,237,57,48,62,0,237,57,0,62,0,211,
  8943. -	96,211,100,201,33,2,0,57,126,35,102,111,
  8944. -	237,56,48,230,175,237,57,48,62,12,237,57,
  8945. -	49,62,76,237,57,32,62,0,237,57,33,237,
  8946. -	57,34,125,237,57,35,124,237,57,36,62,0,
  8947. -	237,57,37,33,128,2,125,237,57,38,124,237,
  8948. -	57,39,237,56,48,246,97,230,207,237,57,48,
  8949. -	62,1,211,96,201,33,2,0,57,126,35,102,
  8950. -	111,229,237,56,48,230,87,237,57,48,125,237,
  8951. -	57,40,124,237,57,41,62,0,237,57,42,62,
  8952. -	67,237,57,43,62,0,237,57,44,58,106,137,
  8953. -	254,1,32,5,33,6,0,24,3,33,128,2,
  8954. -	125,237,57,46,124,237,57,47,237,56,50,230,
  8955. -	252,246,2,237,57,50,225,201,33,4,0,57,
  8956. -	94,35,86,33,2,0,57,126,35,102,111,237,
  8957. -	56,48,230,87,237,57,48,125,237,57,40,124,
  8958. -	237,57,41,62,0,237,57,42,62,67,237,57,
  8959. -	43,62,0,237,57,44,123,237,57,46,122,237,
  8960. -	57,47,237,56,50,230,244,246,0,237,57,50,
  8961. -	237,56,48,246,145,230,207,237,57,48,201,213,
  8962. -	237,56,46,95,237,56,47,87,237,56,46,111,
  8963. -	237,56,47,103,183,237,82,32,235,33,128,2,
  8964. -	183,237,82,209,201,213,237,56,38,95,237,56,
  8965. -	39,87,237,56,38,111,237,56,39,103,183,237,
  8966. -	82,32,235,33,128,2,183,237,82,209,201,245,
  8967. -	197,1,52,0,237,120,230,253,237,121,193,241,
  8968. -	201,245,197,1,52,0,237,120,246,2,237,121,
  8969. -	193,241,201,33,2,0,57,126,35,102,111,126,
  8970. -	35,110,103,201,33,0,0,34,102,152,34,96,
  8971. -	152,34,98,152,33,202,154,34,104,152,237,91,
  8972. -	104,152,42,226,149,183,237,82,17,0,255,25,
  8973. -	34,100,152,203,124,40,6,33,0,125,34,100,
  8974. -	152,42,104,152,35,35,35,229,205,120,139,193,
  8975. -	201,205,186,149,229,42,40,152,35,35,35,229,
  8976. -	205,39,144,193,124,230,3,103,221,117,254,221,
  8977. -	116,255,237,91,42,152,35,35,35,183,237,82,
  8978. -	32,12,17,5,0,42,42,152,205,171,149,242,
  8979. -	169,144,42,40,152,229,205,120,139,193,195,198,
  8980. -	149,237,91,42,152,42,98,152,25,34,98,152,
  8981. -	19,19,19,42,102,152,25,34,102,152,237,91,
  8982. -	100,152,33,158,253,25,237,91,102,152,205,171,
  8983. -	149,242,214,144,33,0,0,34,102,152,62,1,
  8984. -	50,95,152,205,225,144,195,198,149,58,95,152,
  8985. -	183,200,237,91,96,152,42,102,152,205,171,149,
  8986. -	242,5,145,237,91,102,152,33,98,2,25,237,
  8987. -	91,96,152,205,171,149,250,37,145,237,91,96,
  8988. -	152,42,102,152,183,237,82,32,7,42,98,152,
  8989. -	125,180,40,13,237,91,102,152,42,96,152,205,
  8990. -	171,149,242,58,145,237,91,104,152,42,102,152,
  8991. -	25,35,35,35,229,205,120,139,193,175,50,95,
  8992. -	152,201,195,107,139,205,206,149,250,255,243,205,
  8993. -	225,144,251,58,230,149,183,194,198,149,17,1,
  8994. -	0,42,98,152,205,171,149,250,198,149,62,1,
  8995. -	50,230,149,237,91,96,152,42,104,152,25,221,
  8996. -	117,252,221,116,253,237,91,104,152,42,96,152,
  8997. -	25,35,35,35,221,117,254,221,116,255,35,35,
  8998. -	35,229,205,39,144,124,230,3,103,35,35,35,
  8999. -	221,117,250,221,116,251,235,221,110,252,221,102,
  9000. -	253,115,35,114,35,54,4,62,1,211,100,211,
  9001. -	84,195,198,149,33,0,0,34,102,152,34,96,
  9002. -	152,34,98,152,33,202,154,34,104,152,237,91,
  9003. -	104,152,42,226,149,183,237,82,17,0,255,25,
  9004. -	34,100,152,33,109,152,54,0,33,107,152,229,
  9005. -	205,240,142,193,62,47,50,34,152,62,132,50,
  9006. -	49,152,205,241,145,205,61,145,58,39,152,60,
  9007. -	50,39,152,24,241,205,206,149,251,255,33,109,
  9008. -	152,126,183,202,198,149,110,221,117,251,33,109,
  9009. -	152,54,0,221,126,251,254,1,40,28,254,3,
  9010. -	40,101,254,4,202,190,147,254,5,202,147,147,
  9011. -	254,8,40,87,33,107,152,229,205,240,142,195,
  9012. -	198,149,58,201,154,183,32,21,33,111,152,126,
  9013. -	50,229,149,205,52,144,33,110,152,110,38,0,
  9014. -	229,205,11,142,193,237,91,96,152,42,104,152,
  9015. -	25,221,117,254,221,116,255,35,35,54,2,17,
  9016. -	2,0,43,43,115,35,114,58,44,152,35,35,
  9017. -	119,58,228,149,35,119,62,1,211,100,211,84,
  9018. -	62,1,50,201,154,24,169,205,153,142,58,231,
  9019. -	149,183,40,250,175,50,231,149,33,110,152,126,
  9020. -	254,255,40,91,58,233,149,230,63,183,40,83,
  9021. -	94,22,0,33,234,149,25,126,183,40,13,33,
  9022. -	110,152,94,33,234,150,25,126,254,3,32,36,
  9023. -	205,81,148,125,180,33,110,152,94,22,0,40,
  9024. -	17,33,234,149,25,54,0,33,107,152,229,205,
  9025. -	240,142,193,195,198,149,33,234,150,25,54,0,
  9026. -	33,110,152,94,22,0,33,234,149,25,126,50,
  9027. -	49,152,254,132,32,37,62,47,50,34,152,42,
  9028. -	107,152,229,33,110,152,229,205,174,140,193,193,
  9029. -	125,180,33,110,152,94,22,0,33,234,150,202,
  9030. -	117,147,25,52,195,120,147,58,49,152,254,140,
  9031. -	32,7,62,1,50,34,152,24,210,62,32,50,
  9032. -	106,152,24,19,58,49,152,95,58,106,152,163,
  9033. -	183,58,106,152,32,11,203,63,50,106,152,58,
  9034. -	106,152,183,32,231,254,2,40,51,254,4,40,
  9035. -	38,254,8,40,26,254,16,40,13,254,32,32,
  9036. -	158,62,165,50,49,152,62,69,24,190,62,164,
  9037. -	50,49,152,62,70,24,181,62,163,50,49,152,
  9038. -	175,24,173,62,162,50,49,152,62,1,24,164,
  9039. -	62,161,50,49,152,62,3,24,155,25,54,0,
  9040. -	221,126,251,254,8,40,7,58,230,149,183,202,
  9041. -	32,146,33,107,152,229,205,240,142,193,211,84,
  9042. -	195,198,149,237,91,96,152,42,104,152,25,221,
  9043. -	117,254,221,116,255,35,35,54,6,17,2,0,
  9044. -	43,43,115,35,114,58,228,149,35,35,119,58,
  9045. -	233,149,35,119,205,146,142,195,32,146,237,91,
  9046. -	96,152,42,104,152,25,229,205,160,142,193,58,
  9047. -	231,149,183,40,250,175,50,231,149,243,237,91,
  9048. -	96,152,42,104,152,25,221,117,254,221,116,255,
  9049. -	78,35,70,221,113,252,221,112,253,89,80,42,
  9050. -	98,152,183,237,82,34,98,152,203,124,40,19,
  9051. -	33,0,0,34,98,152,34,102,152,34,96,152,
  9052. -	62,1,50,95,152,24,40,221,94,252,221,86,
  9053. -	253,19,19,19,42,96,152,25,34,96,152,237,
  9054. -	91,100,152,33,158,253,25,237,91,96,152,205,
  9055. -	171,149,242,55,148,33,0,0,34,96,152,175,
  9056. -	50,230,149,251,195,32,146,245,62,1,50,231,
  9057. -	149,62,16,237,57,0,211,80,241,251,237,77,
  9058. -	201,205,186,149,229,229,33,0,0,34,37,152,
  9059. -	33,110,152,126,50,234,151,58,44,152,33,235,
  9060. -	151,119,221,54,253,0,221,54,254,0,195,230,
  9061. -	148,33,236,151,54,175,33,3,0,229,33,234,
  9062. -	151,229,205,174,140,193,193,33,236,151,126,254,
  9063. -	255,40,74,33,245,151,110,221,117,255,33,249,
  9064. -	151,126,221,166,255,221,119,255,33,253,151,126,
  9065. -	221,166,255,221,119,255,58,232,149,95,221,126,
  9066. -	255,163,221,119,255,183,40,15,230,191,33,110,
  9067. -	152,94,22,0,33,234,149,25,119,24,12,33,
  9068. -	110,152,94,22,0,33,234,149,25,54,132,33,
  9069. -	0,0,195,198,149,221,110,253,221,102,254,35,
  9070. -	221,117,253,221,116,254,17,32,0,221,110,253,
  9071. -	221,102,254,205,171,149,250,117,148,58,233,149,
  9072. -	203,87,40,84,33,1,0,34,37,152,221,54,
  9073. -	253,0,221,54,254,0,24,53,33,236,151,54,
  9074. -	175,33,3,0,229,33,234,151,229,205,174,140,
  9075. -	193,193,33,236,151,126,254,255,40,14,33,110,
  9076. -	152,94,22,0,33,234,149,25,54,140,24,159,
  9077. -	221,110,253,221,102,254,35,221,117,253,221,116,
  9078. -	254,17,32,0,221,110,253,221,102,254,205,171,
  9079. -	149,250,12,149,33,2,0,34,37,152,221,54,
  9080. -	253,0,221,54,254,0,24,54,33,236,151,54,
  9081. -	175,33,3,0,229,33,234,151,229,205,174,140,
  9082. -	193,193,33,236,151,126,254,255,40,15,33,110,
  9083. -	152,94,22,0,33,234,149,25,54,132,195,211,
  9084. -	148,221,110,253,221,102,254,35,221,117,253,221,
  9085. -	116,254,17,32,0,221,110,253,221,102,254,205,
  9086. -	171,149,250,96,149,33,1,0,195,198,149,124,
  9087. -	170,250,179,149,237,82,201,124,230,128,237,82,
  9088. -	60,201,225,253,229,221,229,221,33,0,0,221,
  9089. -	57,233,221,249,221,225,253,225,201,233,225,253,
  9090. -	229,221,229,221,33,0,0,221,57,94,35,86,
  9091. -	35,235,57,249,235,233,0,0,0,0,0,0,
  9092. -	62,0,0,0,0,0,0,0,0,0,0,0,
  9093. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9094. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9095. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9096. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9097. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9098. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9099. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9100. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9101. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9102. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9103. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9104. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9105. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9106. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9107. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9108. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9109. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9110. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9111. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9112. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9113. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9114. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9115. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9116. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9117. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9118. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9119. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9120. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9121. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9122. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9123. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9124. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9125. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9126. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9127. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9128. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9129. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9130. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9131. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9132. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9133. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9134. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9135. -	175,0,0,0,0,0,0,0,0,0,0,0,
  9136. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9137. -	0,0,0,0,0,0,133,1,0,0,0,63,
  9138. -	255,255,255,255,0,0,0,63,0,0,0,0,
  9139. -	0,0,0,0,0,0,0,24,0,0,0,0,
  9140. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9141. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9142. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9143. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9144. -	0,0,0,0,0,0,0
  9145. -	} ;
  9146. -
  9147. -#endif
  9148. diff -ruN ../linux-4.14.336/drivers/net/appletalk/cops_ltdrv.h ./drivers/net/appletalk/cops_ltdrv.h
  9149. --- linux-4.14.336/../linux-4.14.336/drivers/net/appletalk/cops_ltdrv.h	2024-01-10 14:45:41.000000000 +0100
  9150. +++ linux-4.14.336/./drivers/net/appletalk/cops_ltdrv.h	1970-01-01 01:00:00.000000000 +0100
  9151. @@ -1,241 +0,0 @@
  9152. -/*
  9153. - *	The firmware this driver downloads into the Localtalk card is a
  9154. - *	separate program and is not GPL'd source code, even though the Linux
  9155. - *	side driver and the routine that loads this data into the card are.
  9156. - *	
  9157. - *	It is taken from the COPS SDK and is under the following license
  9158. - *
  9159. - *	This material is licensed to you strictly for use in conjunction with
  9160. - *	the use of COPS LocalTalk adapters.
  9161. - *	There is no charge for this SDK. And no waranty express or implied
  9162. - *	about its fitness for any purpose. However, we will cheerefully
  9163. - *	refund every penny you paid for this SDK...
  9164. - *	Regards,
  9165. - *
  9166. - *	Thomas F. Divine
  9167. - *	Chief Scientist
  9168. - */
  9169. -
  9170. -
  9171. -/*      cops_ltdrv.h: LocalTalk driver firmware dump for Linux.
  9172. - *
  9173. - *      Authors:
  9174. - *      - Jay Schulist <jschlst@samba.org>
  9175. - */
  9176. - 
  9177. -
  9178. -#ifdef CONFIG_COPS_TANGENT
  9179. -
  9180. -static const unsigned char ltdrv_code[] = {
  9181. -	58,3,0,50,148,10,33,143,15,62,85,119,
  9182. -	190,32,9,62,170,119,190,32,3,35,24,241,
  9183. -	34,146,10,249,17,150,10,33,143,15,183,237,
  9184. -	82,77,68,11,107,98,19,54,0,237,176,62,
  9185. -	16,237,57,51,62,0,237,57,50,237,57,54,
  9186. -	62,12,237,57,49,62,195,33,39,2,50,56,
  9187. -	0,34,57,0,237,86,205,30,2,251,205,60,
  9188. -	10,24,169,67,111,112,121,114,105,103,104,116,
  9189. -	32,40,99,41,32,49,57,56,56,45,49,57,
  9190. -	57,50,44,32,80,114,105,110,116,105,110,103,
  9191. -	32,67,111,109,109,117,110,105,99,97,116,105,
  9192. -	111,110,115,32,65,115,115,111,99,105,97,116,
  9193. -	101,115,44,32,73,110,99,46,65,108,108,32,
  9194. -	114,105,103,104,116,115,32,114,101,115,101,114,
  9195. -	118,101,100,46,32,32,4,4,22,40,255,60,
  9196. -	4,96,10,224,6,0,7,126,2,64,11,246,
  9197. -	12,6,13,0,14,193,15,0,5,96,3,192,
  9198. -	1,0,9,8,62,3,211,82,62,192,211,82,
  9199. -	201,62,3,211,82,62,213,211,82,201,62,5,
  9200. -	211,82,62,224,211,82,201,62,5,211,82,62,
  9201. -	224,211,82,201,62,5,211,82,62,96,211,82,
  9202. -	201,6,28,33,180,1,14,82,237,163,194,4,
  9203. -	2,33,39,2,34,64,0,58,3,0,230,1,
  9204. -	192,62,11,237,121,62,118,237,121,201,33,182,
  9205. -	10,54,132,205,253,1,201,245,197,213,229,42,
  9206. -	150,10,14,83,17,98,2,67,20,237,162,58,
  9207. -	179,1,95,219,82,230,1,32,6,29,32,247,
  9208. -	195,17,3,62,1,211,82,219,82,95,230,160,
  9209. -	32,10,237,162,32,225,21,32,222,195,15,3,
  9210. -	237,162,123,230,96,194,21,3,62,48,211,82,
  9211. -	62,1,211,82,175,211,82,237,91,150,10,43,
  9212. -	55,237,82,218,19,3,34,152,10,98,107,58,
  9213. -	154,10,190,32,81,62,1,50,158,10,35,35,
  9214. -	62,132,190,32,44,54,133,43,70,58,154,10,
  9215. -	119,43,112,17,3,0,205,137,3,62,16,211,
  9216. -	82,62,56,211,82,205,217,1,42,150,10,14,
  9217. -	83,17,98,2,67,20,58,178,1,95,195,59,
  9218. -	2,62,129,190,194,227,2,54,130,43,70,58,
  9219. -	154,10,119,43,112,17,3,0,205,137,3,195,
  9220. -	254,2,35,35,126,254,132,194,227,2,205,61,
  9221. -	3,24,20,62,128,166,194,222,2,221,229,221,
  9222. -	33,175,10,205,93,6,205,144,7,221,225,225,
  9223. -	209,193,241,251,237,77,221,229,221,33,159,10,
  9224. -	205,93,6,221,225,205,61,3,195,247,2,24,
  9225. -	237,24,235,24,233,230,64,40,2,24,227,24,
  9226. -	225,175,50,179,10,205,208,1,201,197,33,4,
  9227. -	0,57,126,35,102,111,205,51,3,193,201,62,
  9228. -	1,50,179,10,34,150,10,54,0,58,179,10,
  9229. -	183,200,62,14,211,82,62,193,211,82,62,10,
  9230. -	211,82,62,224,211,82,62,6,211,82,58,154,
  9231. -	10,211,82,62,16,211,82,62,56,211,82,62,
  9232. -	48,211,82,219,82,230,1,40,4,219,83,24,
  9233. -	242,62,14,211,82,62,33,211,82,62,1,211,
  9234. -	82,62,9,211,82,62,32,211,82,205,217,1,
  9235. -	201,14,83,205,208,1,24,23,14,83,205,208,
  9236. -	1,205,226,1,58,174,1,61,32,253,205,244,
  9237. -	1,58,174,1,61,32,253,205,226,1,58,175,
  9238. -	1,61,32,253,62,5,211,82,62,233,211,82,
  9239. -	62,128,211,82,58,176,1,61,32,253,237,163,
  9240. -	27,62,192,211,82,219,82,230,4,40,250,237,
  9241. -	163,27,122,179,32,243,219,82,230,4,40,250,
  9242. -	58,178,1,71,219,82,230,4,40,3,5,32,
  9243. -	247,219,82,230,4,40,250,205,235,1,58,177,
  9244. -	1,61,32,253,205,244,1,201,229,213,35,35,
  9245. -	126,230,128,194,145,4,43,58,154,10,119,43,
  9246. -	70,33,181,10,119,43,112,17,3,0,243,62,
  9247. -	10,211,82,219,82,230,128,202,41,4,209,225,
  9248. -	62,1,55,251,201,205,144,3,58,180,10,254,
  9249. -	255,202,127,4,205,217,1,58,178,1,71,219,
  9250. -	82,230,1,32,6,5,32,247,195,173,4,219,
  9251. -	83,71,58,154,10,184,194,173,4,58,178,1,
  9252. -	71,219,82,230,1,32,6,5,32,247,195,173,
  9253. -	4,219,83,58,178,1,71,219,82,230,1,32,
  9254. -	6,5,32,247,195,173,4,219,83,254,133,194,
  9255. -	173,4,58,179,1,24,4,58,179,1,135,61,
  9256. -	32,253,209,225,205,137,3,205,61,3,183,251,
  9257. -	201,209,225,243,62,10,211,82,219,82,230,128,
  9258. -	202,164,4,62,1,55,251,201,205,144,3,205,
  9259. -	61,3,183,251,201,209,225,62,2,55,251,201,
  9260. -	243,62,14,211,82,62,33,211,82,251,201,33,
  9261. -	4,0,57,94,35,86,33,2,0,57,126,35,
  9262. -	102,111,221,229,34,193,10,237,83,195,10,221,
  9263. -	33,171,10,205,93,6,58,185,10,50,186,10,
  9264. -	58,184,10,135,50,184,10,205,112,6,254,3,
  9265. -	56,16,58,185,10,135,60,230,15,50,185,10,
  9266. -	175,50,184,10,24,23,58,183,10,205,112,6,
  9267. -	254,3,48,13,58,185,10,203,63,50,185,10,
  9268. -	62,255,50,183,10,58,185,10,50,186,10,58,
  9269. -	183,10,135,50,183,10,62,32,50,187,10,50,
  9270. -	188,10,6,255,219,82,230,16,32,3,5,32,
  9271. -	247,205,180,4,6,40,219,82,230,16,40,3,
  9272. -	5,32,247,62,10,211,82,219,82,230,128,194,
  9273. -	46,5,219,82,230,16,40,214,237,95,71,58,
  9274. -	186,10,160,230,15,40,32,71,14,10,62,10,
  9275. -	211,82,219,82,230,128,202,119,5,205,180,4,
  9276. -	195,156,5,219,82,230,16,202,156,5,13,32,
  9277. -	229,16,225,42,193,10,237,91,195,10,205,252,
  9278. -	3,48,7,61,202,156,5,195,197,5,221,225,
  9279. -	33,0,0,201,221,33,163,10,205,93,6,58,
  9280. -	188,10,61,50,188,10,40,19,58,186,10,246,
  9281. -	1,50,186,10,58,183,10,246,1,50,183,10,
  9282. -	195,46,5,221,225,33,1,0,201,221,33,167,
  9283. -	10,205,93,6,58,184,10,246,1,50,184,10,
  9284. -	58,186,10,135,246,1,50,186,10,58,187,10,
  9285. -	61,50,187,10,194,46,5,221,225,33,2,0,
  9286. -	201,221,229,33,0,0,57,17,4,0,25,126,
  9287. -	50,154,10,230,128,50,189,10,58,189,10,183,
  9288. -	40,6,221,33,88,2,24,4,221,33,150,0,
  9289. -	58,154,10,183,40,49,60,40,46,61,33,190,
  9290. -	10,119,35,119,35,54,129,175,50,158,10,221,
  9291. -	43,221,229,225,124,181,40,42,33,190,10,17,
  9292. -	3,0,205,206,4,17,232,3,27,123,178,32,
  9293. -	251,58,158,10,183,40,224,58,154,10,71,62,
  9294. -	7,128,230,127,71,58,189,10,176,50,154,10,
  9295. -	24,166,221,225,201,183,221,52,0,192,221,52,
  9296. -	1,192,221,52,2,192,221,52,3,192,55,201,
  9297. -	6,8,14,0,31,48,1,12,16,250,121,201,
  9298. -	33,2,0,57,94,35,86,35,78,35,70,35,
  9299. -	126,35,102,105,79,120,68,103,237,176,201,33,
  9300. -	2,0,57,126,35,102,111,62,17,237,57,48,
  9301. -	125,237,57,40,124,237,57,41,62,0,237,57,
  9302. -	42,62,64,237,57,43,62,0,237,57,44,33,
  9303. -	128,2,125,237,57,46,124,237,57,47,62,145,
  9304. -	237,57,48,211,68,58,149,10,211,66,201,33,
  9305. -	2,0,57,126,35,102,111,62,33,237,57,48,
  9306. -	62,64,237,57,32,62,0,237,57,33,237,57,
  9307. -	34,125,237,57,35,124,237,57,36,62,0,237,
  9308. -	57,37,33,128,2,125,237,57,38,124,237,57,
  9309. -	39,62,97,237,57,48,211,67,58,149,10,211,
  9310. -	66,201,237,56,46,95,237,56,47,87,237,56,
  9311. -	46,111,237,56,47,103,183,237,82,32,235,33,
  9312. -	128,2,183,237,82,201,237,56,38,95,237,56,
  9313. -	39,87,237,56,38,111,237,56,39,103,183,237,
  9314. -	82,32,235,33,128,2,183,237,82,201,205,106,
  9315. -	10,221,110,6,221,102,7,126,35,110,103,195,
  9316. -	118,10,205,106,10,33,0,0,34,205,10,34,
  9317. -	198,10,34,200,10,33,143,15,34,207,10,237,
  9318. -	91,207,10,42,146,10,183,237,82,17,0,255,
  9319. -	25,34,203,10,203,124,40,6,33,0,125,34,
  9320. -	203,10,42,207,10,229,205,37,3,195,118,10,
  9321. -	205,106,10,229,42,150,10,35,35,35,229,205,
  9322. -	70,7,193,124,230,3,103,221,117,254,221,116,
  9323. -	255,237,91,152,10,35,35,35,183,237,82,32,
  9324. -	12,17,5,0,42,152,10,205,91,10,242,203,
  9325. -	7,42,150,10,229,205,37,3,195,118,10,237,
  9326. -	91,152,10,42,200,10,25,34,200,10,42,205,
  9327. -	10,25,34,205,10,237,91,203,10,33,158,253,
  9328. -	25,237,91,205,10,205,91,10,242,245,7,33,
  9329. -	0,0,34,205,10,62,1,50,197,10,205,5,
  9330. -	8,33,0,0,57,249,195,118,10,205,106,10,
  9331. -	58,197,10,183,202,118,10,237,91,198,10,42,
  9332. -	205,10,205,91,10,242,46,8,237,91,205,10,
  9333. -	33,98,2,25,237,91,198,10,205,91,10,250,
  9334. -	78,8,237,91,198,10,42,205,10,183,237,82,
  9335. -	32,7,42,200,10,125,180,40,13,237,91,205,
  9336. -	10,42,198,10,205,91,10,242,97,8,237,91,
  9337. -	207,10,42,205,10,25,229,205,37,3,175,50,
  9338. -	197,10,195,118,10,205,29,3,33,0,0,57,
  9339. -	249,195,118,10,205,106,10,58,202,10,183,40,
  9340. -	22,205,14,7,237,91,209,10,19,19,19,205,
  9341. -	91,10,242,139,8,33,1,0,195,118,10,33,
  9342. -	0,0,195,118,10,205,126,10,252,255,205,108,
  9343. -	8,125,180,194,118,10,237,91,200,10,33,0,
  9344. -	0,205,91,10,242,118,10,237,91,207,10,42,
  9345. -	198,10,25,221,117,254,221,116,255,35,35,35,
  9346. -	229,205,70,7,193,124,230,3,103,35,35,35,
  9347. -	221,117,252,221,116,253,229,221,110,254,221,102,
  9348. -	255,229,33,212,10,229,205,124,6,193,193,221,
  9349. -	110,252,221,102,253,34,209,10,33,211,10,54,
  9350. -	4,33,209,10,227,205,147,6,193,62,1,50,
  9351. -	202,10,243,221,94,252,221,86,253,42,200,10,
  9352. -	183,237,82,34,200,10,203,124,40,17,33,0,
  9353. -	0,34,200,10,34,205,10,34,198,10,50,197,
  9354. -	10,24,37,221,94,252,221,86,253,42,198,10,
  9355. -	25,34,198,10,237,91,203,10,33,158,253,25,
  9356. -	237,91,198,10,205,91,10,242,68,9,33,0,
  9357. -	0,34,198,10,205,5,8,33,0,0,57,249,
  9358. -	251,195,118,10,205,106,10,33,49,13,126,183,
  9359. -	40,16,205,42,7,237,91,47,13,19,19,19,
  9360. -	205,91,10,242,117,9,58,142,15,198,1,50,
  9361. -	142,15,195,118,10,33,49,13,126,254,1,40,
  9362. -	25,254,3,202,7,10,254,5,202,21,10,33,
  9363. -	49,13,54,0,33,47,13,229,205,207,6,195,
  9364. -	118,10,58,141,15,183,32,72,33,51,13,126,
  9365. -	50,149,10,205,86,7,33,50,13,126,230,127,
  9366. -	183,32,40,58,142,15,230,127,50,142,15,183,
  9367. -	32,5,198,1,50,142,15,33,50,13,126,111,
  9368. -	23,159,103,203,125,58,142,15,40,5,198,128,
  9369. -	50,142,15,33,50,13,119,33,50,13,126,111,
  9370. -	23,159,103,229,205,237,5,193,33,211,10,54,
  9371. -	2,33,2,0,34,209,10,58,154,10,33,212,
  9372. -	10,119,58,148,10,33,213,10,119,33,209,10,
  9373. -	229,205,147,6,193,24,128,42,47,13,229,33,
  9374. -	50,13,229,205,191,4,193,24,239,33,211,10,
  9375. -	54,6,33,3,0,34,209,10,58,154,10,33,
  9376. -	212,10,119,58,148,10,33,213,10,119,33,214,
  9377. -	10,54,5,33,209,10,229,205,147,6,24,200,
  9378. -	205,106,10,33,49,13,54,0,33,47,13,229,
  9379. -	205,207,6,33,209,10,227,205,147,6,193,205,
  9380. -	80,9,205,145,8,24,248,124,170,250,99,10,
  9381. -	237,82,201,124,230,128,237,82,60,201,225,253,
  9382. -	229,221,229,221,33,0,0,221,57,233,221,249,
  9383. -	221,225,253,225,201,233,225,253,229,221,229,221,
  9384. -	33,0,0,221,57,94,35,86,35,235,57,249,
  9385. -	235,233,0,0,0,0,0,0,0,0,0,0,
  9386. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9387. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9388. -	0,0,0,0,0,0,0,0,0,0,0,0,
  9389. -	0,0,0,0,0
  9390. -	} ;
  9391. -
  9392. -#endif